From 05e74480f59efd71f664d4df82a1d3a1644ee676 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Tue, 20 Aug 2024 13:32:02 +0800 Subject: [PATCH 1/5] feat(esp_system): gate some clock by default to optmize esp32p4 active power --- .../src/esp32p4/bootloader_esp32p4.c | 3 +- .../esp_driver_cam/csi/src/esp_cam_ctlr_csi.c | 6 + components/esp_driver_uart/src/uart.c | 19 +- components/esp_hw_support/CMakeLists.txt | 4 + .../include/esp_private/uart_share_hw_ctrl.h | 2 + .../esp_hw_support/port/esp32c5/io_mux.c | 1 + .../esp_hw_support/port/esp32c6/Kconfig.rtc | 3 + .../esp_hw_support/port/esp32c6/io_mux.c | 1 + .../esp_hw_support/port/esp32h2/Kconfig.rtc | 3 + .../esp_hw_support/port/esp32p4/Kconfig.rtc | 3 + .../esp_hw_support/port/esp32p4/io_mux.c | 39 ++- components/esp_hw_support/port/pau_regdma.c | 11 +- components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c | 4 + components/esp_system/port/cpu_start.c | 3 +- components/esp_system/port/soc/esp32c6/clk.c | 3 + components/esp_system/port/soc/esp32p4/clk.c | 276 ++++++++++++------ components/hal/esp32/include/hal/uart_ll.h | 33 +++ components/hal/esp32c2/include/hal/uart_ll.h | 13 + components/hal/esp32c3/include/hal/uart_ll.h | 13 + components/hal/esp32c5/include/hal/uart_ll.h | 35 +++ components/hal/esp32c6/include/hal/uart_ll.h | 35 +++ components/hal/esp32c61/include/hal/uart_ll.h | 11 + components/hal/esp32h2/include/hal/uart_ll.h | 11 + components/hal/esp32p4/include/hal/adc_ll.h | 1 + components/hal/esp32p4/include/hal/aes_ll.h | 4 +- .../hal/esp32p4/include/hal/assist_debug_ll.h | 9 +- components/hal/esp32p4/include/hal/cam_ll.h | 1 + .../hal/esp32p4/include/hal/clk_tree_ll.h | 4 + components/hal/esp32p4/include/hal/ds_ll.h | 4 +- components/hal/esp32p4/include/hal/ecc_ll.h | 4 +- components/hal/esp32p4/include/hal/etm_ll.h | 4 +- components/hal/esp32p4/include/hal/gdma_ll.h | 4 +- components/hal/esp32p4/include/hal/gpio_ll.h | 1 + components/hal/esp32p4/include/hal/hmac_ll.h | 4 +- components/hal/esp32p4/include/hal/i2s_ll.h | 4 + components/hal/esp32p4/include/hal/isp_ll.h | 2 + components/hal/esp32p4/include/hal/lcd_ll.h | 1 + components/hal/esp32p4/include/hal/ledc_ll.h | 1 + components/hal/esp32p4/include/hal/mcpwm_ll.h | 1 + .../hal/esp32p4/include/hal/mipi_csi_ll.h | 30 +- .../hal/esp32p4/include/hal/mipi_dsi_ll.h | 32 +- components/hal/esp32p4/include/hal/mpi_ll.h | 4 +- .../hal/esp32p4/include/hal/parlio_ll.h | 5 + components/hal/esp32p4/include/hal/pau_ll.h | 6 +- components/hal/esp32p4/include/hal/rmt_ll.h | 1 + .../hal/esp32p4/include/hal/rtc_io_ll.h | 15 + components/hal/esp32p4/include/hal/sdmmc_ll.h | 1 + components/hal/esp32p4/include/hal/sha_ll.h | 4 +- components/hal/esp32p4/include/hal/spi_ll.h | 8 +- .../hal/esp32p4/include/hal/spimem_flash_ll.h | 19 ++ components/hal/esp32p4/include/hal/timer_ll.h | 5 +- components/hal/esp32p4/include/hal/uart_ll.h | 69 ++++- .../esp32p4/include/hal/usb_serial_jtag_ll.h | 4 +- .../hal/esp32p4/include/hal/usb_utmi_ll.h | 4 +- components/hal/esp32s2/include/hal/uart_ll.h | 33 +++ components/hal/esp32s3/include/hal/uart_ll.h | 33 +++ components/hal/include/hal/rtc_io_hal.h | 2 +- .../esp32p4/include/soc/Kconfig.soc_caps.in | 4 + components/soc/esp32p4/include/soc/reg_base.h | 8 +- components/soc/esp32p4/include/soc/soc.h | 1 + components/soc/esp32p4/include/soc/soc_caps.h | 5 +- .../soc/esp32p4/include/soc/trace_reg.h | 52 ++-- .../soc/esp32p4/include/soc/trace_struct.h | 16 +- .../soc/esp32p4/ld/esp32p4.peripherals.ld | 2 + components/ulp/lp_core/lp_core_uart.c | 1 + components/usb/usb_phy_p4.c | 13 +- 66 files changed, 769 insertions(+), 189 deletions(-) diff --git a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c index 9b70bf6817..7b0d9fd68d 100644 --- a/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c +++ b/components/bootloader_support/src/esp32p4/bootloader_esp32p4.c @@ -37,6 +37,7 @@ #include "bootloader_soc.h" #include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" +#include "hal/assist_debug_ll.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" #include "hal/clk_tree_ll.h" @@ -55,7 +56,7 @@ static const char *TAG = "boot.esp32p4"; static void wdt_reset_cpu0_info_enable(void) { - //TODO: IDF-7688 + _assist_debug_ll_enable_bus_clock(true); REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN); } diff --git a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c index ebfcdb3fcc..49aee4a745 100644 --- a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c +++ b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c @@ -63,7 +63,11 @@ static esp_err_t s_csi_claim_controller(csi_controller_t *controller) controller->csi_id = i; PERIPH_RCC_ATOMIC() { mipi_csi_ll_enable_host_bus_clock(i, 0); + mipi_csi_ll_enable_host_clock(i, 0); + mipi_csi_ll_enable_host_config_clock(i, 0); mipi_csi_ll_enable_host_bus_clock(i, 1); + mipi_csi_ll_enable_host_clock(i, 1); + mipi_csi_ll_enable_host_config_clock(i, 1); mipi_csi_ll_reset_host_clock(i); } break; @@ -85,6 +89,8 @@ static esp_err_t s_csi_declaim_controller(csi_controller_t *controller) s_platform.controllers[controller->csi_id] = NULL; PERIPH_RCC_ATOMIC() { mipi_csi_ll_enable_host_bus_clock(controller->csi_id, 0); + mipi_csi_ll_enable_host_clock(controller->csi_id, 0); + mipi_csi_ll_enable_host_config_clock(controller->csi_id, 0); } _lock_release(&s_platform.mutex); diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 03f9c1bffd..ebd7ee92d4 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -71,6 +71,7 @@ static const char *UART_TAG = "uart"; #if (SOC_UART_LP_NUM >= 1) #define UART_THRESHOLD_NUM(uart_num, field_name) ((uart_num < SOC_UART_HP_NUM) ? field_name : LP_##field_name) +#define TO_LP_UART_NUM(uart_num) (uart_num - SOC_UART_HP_NUM) #else #define UART_THRESHOLD_NUM(uart_num, field_name) (field_name) #endif @@ -209,6 +210,9 @@ static void uart_module_enable(uart_port_t uart_num) HP_UART_BUS_CLK_ATOMIC() { uart_ll_reset_register(uart_num); } + HP_UART_SRC_CLK_ATOMIC() { + uart_ll_sclk_enable(uart_context[uart_num].hal.dev); + } } #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP @@ -236,9 +240,10 @@ static void uart_module_enable(uart_port_t uart_num) #if (SOC_UART_LP_NUM >= 1) else { LP_UART_BUS_CLK_ATOMIC() { - lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, true); - lp_uart_ll_reset_register(uart_num - SOC_UART_HP_NUM); + lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), true); + lp_uart_ll_reset_register(TO_LP_UART_NUM(uart_num)); } + lp_uart_ll_sclk_enable(TO_LP_UART_NUM(uart_num)); } #endif uart_context[uart_num].hw_enabled = true; @@ -260,15 +265,18 @@ static void uart_module_disable(uart_port_t uart_num) uart_context[uart_num].retention_link_inited = false; } #endif - + HP_UART_SRC_CLK_ATOMIC() { + uart_ll_sclk_disable(uart_context[uart_num].hal.dev); + } HP_UART_BUS_CLK_ATOMIC() { uart_ll_enable_bus_clock(uart_num, false); } } #if (SOC_UART_LP_NUM >= 1) else if (uart_num >= SOC_UART_HP_NUM) { + lp_uart_ll_sclk_disable(TO_LP_UART_NUM(uart_num)); LP_UART_BUS_CLK_ATOMIC() { - lp_uart_ll_enable_bus_clock(uart_num - SOC_UART_HP_NUM, false); + lp_uart_ll_enable_bus_clock(TO_LP_UART_NUM(uart_num), false); } } #endif @@ -1922,6 +1930,9 @@ esp_err_t uart_set_wakeup_threshold(uart_port_t uart_num, int wakeup_threshold) "wakeup_threshold out of bounds"); UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_set_wakeup_thrd(&(uart_context[uart_num].hal), wakeup_threshold); + HP_UART_PAD_CLK_ATOMIC() { + uart_ll_enable_pad_sleep_clock(uart_context[uart_num].hal.dev, true); + } UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); return ESP_OK; } diff --git a/components/esp_hw_support/CMakeLists.txt b/components/esp_hw_support/CMakeLists.txt index 4abb2814c3..535470f8c2 100644 --- a/components/esp_hw_support/CMakeLists.txt +++ b/components/esp_hw_support/CMakeLists.txt @@ -17,6 +17,10 @@ if(${target} STREQUAL "esp32c6") list(APPEND priv_requires hal) endif() +if(CONFIG_RTC_CLK_SRC_INT_RC32K) + message(WARNING "Internal RC32K clock is unstable at extreme temperatures and is not recommended for use.") +endif() + set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c") if(NOT BOOTLOADER_BUILD) list(APPEND srcs "esp_clk.c" diff --git a/components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h b/components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h index e132593b1e..dbeef427d5 100644 --- a/components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h +++ b/components/esp_hw_support/include/esp_private/uart_share_hw_ctrl.h @@ -22,8 +22,10 @@ extern "C" { #if SOC_RCC_IS_INDEPENDENT #define HP_UART_BUS_CLK_ATOMIC() +#define HP_UART_PAD_CLK_ATOMIC() #else #define HP_UART_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC() +#define HP_UART_PAD_CLK_ATOMIC() PERIPH_RCC_ATOMIC() #endif #if (SOC_UART_LP_NUM >= 1) diff --git a/components/esp_hw_support/port/esp32c5/io_mux.c b/components/esp_hw_support/port/esp32c5/io_mux.c index e8fb906555..83f2e29c4a 100644 --- a/components/esp_hw_support/port/esp32c5/io_mux.c +++ b/components/esp_hw_support/port/esp32c5/io_mux.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "freertos/FreeRTOS.h" #include "esp_private/io_mux.h" #include "esp_private/periph_ctrl.h" diff --git a/components/esp_hw_support/port/esp32c6/Kconfig.rtc b/components/esp_hw_support/port/esp32c6/Kconfig.rtc index b02d6e6cc0..c60027fa76 100644 --- a/components/esp_hw_support/port/esp32c6/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32c6/Kconfig.rtc @@ -14,6 +14,9 @@ choice RTC_CLK_SRC select ESP_SYSTEM_RTC_EXT_OSC config RTC_CLK_SRC_INT_RC32K bool "Internal 32 kHz RC oscillator" + help + Internal RC32K clock is unstable at extreme temperatures and is not recommended for use. + This option will be removed in IDF v6.0. endchoice config RTC_CLK_CAL_CYCLES diff --git a/components/esp_hw_support/port/esp32c6/io_mux.c b/components/esp_hw_support/port/esp32c6/io_mux.c index bd164ce683..eae8b2d771 100644 --- a/components/esp_hw_support/port/esp32c6/io_mux.c +++ b/components/esp_hw_support/port/esp32c6/io_mux.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" #include "esp_attr.h" #include "freertos/FreeRTOS.h" #include "esp_private/io_mux.h" diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.rtc b/components/esp_hw_support/port/esp32h2/Kconfig.rtc index b02d6e6cc0..c60027fa76 100644 --- a/components/esp_hw_support/port/esp32h2/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32h2/Kconfig.rtc @@ -14,6 +14,9 @@ choice RTC_CLK_SRC select ESP_SYSTEM_RTC_EXT_OSC config RTC_CLK_SRC_INT_RC32K bool "Internal 32 kHz RC oscillator" + help + Internal RC32K clock is unstable at extreme temperatures and is not recommended for use. + This option will be removed in IDF v6.0. endchoice config RTC_CLK_CAL_CYCLES diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.rtc b/components/esp_hw_support/port/esp32p4/Kconfig.rtc index 19541352ab..8c56a77f77 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.rtc +++ b/components/esp_hw_support/port/esp32p4/Kconfig.rtc @@ -11,6 +11,9 @@ choice RTC_CLK_SRC select ESP_SYSTEM_RTC_EXT_XTAL config RTC_CLK_SRC_INT_RC32K bool "Internal 32 kHz RC oscillator" + help + Internal RC32K clock is unstable at extreme temperatures and is not recommended for use. + This option will be removed in IDF v6.0. endchoice config RTC_CLK_CAL_CYCLES diff --git a/components/esp_hw_support/port/esp32p4/io_mux.c b/components/esp_hw_support/port/esp32p4/io_mux.c index 10e021aba0..5f3bf951ab 100644 --- a/components/esp_hw_support/port/esp32p4/io_mux.c +++ b/components/esp_hw_support/port/esp32p4/io_mux.c @@ -1,17 +1,30 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" +#include "esp_attr.h" #include "freertos/FreeRTOS.h" #include "esp_private/io_mux.h" #include "esp_private/periph_ctrl.h" #include "hal/gpio_ll.h" +#include "hal/rtc_io_ll.h" + +#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC() static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED; static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter) +#if CONFIG_ULP_COPROC_ENABLED +RTC_DATA_ATTR +#endif +static rtc_io_status_t s_rtc_io_status = { + .rtc_io_enabled_cnt = { 0 }, + .rtc_io_using_mask = 0 +}; + esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) { bool clk_conflict = false; @@ -32,3 +45,27 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) } return ESP_OK; } + +void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable) +{ + portENTER_CRITICAL(&s_io_mux_spinlock); + if (enable) { + if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) { + s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num); + } + s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++; + } else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) { + s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--; + if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) { + s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num); + } + } + RTCIO_RCC_ATOMIC() { + if (s_rtc_io_status.rtc_io_using_mask == 0) { + rtcio_ll_enable_io_clock(false); + } else { + rtcio_ll_enable_io_clock(true); + } + } + portEXIT_CRITICAL(&s_io_mux_spinlock); +} diff --git a/components/esp_hw_support/port/pau_regdma.c b/components/esp_hw_support/port/pau_regdma.c index 2f54f0c6a1..40696e33e8 100644 --- a/components/esp_hw_support/port/pau_regdma.c +++ b/components/esp_hw_support/port/pau_regdma.c @@ -25,6 +25,13 @@ static __attribute__((unused)) const char *TAG = "pau_regdma"; +#if !SOC_RCC_IS_INDEPENDENT +// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section +#define PAU_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define PAU_RCC_ATOMIC() +#endif + typedef struct { pau_hal_context_t *hal; } pau_context_t; @@ -39,7 +46,9 @@ pau_context_t * __attribute__((weak)) IRAM_ATTR PAU_instance(void) if (pau_hal.dev == NULL) { pau_hal.dev = &PAU; - pau_hal_enable_bus_clock(true); + PAU_RCC_ATOMIC() { + pau_hal_enable_bus_clock(true); + } pau_hal_set_regdma_wait_timeout(&pau_hal, PAU_REGDMA_LINK_WAIT_RETRY_COUNT, PAU_REGDMA_LINK_WAIT_READ_INTERNAL); pau_hal_set_regdma_work_timeout(&pau_hal, PAU_REGDMA_LINK_LOOP, PAU_REGDMA_REG_ACCESS_TIME); #if SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c index 7fa3e1dc94..ca519162d6 100644 --- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c +++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c @@ -39,6 +39,8 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc // Enable the APB clock for accessing the DSI host and bridge registers DSI_RCC_ATOMIC() { mipi_dsi_ll_enable_bus_clock(bus_id, true); + mipi_dsi_ll_enable_host_clock(bus_id, true); + mipi_dsi_ll_enable_host_config_clock(bus_id, true); mipi_dsi_ll_reset_register(bus_id); } @@ -140,6 +142,8 @@ esp_err_t esp_lcd_del_dsi_bus(esp_lcd_dsi_bus_handle_t bus) // disable the APB clock for accessing the DSI peripheral registers DSI_RCC_ATOMIC() { mipi_dsi_ll_enable_bus_clock(bus_id, false); + mipi_dsi_ll_enable_host_clock(bus_id, false); + mipi_dsi_ll_enable_host_config_clock(bus_id, false); } if (bus->pm_lock) { esp_pm_lock_release(bus->pm_lock); diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 1e328d472d..0edd50c156 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -228,7 +228,8 @@ void IRAM_ATTR call_start_cpu1(void) DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE); DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE); #elif CONFIG_IDF_TARGET_ESP32P4 - //TODO: IDF-7688 + REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_PDEBUGEN); + REG_SET_BIT(ASSIST_DEBUG_CORE_1_RCD_EN_REG, ASSIST_DEBUG_CORE_1_RCD_RECORDEN); #else REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG, 1); REG_WRITE(ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG, 1); diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 42a2f8f00a..6ac2ff9553 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -234,7 +234,9 @@ __attribute__((weak)) void esp_perip_clk_init(void) && (rst_reason != RESET_REASON_CPU0_JTAG)) { #if CONFIG_ESP_CONSOLE_UART_NUM != 0 uart_ll_enable_bus_clock(UART_NUM_0, false); + uart_ll_sclk_disable(&UART0); #elif CONFIG_ESP_CONSOLE_UART_NUM != 1 + uart_ll_sclk_disable(&UART1); uart_ll_enable_bus_clock(UART_NUM_1, false); #endif i2c_ll_enable_bus_clock(0, false); @@ -305,6 +307,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) { _lp_i2c_ll_enable_bus_clock(0, false); _lp_uart_ll_enable_bus_clock(0, false); + lp_uart_ll_sclk_disable(0); lp_core_ll_enable_bus_clock(false); _lp_clkrst_ll_enable_rng_clock(false); diff --git a/components/esp_system/port/soc/esp32p4/clk.c b/components/esp_system/port/soc/esp32p4/clk.c index a526cef6dc..d715fc7fa9 100644 --- a/components/esp_system/port/soc/esp32p4/clk.c +++ b/components/esp_system/port/soc/esp32p4/clk.c @@ -21,7 +21,40 @@ #include "soc/i2s_reg.h" #include "soc/hp_sys_clkrst_reg.h" #include "esp_cpu.h" +#include "mspi_timing_tuning_configs.h" + +#include "soc/hp_sys_clkrst_reg.h" +#include "soc/lp_clkrst_reg.h" +#include "soc/lp_system_reg.h" +#include "soc/sdmmc_reg.h" +#include "soc/spi_mem_c_reg.h" +#include "soc/spi_mem_s_reg.h" +#include "soc/usb_serial_jtag_reg.h" +#include "soc/trace_struct.h" + +#include "hal/aes_ll.h" +#include "hal/assist_debug_ll.h" +#include "hal/ds_ll.h" +#include "hal/ecc_ll.h" +#include "hal/etm_ll.h" +#include "hal/gdma_ll.h" +#include "hal/hmac_ll.h" +#include "hal/mipi_csi_ll.h" +#include "hal/mipi_dsi_brg_ll.h" +#include "hal/mpi_ll.h" +#include "hal/pau_ll.h" +#include "hal/parlio_ll.h" +#include "hal/psram_ctrlr_ll.h" +#include "hal/rtc_io_ll.h" +#include "hal/sha_ll.h" +#include "hal/spi_ll.h" +#include "hal/spimem_flash_ll.h" +#include "hal/timer_ll.h" +#include "hal/uart_ll.h" +#include "hal/usb_serial_jtag_ll.h" +#include "hal/usb_utmi_ll.h" #include "hal/wdt_hal.h" + #include "esp_private/esp_modem_clock.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" @@ -177,115 +210,164 @@ __attribute__((weak)) void esp_perip_clk_init(void) { soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); - if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); - esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_ON); - // RC slow (150K) always ON + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_XTAL_32K_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_RC_32K_CLK_EN); + esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); // RC slow (150K) always ON - } else { - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_AUTO); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_RC_32K_CLK_EN); + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_ON); + } else if (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC32K) { + // RC slow (150K) always ON + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL32K, ESP_PD_OPTION_AUTO); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_XTAL_32K_CLK_EN); + esp_sleep_pd_config(ESP_PD_DOMAIN_RC32K, ESP_PD_OPTION_ON); } - ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); -#if 0 // TODO: IDF-5658 - uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; - uint32_t common_perip_clk1 = 0; - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + if ((rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU_MWDT) \ + && (rst_reason != RESET_REASON_CPU_RWDT) && (rst_reason != RESET_REASON_CPU_JTAG) \ + && (rst_reason != RESET_REASON_CPU_LOCKUP)) { + _gdma_ll_enable_bus_clock(0, false); + _gdma_ll_enable_bus_clock(1, false); + _pau_ll_enable_bus_clock(false); + _parlio_ll_enable_bus_clock(0, false); + _etm_ll_enable_bus_clock(0, false); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN); - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || - rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) { - common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); - wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); - } else { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | +// Non-Console UART #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | + _uart_ll_enable_bus_clock(UART_NUM_0, false); + _uart_ll_sclk_disable(&UART0); +#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 + _uart_ll_enable_bus_clock(UART_NUM_1, false); + _uart_ll_sclk_disable(&UART1); #endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; + _uart_ll_enable_bus_clock(UART_NUM_2, false); + _uart_ll_sclk_disable(&UART2); + _uart_ll_enable_bus_clock(UART_NUM_3, false); + _uart_ll_sclk_disable(&UART3); + _uart_ll_enable_bus_clock(UART_NUM_4, false); + _uart_ll_sclk_disable(&UART4); - common_perip_clk1 = 0; - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | - SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_UNUSED_BIT5 | - SYSTEM_WIFI_CLK_UNUSED_BIT12; + _timer_ll_enable_bus_clock(0, false); + _timer_ll_enable_clock(&TIMERG0, 0, false); + _timer_ll_enable_clock(&TIMERG0, 1, false); + + _timer_ll_enable_bus_clock(1, false); + _timer_ll_enable_clock(&TIMERG1, 0, false); + _timer_ll_enable_clock(&TIMERG1, 1, false); + + mipi_dsi_brg_ll_enable_ref_clock(&MIPI_DSI_BRIDGE, false); + _mipi_csi_ll_enable_host_bus_clock(0, false); + + REG_CLR_BIT(SDHOST_CLK_EDGE_SEL_REG, SDHOST_CCLK_EN); + +#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + _spimem_ctrlr_ll_unset_clock(0); +#endif + +#if !MSPI_TIMING_FLASH_NEEDS_TUNING + REG_CLR_BIT(SPI_MEM_C_TIMING_CALI_REG, SPI_MEM_C_TIMING_CLK_ENA); + REG_CLR_BIT(SPI_MEM_C_SMEM_TIMING_CALI_REG, SPI_MEM_C_SMEM_TIMING_CLK_ENA); +#endif + +#if !MSPI_TIMING_PSRAM_NEEDS_TUNING + REG_CLR_BIT(SPI_MEM_S_TIMING_CALI_REG, SPI_MEM_S_TIMING_CLK_ENA); + REG_CLR_BIT(SPI_MEM_S_SMEM_TIMING_CALI_REG, SPI_MEM_S_SMEM_TIMING_CLK_ENA); +#endif + +#if !CONFIG_SPIRAM + _psram_ctrlr_ll_enable_core_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); + _psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false); +#endif + + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN); + // 240M CLK is for Key Management use, should not be gated + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN); + + _spi_ll_enable_bus_clock(SPI2_HOST, false); + _spi_ll_enable_bus_clock(SPI3_HOST, false); + _spi_ll_enable_clock(SPI2_HOST, false); + _spi_ll_enable_clock(SPI3_HOST, false); + +#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD + /* Disable ASSIST Debug module clock if PC recoreding function is not used, + * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ + _assist_debug_ll_enable_bus_clock(false); +#endif + // Trace & Bus Monitor (0) + TRACE0.clock_gate.clk_en = 0; + TRACE1.clock_gate.clk_en = 0; + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_L2MEMMON_MEM_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_L2MEMMON_SYS_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN); + + // Crypto Modules + _aes_ll_enable_bus_clock(false); + _ds_ll_enable_bus_clock(false); + _ecc_ll_enable_bus_clock(false); + _hmac_ll_enable_bus_clock(false); + _mpi_ll_enable_bus_clock(false); + _sha_ll_enable_bus_clock(false); + + // USB1.1 + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG11_BK_SYS_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG11_48M_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_USB_OTG11_SYS_CLK_EN); + // USB2.0 + _usb_utmi_ll_enable_bus_clock(false); + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL0_REG, LP_CLKRST_USB_OTG20_BK_SYS_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_USB_CLKRST_CTRL1_REG, LP_CLKRST_USB_OTG20_ULPI_CLK_EN); + // UHCI + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN); + REG_CLR_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN); + +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + // Disable USB-Serial-JTAG clock and it's pad if not used + usb_serial_jtag_ll_phy_enable_pad(false); + _usb_serial_jtag_ll_enable_bus_clock(false); + REG_SET_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_PD); + REG_CLR_BIT(USB_SERIAL_JTAG_MEM_CONF_REG, USB_SERIAL_JTAG_USB_MEM_CLK_EN); +#endif } - //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. - common_perip_clk |= SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; - - /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, - * the current is not reduced when disable I2S clock. - */ - // TOCK(check replacement) - // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - - /* Disable some peripheral clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); - - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); - - /* Disable hardware crypto clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); - - /* Disable WiFi/BT/SDIO clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); - SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); - - /* Set WiFi light sleep clock source to RTC slow clock */ - REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); - CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW); - SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); - - /* Enable RNG clock. */ - periph_module_enable(PERIPH_RNG_MODULE); + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ + || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) { + _lp_uart_ll_enable_bus_clock(0, false); + lp_uart_ll_sclk_disable(0); + _rtcio_ll_enable_io_clock(false); + // LP_Peri & Clock Control + _uart_ll_enable_pad_sleep_clock(&UART0, false); + _uart_ll_enable_pad_sleep_clock(&UART1, false); + _uart_ll_enable_pad_sleep_clock(&UART2, false); + _uart_ll_enable_pad_sleep_clock(&UART3, false); + _uart_ll_enable_pad_sleep_clock(&UART4, false); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_TX_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_PARLIO_RX_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S2_MCLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S1_MCLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_I2S0_MCLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TX_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_RX_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PAD_EMAC_TXRX_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_PLL_8M_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL2_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL1_CLK_EN); + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_SDIO_PLL0_CLK_EN); +#if !CONFIG_SPIRAM_BOOT_INIT + REG_CLR_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN); #endif + REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN); + } } diff --git a/components/hal/esp32/include/hal/uart_ll.h b/components/hal/esp32/include/hal/uart_ll.h index 02134517e7..4c66c7bc49 100644 --- a/components/hal/esp32/include/hal/uart_ll.h +++ b/components/hal/esp32/include/hal/uart_ll.h @@ -131,6 +131,26 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +{ + (void)hw; +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +{ + (void)hw; +} + /** * @brief Set the UART source clock. * @@ -697,6 +717,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf.active_threshold = wakeup_thrd - (UART_LL_MIN_WAKEUP_THRESH - 1); } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index 7c5e3d12ed..157d2e2cb3 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -679,6 +679,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index f9f00ad85a..fd7aa05de0 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -682,6 +682,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index afbdab2cf6..7bc6606bc9 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -189,6 +189,30 @@ static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) /// LPPERI.clk_en is a shared register, so this function must be used in an atomic way #define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__) +/** + * @brief Enable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_enable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 1; + LP_UART.clk_conf.rx_sclk_en = 1; +} + +/** + * @brief Disable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_disable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 0; + LP_UART.clk_conf.rx_sclk_en = 0; +} + /** * @brief Reset LP UART module * @@ -894,6 +918,17 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32c6/include/hal/uart_ll.h b/components/hal/esp32c6/include/hal/uart_ll.h index cbbf308bdc..653fb37bbc 100644 --- a/components/hal/esp32c6/include/hal/uart_ll.h +++ b/components/hal/esp32c6/include/hal/uart_ll.h @@ -189,6 +189,30 @@ static inline void _lp_uart_ll_enable_bus_clock(int hw_id, bool enable) /// LPPERI.clk_en is a shared register, so this function must be used in an atomic way #define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_uart_ll_enable_bus_clock(__VA_ARGS__) +/** + * @brief Enable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_enable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 1; + LP_UART.clk_conf.rx_sclk_en = 1; +} + +/** + * @brief Disable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_disable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 0; + LP_UART.clk_conf.rx_sclk_en = 0; +} + /** * @brief Reset LP UART module * @@ -875,6 +899,17 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32c61/include/hal/uart_ll.h b/components/hal/esp32c61/include/hal/uart_ll.h index c12c9ecc75..f6599d94bd 100644 --- a/components/hal/esp32c61/include/hal/uart_ll.h +++ b/components/hal/esp32c61/include/hal/uart_ll.h @@ -741,6 +741,17 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index 14cbbfb14f..4fa29d216f 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -725,6 +725,17 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h index 881cfd0c63..fb08fa93d9 100644 --- a/components/hal/esp32p4/include/hal/adc_ll.h +++ b/components/hal/esp32p4/include/hal/adc_ll.h @@ -223,6 +223,7 @@ static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1; break; case ADC_DIGI_CLK_SRC_PLL_F80M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/aes_ll.h b/components/hal/esp32p4/include/hal/aes_ll.h index befdbe4c6d..c98ac4651b 100644 --- a/components/hal/esp32p4/include/hal/aes_ll.h +++ b/components/hal/esp32p4/include/hal/aes_ll.h @@ -31,14 +31,14 @@ typedef enum { * * @param enable true to enable the module, false to disable the module */ -static inline void aes_ll_enable_bus_clock(bool enable) +static inline void _aes_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_aes_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define aes_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; aes_ll_enable_bus_clock(__VA_ARGS__) +#define aes_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _aes_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the AES peripheral module diff --git a/components/hal/esp32p4/include/hal/assist_debug_ll.h b/components/hal/esp32p4/include/hal/assist_debug_ll.h index 34f6bb6c01..e22eef7463 100644 --- a/components/hal/esp32p4/include/hal/assist_debug_ll.h +++ b/components/hal/esp32p4/include/hal/assist_debug_ll.h @@ -114,14 +114,15 @@ FORCE_INLINE_ATTR uint32_t assist_debug_ll_sp_spill_get_pc(uint32_t core_id) return REG_READ(core_id ? ASSIST_DEBUG_CORE_1_SP_PC_REG : ASSIST_DEBUG_CORE_0_SP_PC_REG); } -FORCE_INLINE_ATTR void assist_debug_ll_enable_bus_clock(bool enable) +FORCE_INLINE_ATTR void _assist_debug_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.soc_clk_ctrl0.reg_busmon_cpu_clk_en = enable; + REG_SET_FIELD(ASSIST_DEBUG_CLOCK_GATE_REG, ASSIST_DEBUG_CLK_EN, enable); } #define assist_debug_ll_enable_bus_clock(...) \ - (void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_enable_bus_clock(__VA_ARGS__) + (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_enable_bus_clock(__VA_ARGS__) -FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void) +FORCE_INLINE_ATTR void _assist_debug_ll_reset_register(void) { /* esp32p4 has no assist_debug reset register: disable & clear interrupts manually. */ for (int i = 0; i < CONFIG_SOC_CPU_CORES_NUM; i++) { @@ -134,7 +135,7 @@ FORCE_INLINE_ATTR void assist_debug_ll_reset_register(void) } } #define assist_debug_ll_reset_register(...) \ - (void)__DECLARE_RCC_ATOMIC_ENV; assist_debug_ll_reset_register(__VA_ARGS__) + (void)__DECLARE_RCC_ATOMIC_ENV; _assist_debug_ll_reset_register(__VA_ARGS__) #ifdef __cplusplus } diff --git a/components/hal/esp32p4/include/hal/cam_ll.h b/components/hal/esp32p4/include/hal/cam_ll.h index a48dba2dc8..638b8f7ba5 100644 --- a/components/hal/esp32p4/include/hal/cam_ll.h +++ b/components/hal/esp32p4/include/hal/cam_ll.h @@ -96,6 +96,7 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src) HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 0; break; case CAM_CLK_SRC_PLL160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 1; break; case CAM_CLK_SRC_APLL: diff --git a/components/hal/esp32p4/include/hal/clk_tree_ll.h b/components/hal/esp32p4/include/hal/clk_tree_ll.h index 80f3979752..3a6ad12024 100644 --- a/components/hal/esp32p4/include/hal/clk_tree_ll.h +++ b/components/hal/esp32p4/include/hal/clk_tree_ll.h @@ -13,6 +13,7 @@ #include "soc/clk_tree_defs.h" #include "soc/hp_sys_clkrst_reg.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_clkrst_reg.h" #include "soc/lp_clkrst_struct.h" #include "soc/pmu_reg.h" #include "hal/regi2c_ctrl.h" @@ -114,6 +115,7 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void) */ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) { + SET_PERI_REG_MASK(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN); SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_APLL | PMU_TIE_HIGH_XPD_APLL_I2C); SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_APLL_ICG); } @@ -123,6 +125,7 @@ static inline __attribute__((always_inline)) void clk_ll_apll_enable(void) */ static inline __attribute__((always_inline)) void clk_ll_apll_disable(void) { + CLEAR_PERI_REG_MASK(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_AUDIO_PLL_CLK_EN); SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_APLL_ICG) ; SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_APLL | PMU_TIE_LOW_XPD_APLL_I2C); } @@ -151,6 +154,7 @@ static inline __attribute__((always_inline)) void clk_ll_lp_pll_disable(void) static inline __attribute__((always_inline)) void clk_ll_mpll_enable(void) { REG_SET_BIT(PMU_RF_PWC_REG, PMU_MSPI_PHY_XPD); + REG_SET_BIT(LP_CLKRST_HP_CLK_CTRL_REG, LP_CLKRST_HP_MPLL_500M_CLK_EN); } /** diff --git a/components/hal/esp32p4/include/hal/ds_ll.h b/components/hal/esp32p4/include/hal/ds_ll.h index 0d362d259e..1ec56ea45f 100644 --- a/components/hal/esp32p4/include/hal/ds_ll.h +++ b/components/hal/esp32p4/include/hal/ds_ll.h @@ -30,14 +30,14 @@ extern "C" { * * @param true to enable the module, false to disable the module */ -static inline void ds_ll_enable_bus_clock(bool enable) +static inline void _ds_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_ds_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define ds_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ds_ll_enable_bus_clock(__VA_ARGS__) +#define ds_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _ds_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the DS peripheral module diff --git a/components/hal/esp32p4/include/hal/ecc_ll.h b/components/hal/esp32p4/include/hal/ecc_ll.h index 92d747afbc..880df25246 100644 --- a/components/hal/esp32p4/include/hal/ecc_ll.h +++ b/components/hal/esp32p4/include/hal/ecc_ll.h @@ -30,14 +30,14 @@ typedef enum { * * @param true to enable the module, false to disable the module */ -static inline void ecc_ll_enable_bus_clock(bool enable) +static inline void _ecc_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_ecc_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define ecc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ecc_ll_enable_bus_clock(__VA_ARGS__) +#define ecc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _ecc_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the ECC peripheral module diff --git a/components/hal/esp32p4/include/hal/etm_ll.h b/components/hal/esp32p4/include/hal/etm_ll.h index 50ef1a91e7..d4f1293475 100644 --- a/components/hal/esp32p4/include/hal/etm_ll.h +++ b/components/hal/esp32p4/include/hal/etm_ll.h @@ -26,7 +26,7 @@ extern "C" { * @param group_id Group ID * @param enable true to enable, false to disable */ -static inline void etm_ll_enable_bus_clock(int group_id, bool enable) +static inline void _etm_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; HP_SYS_CLKRST.soc_clk_ctrl3.reg_etm_apb_clk_en = enable; @@ -35,7 +35,7 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_enable_bus_clock(__VA_ARGS__) +#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _etm_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the ETM module diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index f058a9af7c..055b643664 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -95,7 +95,7 @@ extern "C" { /** * @brief Enable the bus clock for the DMA module */ -static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) +static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable) { if (group_id == 0) { HP_SYS_CLKRST.soc_clk_ctrl1.reg_ahb_pdma_sys_clk_en = enable; @@ -106,7 +106,7 @@ static inline void gdma_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; gdma_ll_enable_bus_clock(__VA_ARGS__) +#define gdma_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _gdma_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the DMA module diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index 094cf73cb2..56f6d4d514 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -637,6 +637,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 0; break; case SOC_MOD_CLK_PLL_F80M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 1; break; default: diff --git a/components/hal/esp32p4/include/hal/hmac_ll.h b/components/hal/esp32p4/include/hal/hmac_ll.h index b812350cfa..dd1eb55619 100644 --- a/components/hal/esp32p4/include/hal/hmac_ll.h +++ b/components/hal/esp32p4/include/hal/hmac_ll.h @@ -37,14 +37,14 @@ extern "C" { * * @param true to enable the module, false to disable the module */ -static inline void hmac_ll_enable_bus_clock(bool enable) +static inline void _hmac_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_hmac_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define hmac_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; hmac_ll_enable_bus_clock(__VA_ARGS__) +#define hmac_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _hmac_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the HMAC peripheral module diff --git a/components/hal/esp32p4/include/hal/i2s_ll.h b/components/hal/esp32p4/include/hal/i2s_ll.h index a9009a0b94..cfb2f2d7c6 100644 --- a/components/hal/esp32p4/include/hal/i2s_ll.h +++ b/components/hal/esp32p4/include/hal/i2s_ll.h @@ -19,6 +19,7 @@ #include "soc/i2s_struct.h" #include "soc/soc_etm_struct.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_clkrst_struct.h" #include "soc/soc_etm_source.h" #include "hal/i2s_types.h" #include "hal/hal_utils.h" @@ -122,12 +123,15 @@ static inline void i2s_ll_enable_bus_clock(int i2s_id, bool enable) switch (i2s_id) { case 0: HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s0_apb_clk_en = enable; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s0_mclk_en = enable; return; case 1: HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s1_apb_clk_en = enable; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s1_mclk_en = enable; return; case 2: HP_SYS_CLKRST.soc_clk_ctrl2.reg_i2s2_apb_clk_en = enable; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_i2s2_mclk_en = enable; return; } } diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index dcbf678933..1f96086bac 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -198,9 +198,11 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr clk_val = 0; break; case ISP_CLK_SRC_PLL160: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_val = 1; break; case ISP_CLK_SRC_PLL240: + HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_240m_clk_en = 1; clk_val = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/lcd_ll.h b/components/hal/esp32p4/include/hal/lcd_ll.h index 99e41cfc68..e10f8c8eee 100644 --- a/components/hal/esp32p4/include/hal/lcd_ll.h +++ b/components/hal/esp32p4/include/hal/lcd_ll.h @@ -102,6 +102,7 @@ static inline void lcd_ll_select_clk_src(lcd_cam_dev_t *dev, lcd_clock_source_t HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 0; break; case LCD_CLK_SRC_PLL160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 1; break; case LCD_CLK_SRC_APLL: diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index dea593b889..8d13cc6ee3 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -103,6 +103,7 @@ static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t clk_sel_val = 1; break; case LEDC_SLOW_CLK_PLL_DIV: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; clk_sel_val = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mcpwm_ll.h b/components/hal/esp32p4/include/hal/mcpwm_ll.h index 4031c06070..870f7ef23e 100644 --- a/components/hal/esp32p4/include/hal/mcpwm_ll.h +++ b/components/hal/esp32p4/include/hal/mcpwm_ll.h @@ -168,6 +168,7 @@ static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_ clk_id = 1; break; case SOC_MOD_CLK_PLL_F160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_id = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mipi_csi_ll.h b/components/hal/esp32p4/include/hal/mipi_csi_ll.h index eadcd22ace..9c007b8884 100644 --- a/components/hal/esp32p4/include/hal/mipi_csi_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_csi_ll.h @@ -69,12 +69,14 @@ static inline void mipi_csi_ll_set_phy_clock_source(int group_id, mipi_csi_phy_c (void)group_id; switch (source) { case MIPI_CSI_PHY_CLK_SRC_PLL_F20M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 0; break; case MIPI_CSI_PHY_CLK_SRC_RC_FAST: HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 1; break; case MIPI_CSI_PHY_CLK_SRC_PLL_F25M: + HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 2; break; default: @@ -111,7 +113,7 @@ static inline void mipi_csi_ll_enable_phy_config_clock(int group_id, bool en) * @param group_id Group ID * @param en true to enable, false to disable */ -static inline void mipi_csi_ll_enable_host_bus_clock(int group_id, bool en) +static inline void _mipi_csi_ll_enable_host_bus_clock(int group_id, bool en) { (void)group_id; HP_SYS_CLKRST.soc_clk_ctrl1.reg_csi_host_sys_clk_en = en; @@ -119,7 +121,31 @@ static inline void mipi_csi_ll_enable_host_bus_clock(int group_id, bool en) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__) +#define mipi_csi_ll_enable_host_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_csi_ll_enable_host_bus_clock(__VA_ARGS__) + +/** + * @brief Enable the clock for MIPI CSI host + * + * @param group_id Group ID + * @param en true to enable, false to disable + */ +static inline void mipi_csi_ll_enable_host_clock(int group_id, bool en) +{ + (void)group_id; + MIPI_CSI_BRIDGE.host_ctrl.csi_enableclk = en; +} + +/** + * @brief Enable the config clock for MIPI CSI host + * + * @param group_id Group ID + * @param en true to enable, false to disable + */ +static inline void mipi_csi_ll_enable_host_config_clock(int group_id, bool en) +{ + (void)group_id; + MIPI_CSI_BRIDGE.host_ctrl.csi_cfg_clk_en = en; +} /** * @brief Reset the MIPI CSI host CLK diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h index e876817684..2021c636cc 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h @@ -27,7 +27,7 @@ extern "C" { * @param group_id Group ID * @param enable true to enable, false to disable */ -static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable) +static inline void _mipi_dsi_ll_enable_bus_clock(int group_id, bool enable) { (void)group_id; HP_SYS_CLKRST.soc_clk_ctrl1.reg_dsi_sys_clk_en = enable; @@ -35,7 +35,31 @@ static inline void mipi_dsi_ll_enable_bus_clock(int group_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mipi_dsi_ll_enable_bus_clock(__VA_ARGS__) +#define mipi_dsi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mipi_dsi_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Enable the clock for MIPI DSI host + * + * @param group_id Group ID + * @param en true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_host_clock(int group_id, bool en) +{ + (void)group_id; + MIPI_DSI_BRIDGE.clk_en.clk_en = en; +} + +/** + * @brief Enable the config clock for MIPI DSI host + * + * @param group_id Group ID + * @param en true to enable, false to disable + */ +static inline void mipi_dsi_ll_enable_host_config_clock(int group_id, bool en) +{ + (void)group_id; + MIPI_DSI_BRIDGE.host_ctrl.dsi_cfg_ref_clk_en = en; +} /** * @brief Reset the MIPI DSI module @@ -83,9 +107,11 @@ static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_c HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0; break; case MIPI_DSI_DPI_CLK_SRC_PLL_F160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2; break; case MIPI_DSI_DPI_CLK_SRC_PLL_F240M: + // PLL240 has no gating by default in esp_perip_clk_init. HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1; break; default: @@ -156,12 +182,14 @@ static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_c (void)group_id; switch (source) { case MIPI_DSI_PHY_CLK_SRC_PLL_F20M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0; break; case MIPI_DSI_PHY_CLK_SRC_RC_FAST: HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1; break; case MIPI_DSI_PHY_CLK_SRC_PLL_F25M: + HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mpi_ll.h b/components/hal/esp32p4/include/hal/mpi_ll.h index 24f3de53a8..ba31a2ddbe 100644 --- a/components/hal/esp32p4/include/hal/mpi_ll.h +++ b/components/hal/esp32p4/include/hal/mpi_ll.h @@ -23,14 +23,14 @@ extern "C" { * * @param enable true to enable the module, false to disable the module */ -static inline void mpi_ll_enable_bus_clock(bool enable) +static inline void _mpi_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_rsa_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define mpi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mpi_ll_enable_bus_clock(__VA_ARGS__) +#define mpi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _mpi_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the MPI peripheral module diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h index f863acf277..46ffb279bb 100644 --- a/components/hal/esp32p4/include/hal/parlio_ll.h +++ b/components/hal/esp32p4/include/hal/parlio_ll.h @@ -15,6 +15,7 @@ #include "hal/parlio_types.h" #include "hal/hal_utils.h" #include "soc/hp_sys_clkrst_struct.h" +#include "soc/lp_clkrst_struct.h" #include "soc/parl_io_struct.h" #define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF @@ -102,6 +103,7 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo clk_sel = 1; break; case PARLIO_CLK_SRC_PLL_F160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_sel = 2; break; case PARLIO_CLK_SRC_EXTERNAL: @@ -164,6 +166,7 @@ __attribute__((always_inline)) static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en) { (void)dev; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en; HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en; } @@ -425,6 +428,7 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo clk_sel = 1; break; case PARLIO_CLK_SRC_PLL_F160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_sel = 2; break; case PARLIO_CLK_SRC_EXTERNAL: @@ -488,6 +492,7 @@ __attribute__((always_inline)) static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en) { (void)dev; + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en; HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en; } diff --git a/components/hal/esp32p4/include/hal/pau_ll.h b/components/hal/esp32p4/include/hal/pau_ll.h index edd8007e84..8ecde59e79 100644 --- a/components/hal/esp32p4/include/hal/pau_ll.h +++ b/components/hal/esp32p4/include/hal/pau_ll.h @@ -22,7 +22,7 @@ extern "C" { #endif -static inline void pau_ll_enable_bus_clock(bool enable) +static inline void _pau_ll_enable_bus_clock(bool enable) { if (enable) { HP_SYS_CLKRST.soc_clk_ctrl1.reg_regdma_sys_clk_en = 1; @@ -33,6 +33,10 @@ static inline void pau_ll_enable_bus_clock(bool enable) } } +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define pau_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _pau_ll_enable_bus_clock(__VA_ARGS__) + static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev) { return dev->regdma_conf.flow_err; diff --git a/components/hal/esp32p4/include/hal/rmt_ll.h b/components/hal/esp32p4/include/hal/rmt_ll.h index affcc3eeac..04c3052820 100644 --- a/components/hal/esp32p4/include/hal/rmt_ll.h +++ b/components/hal/esp32p4/include/hal/rmt_ll.h @@ -98,6 +98,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl22, reg_rmt_clk_div_denominator, divider_denominator); switch (src) { case RMT_CLK_SRC_PLL_F80M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl22.reg_rmt_clk_src_sel = 2; break; case RMT_CLK_SRC_RC_FAST: diff --git a/components/hal/esp32p4/include/hal/rtc_io_ll.h b/components/hal/esp32p4/include/hal/rtc_io_ll.h index a23bb2ead0..1bfe4659ff 100644 --- a/components/hal/esp32p4/include/hal/rtc_io_ll.h +++ b/components/hal/esp32p4/include/hal/rtc_io_ll.h @@ -103,6 +103,21 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) } } +/** + * @brief Enable/Disable LP_GPIO peripheral clock. + * + * @param enable true to enable the clock / false to disable the clock + */ +static inline void _rtcio_ll_enable_io_clock(bool enable) +{ + LP_GPIO.clk_en.reg_clk_en = enable; + while (LP_GPIO.clk_en.reg_clk_en != enable) { + ; + } +} + +#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__) + /** * @brief Select the lp_gpio/hp_gpio function to control the pad. * diff --git a/components/hal/esp32p4/include/hal/sdmmc_ll.h b/components/hal/esp32p4/include/hal/sdmmc_ll.h index 1141854f5c..f859496af2 100644 --- a/components/hal/esp32p4/include/hal/sdmmc_ll.h +++ b/components/hal/esp32p4/include/hal/sdmmc_ll.h @@ -135,6 +135,7 @@ static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_ uint32_t clk_val = 0; switch (clk_src) { case SDMMC_CLK_SRC_PLL160M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_val = 0; break; // case SDMMC_CLK_SRC_PLL200M: // TODO: IDF-8886 diff --git a/components/hal/esp32p4/include/hal/sha_ll.h b/components/hal/esp32p4/include/hal/sha_ll.h index 97aa09ad37..bcf0f9fa6c 100644 --- a/components/hal/esp32p4/include/hal/sha_ll.h +++ b/components/hal/esp32p4/include/hal/sha_ll.h @@ -19,14 +19,14 @@ extern "C" { * * @param enable true to enable the module, false to disable the module */ -static inline void sha_ll_enable_bus_clock(bool enable) +static inline void _sha_ll_enable_bus_clock(bool enable) { HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_sha_clk_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__) +#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sha_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the SHA peripheral module diff --git a/components/hal/esp32p4/include/hal/spi_ll.h b/components/hal/esp32p4/include/hal/spi_ll.h index 68299190eb..7f3bc1ed98 100644 --- a/components/hal/esp32p4/include/hal/spi_ll.h +++ b/components/hal/esp32p4/include/hal/spi_ll.h @@ -98,7 +98,7 @@ typedef enum { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { +static inline void _spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) { switch (host_id) { case SPI2_HOST: @@ -115,7 +115,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spi_ll_enable_bus_clock(__VA_ARGS__) +#define spi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spi_ll_enable_bus_clock(__VA_ARGS__) /** * Reset whole peripheral register to init value defined by HW design @@ -147,7 +147,7 @@ static inline void spi_ll_reset_register(spi_host_device_t host_id) { * @param host_id Peripheral index number, see `spi_host_device_t` * @param enable Enable/Disable */ -static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) +static inline void _spi_ll_enable_clock(spi_host_device_t host_id, bool enable) { switch (host_id) { @@ -165,7 +165,7 @@ static inline void spi_ll_enable_clock(spi_host_device_t host_id, bool enable) /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define spi_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; spi_ll_enable_clock(__VA_ARGS__) +#define spi_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spi_ll_enable_clock(__VA_ARGS__) /** * Select SPI peripheral clock source (master). diff --git a/components/hal/esp32p4/include/hal/spimem_flash_ll.h b/components/hal/esp32p4/include/hal/spimem_flash_ll.h index 44ba5f2ecd..95d11df008 100644 --- a/components/hal/esp32p4/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32p4/include/hal/spimem_flash_ll.h @@ -753,6 +753,7 @@ static inline void _spimem_flash_ll_select_clk_source(uint32_t mspi_id, soc_peri break; } + HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel = clk_val; } @@ -779,6 +780,24 @@ static inline void _spimem_ctrlr_ll_set_core_clock(uint8_t mspi_id, uint32_t fre /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance #define spimem_ctrlr_ll_set_core_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_set_core_clock(__VA_ARGS__) +/** + * @brief Disable FLASH MSPI clock + * + * @param mspi_id mspi_id + */ +__attribute__((always_inline)) +static inline void _spimem_ctrlr_ll_unset_clock(uint8_t mspi_id) +{ + (void)mspi_id; + HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_en = 0; + HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_pll_clk_en = 0; + HP_SYS_CLKRST.soc_clk_ctrl0.reg_flash_sys_clk_en = 0; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define spimem_ctrlr_ll_unset_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _spimem_ctrlr_ll_unset_clock(__VA_ARGS__) + /** * @brief Reset whole memory spi */ diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/hal/esp32p4/include/hal/timer_ll.h index e8c678e88e..c13de5bda3 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/hal/esp32p4/include/hal/timer_ll.h @@ -142,6 +142,7 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, clk_id = 0; break; case GPTIMER_CLK_SRC_PLL_F80M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; clk_id = 2; break; case GPTIMER_CLK_SRC_RC_FAST: @@ -177,7 +178,7 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, * @param timer_num Timer index in the group * @param en true to enable, false to disable */ -static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) +static inline void _timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, bool en) { if (hw == &TIMERG0) { if (timer_num == 0) { @@ -196,7 +197,7 @@ static inline void timer_ll_enable_clock(timg_dev_t *hw, uint32_t timer_num, boo /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define timer_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; timer_ll_enable_clock(__VA_ARGS__) +#define timer_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _timer_ll_enable_clock(__VA_ARGS__) /** * @brief Enable alarm event diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index 70560c235d..ed3e327c97 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -174,14 +174,38 @@ FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui * @param hw_id LP UART instance ID * @param enable True to enable, False to disable */ -static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) +static inline void _lp_uart_ll_enable_bus_clock(int hw_id, bool enable) { (void)hw_id; LPPERI.clk_en.ck_en_lp_uart = enable; } // LPPERI.clk_en is a shared register, so this function must be used in an atomic way -#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__) +#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_uart_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Enable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_enable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 1; + LP_UART.clk_conf.rx_sclk_en = 1; +} + +/** + * @brief Disable the UART clock. + * + * @param hw_id LP UART instance ID + */ +FORCE_INLINE_ATTR void lp_uart_ll_sclk_disable(int hw_id) +{ + (void)hw_id; + LP_UART.clk_conf.tx_sclk_en = 0; + LP_UART.clk_conf.rx_sclk_en = 0; +} /** * @brief Reset LP UART module @@ -256,7 +280,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num) * @param uart_num UART port number, the max port number is (UART_NUM_MAX -1). * @param enable true to enable, false to disable */ -static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) +static inline void _uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) { switch (uart_num) { case 0: @@ -288,7 +312,7 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable) } } // HP_SYS_CLKRST.soc_clk_ctrlx are shared registers, so this function must be used in an atomic way -#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_enable_bus_clock(__VA_ARGS__) +#define uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset UART module @@ -336,7 +360,7 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) * @return None. */ -FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +FORCE_INLINE_ATTR void _uart_ll_sclk_enable(uart_dev_t *hw) { if ((hw) == &UART0) { HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 1; @@ -352,9 +376,11 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) // Not going to implement LP_UART reset in this function, it will have its own LL function abort(); } + hw->clk_conf.tx_sclk_en = 1; + hw->clk_conf.rx_sclk_en = 1; } // HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way -#define uart_ll_sclk_enable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_enable(__VA_ARGS__) +#define uart_ll_sclk_enable(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_sclk_enable(__VA_ARGS__) /** * @brief Disable the UART clock. @@ -363,7 +389,7 @@ FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) * * @return None. */ -FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +FORCE_INLINE_ATTR void _uart_ll_sclk_disable(uart_dev_t *hw) { if ((hw) == &UART0) { HP_SYS_CLKRST.peri_clk_ctrl110.reg_uart0_clk_en = 0; @@ -379,9 +405,11 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) // Not going to implement LP_UART reset in this function, it will have its own LL function abort(); } + hw->clk_conf.tx_sclk_en = 0; + hw->clk_conf.rx_sclk_en = 0; } // HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way -#define uart_ll_sclk_disable(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_sclk_disable(__VA_ARGS__) +#define uart_ll_sclk_disable(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_sclk_disable(__VA_ARGS__) /** * @brief Set the UART source clock. @@ -403,6 +431,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ sel_value = 1; break; case UART_SCLK_PLL_F80M: + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; sel_value = 2; break; default: @@ -991,6 +1020,30 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + if (hw == &UART0) { + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart0_slp_clk_en = 1; + } else if (hw == &UART1) { + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart1_slp_clk_en = 1; + } else if (hw == &UART2) { + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart2_slp_clk_en = 1; + } else if (hw == &UART3) { + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart3_slp_clk_en = 1; + } else if (hw == &UART4) { + LP_AON_CLKRST.hp_clk_ctrl.hp_pad_uart4_slp_clk_en = 1; + } +} + +// LP_AON_CLKRST.hp_clk_ctrl is a shared register, so this function must be used in an atomic way +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h index 7028767748..21458ea510 100644 --- a/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h @@ -331,7 +331,7 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable) * @brief Enable the bus clock for USJ module * @param clk_en True if enable the clock of USJ module */ -FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) +FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en) { HP_SYS_CLKRST.soc_clk_ctrl2.reg_usb_device_apb_clk_en = clk_en; // Enable PHY clock (48MHz) for USB FSLS PHY 0 @@ -339,7 +339,7 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en) } // HP_SYS_CLKRST.soc_clk_ctrlx and LP_AON_CLKRST.hp_usb_clkrst_ctrlx are shared registers, so this function must be used in an atomic way -#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__) +#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the USJ module diff --git a/components/hal/esp32p4/include/hal/usb_utmi_ll.h b/components/hal/esp32p4/include/hal/usb_utmi_ll.h index 027bb2e613..14eb8fd176 100644 --- a/components/hal/esp32p4/include/hal/usb_utmi_ll.h +++ b/components/hal/esp32p4/include/hal/usb_utmi_ll.h @@ -39,7 +39,7 @@ FORCE_INLINE_ATTR void usb_utmi_ll_configure_ls(usb_utmi_dev_t *hw, bool paralle * * @param[in] clk_en True to enable, false to disable */ -FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en) +FORCE_INLINE_ATTR void _usb_utmi_ll_enable_bus_clock(bool clk_en) { // Enable/disable system clock for USB_UTMI and USB_DWC_HS HP_SYS_CLKRST.soc_clk_ctrl1.reg_usb_otg20_sys_clk_en = clk_en; @@ -48,7 +48,7 @@ FORCE_INLINE_ATTR void usb_utmi_ll_enable_bus_clock(bool clk_en) } // HP_SYS_CLKRST.soc_clk_ctrlx and LP_AON_CLKRST.hp_usb_clkrst_ctrlx are shared registers, so this function must be used in an atomic way -#define usb_utmi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_utmi_ll_enable_bus_clock(__VA_ARGS__) +#define usb_utmi_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_utmi_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the USB UTMI PHY and USB_DWC_HS controller diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index 4dfbeb9543..e044addcc7 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -120,6 +120,26 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +{ + (void)hw; +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +{ + (void)hw; +} + /** * @brief Set the UART source clock. * @@ -637,6 +657,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 3dd538ec50..ceaa3e246f 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -137,6 +137,26 @@ static inline void uart_ll_reset_register(uart_port_t uart_num) // SYSTEM.perip_rst_enx are shared registers, so this function must be used in an atomic way #define uart_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_reset_register(__VA_ARGS__) +/** + * @brief Enable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw) +{ + (void)hw; +} + +/** + * @brief Disable the UART clock. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw) +{ + (void)hw; +} + /** * @brief Set the UART source clock. * @@ -665,6 +685,19 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_t hw->sleep_conf.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH; } +/** + * @brief Enable/disable the UART pad clock in sleep_state + * + * @param hw Beginning address of the peripheral registers. + * @param enable enable or disable + */ +FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enable) +{ + (void)hw; (void)enable; +} + +#define uart_ll_enable_pad_sleep_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _uart_ll_enable_pad_sleep_clock(__VA_ARGS__) + /** * @brief Configure the UART work in normal mode. * diff --git a/components/hal/include/hal/rtc_io_hal.h b/components/hal/include/hal/rtc_io_hal.h index 086bec8c0d..471a09e006 100644 --- a/components/hal/include/hal/rtc_io_hal.h +++ b/components/hal/include/hal/rtc_io_hal.h @@ -36,7 +36,7 @@ extern "C" { /** * Enable rtcio module clock. */ -#define rtcio_hal_enable_io_clock(enable) rtcio_ll_output_enable(enable) +#define rtcio_hal_enable_io_clock(enable) rtcio_ll_enable_io_clock(enable) #endif /** diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index f1ac7a0dd8..d3b7db707c 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -623,6 +623,10 @@ config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE bool default y +config SOC_LP_IO_CLOCK_IS_INDEPENDENT + bool + default y + config SOC_GPIO_VALID_GPIO_MASK hex default 0x007FFFFFFFFFFFFF diff --git a/components/soc/esp32p4/include/soc/reg_base.h b/components/soc/esp32p4/include/soc/reg_base.h index 0a0bd2c5c9..5b5d58708c 100644 --- a/components/soc/esp32p4/include/soc/reg_base.h +++ b/components/soc/esp32p4/include/soc/reg_base.h @@ -198,9 +198,7 @@ #define DR_REG_INTERRUPT_CORE1_BASE (DR_REG_INTR_BASE + 0x800) #define DR_REG_LPPERI_BASE DR_REG_LP_PERI_CLKRST_BASE #define DR_REG_CPU_BUS_MONITOR_BASE DR_REG_CPU_BUS_MON_BASE - +#define DR_REG_ASSIST_DEBUG_BASE DR_REG_CPU_BUS_MON_BASE #define DR_REG_PAU_BASE DR_REG_REGDMA_BASE - -//TODO: IDF-7688 -// #define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_ASSIST_DEBUG_BASE 0x3FF06000 +#define DR_REG_SDHOST_BASE DR_REG_SDMMC_BASE +#define DR_REG_TRACE_BASE DR_REG_TRACE0_BASE diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h index 5b1b8490a6..baf879c9e5 100644 --- a/components/soc/esp32p4/include/soc/soc.h +++ b/components/soc/esp32p4/include/soc/soc.h @@ -26,6 +26,7 @@ #define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000) #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000) #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1 +#define REG_TRACE_BASE(i) (DR_REG_TRACE_BASE + (i) * 0x1000) //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index a1ccd05234..ae8de5cd90 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -242,6 +242,9 @@ #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) #define SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE (1) +// LP IO peripherals have independent clock gating to manage +#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1) + #define SOC_GPIO_VALID_GPIO_MASK (0x007FFFFFFFFFFFFF) #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK @@ -654,7 +657,7 @@ #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ #define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */ -#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */ +#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */ // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) diff --git a/components/soc/esp32p4/include/soc/trace_reg.h b/components/soc/esp32p4/include/soc/trace_reg.h index c0f45143e9..24a70d315a 100644 --- a/components/soc/esp32p4/include/soc/trace_reg.h +++ b/components/soc/esp32p4/include/soc/trace_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** TRACE_MEM_START_ADDR_REG register * mem start addr */ -#define TRACE_MEM_START_ADDR_REG (DR_REG_TRACE_BASE + 0x0) +#define TRACE_MEM_START_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x0) /** TRACE_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; * The start address of trace memory */ @@ -26,7 +26,7 @@ extern "C" { /** TRACE_MEM_END_ADDR_REG register * mem end addr */ -#define TRACE_MEM_END_ADDR_REG (DR_REG_TRACE_BASE + 0x4) +#define TRACE_MEM_END_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x4) /** TRACE_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; * The end address of trace memory */ @@ -38,7 +38,7 @@ extern "C" { /** TRACE_MEM_CURRENT_ADDR_REG register * mem current addr */ -#define TRACE_MEM_CURRENT_ADDR_REG (DR_REG_TRACE_BASE + 0x8) +#define TRACE_MEM_CURRENT_ADDR_REG(i) (REG_TRACE_BASE(i) + 0x8) /** TRACE_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0; * current_mem_addr,indicate that next writing addr */ @@ -50,7 +50,7 @@ extern "C" { /** TRACE_MEM_ADDR_UPDATE_REG register * mem addr update */ -#define TRACE_MEM_ADDR_UPDATE_REG (DR_REG_TRACE_BASE + 0xc) +#define TRACE_MEM_ADDR_UPDATE_REG(i) (REG_TRACE_BASE(i) + 0xc) /** TRACE_MEM_CURRENT_ADDR_UPDATE : WT; bitpos: [0]; default: 0; * when set, the will * \hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to @@ -64,7 +64,7 @@ extern "C" { /** TRACE_FIFO_STATUS_REG register * fifo status register */ -#define TRACE_FIFO_STATUS_REG (DR_REG_TRACE_BASE + 0x10) +#define TRACE_FIFO_STATUS_REG(i) (REG_TRACE_BASE(i) + 0x10) /** TRACE_FIFO_EMPTY : RO; bitpos: [0]; default: 1; * Represent whether the fifo is empty. \\1: empty \\0: not empty */ @@ -84,7 +84,7 @@ extern "C" { /** TRACE_INTR_ENA_REG register * interrupt enable register */ -#define TRACE_INTR_ENA_REG (DR_REG_TRACE_BASE + 0x14) +#define TRACE_INTR_ENA_REG(i) (REG_TRACE_BASE(i) + 0x14) /** TRACE_FIFO_OVERFLOW_INTR_ENA : R/W; bitpos: [0]; default: 0; * Set 1 enable fifo_overflow interrupt */ @@ -103,7 +103,7 @@ extern "C" { /** TRACE_INTR_RAW_REG register * interrupt status register */ -#define TRACE_INTR_RAW_REG (DR_REG_TRACE_BASE + 0x18) +#define TRACE_INTR_RAW_REG(i) (REG_TRACE_BASE(i) + 0x18) /** TRACE_FIFO_OVERFLOW_INTR_RAW : RO; bitpos: [0]; default: 0; * fifo_overflow interrupt status */ @@ -122,7 +122,7 @@ extern "C" { /** TRACE_INTR_CLR_REG register * interrupt clear register */ -#define TRACE_INTR_CLR_REG (DR_REG_TRACE_BASE + 0x1c) +#define TRACE_INTR_CLR_REG(i) (REG_TRACE_BASE(i) + 0x1c) /** TRACE_FIFO_OVERFLOW_INTR_CLR : WT; bitpos: [0]; default: 0; * Set 1 clear fifo overflow interrupt */ @@ -141,7 +141,7 @@ extern "C" { /** TRACE_TRIGGER_REG register * trigger register */ -#define TRACE_TRIGGER_REG (DR_REG_TRACE_BASE + 0x20) +#define TRACE_TRIGGER_REG(i) (REG_TRACE_BASE(i) + 0x20) /** TRACE_TRIGGER_ON : WT; bitpos: [0]; default: 0; * Configure whether or not start trace.\\1: start trace \\0: invalid\\ */ @@ -157,7 +157,7 @@ extern "C" { #define TRACE_TRIGGER_OFF_V 0x00000001U #define TRACE_TRIGGER_OFF_S 1 /** TRACE_MEM_LOOP : R/W; bitpos: [2]; default: 1; - * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * Configure memory loop mode. \\1: trace will loop write trace_mem. \\0: when * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ */ #define TRACE_MEM_LOOP (BIT(2)) @@ -175,7 +175,7 @@ extern "C" { /** TRACE_CONFIG_REG register * trace configuration register */ -#define TRACE_CONFIG_REG (DR_REG_TRACE_BASE + 0x24) +#define TRACE_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x24) /** TRACE_DM_TRIGGER_ENA : R/W; bitpos: [0]; default: 0; * Configure whether or not enable cpu trigger action.\\1: enable\\0:disable\\ */ @@ -184,9 +184,9 @@ extern "C" { #define TRACE_DM_TRIGGER_ENA_V 0x00000001U #define TRACE_DM_TRIGGER_ENA_S 0 /** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0; - * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * Configure whether or not enable trace cpu haverest, when enabled, if cpu have * reset, the encoder will output a packet to report the address of the last - * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * instruction, and upon reset deassertion, the encoder start again.\\1: enabled\\0: * disabled\\ */ #define TRACE_RESET_ENA (BIT(1)) @@ -194,11 +194,11 @@ extern "C" { #define TRACE_RESET_ENA_V 0x00000001U #define TRACE_RESET_ENA_S 1 /** TRACE_HALT_ENA : R/W; bitpos: [2]; default: 0; - * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * Configure whether or not enable trace cpu is halted, when enabled, if the cpu * halted, the encoder will output a packet to report the address of the last * instruction, and upon halted deassertion, the encoder start again.When disabled, * encoder will not report the last address before halted and first address after - * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + * halted, cpu halted information will not be tracked. \\1: enabled\\0: disabled\\ */ #define TRACE_HALT_ENA (BIT(2)) #define TRACE_HALT_ENA_M (TRACE_HALT_ENA_V << TRACE_HALT_ENA_S) @@ -222,7 +222,7 @@ extern "C" { #define TRACE_FULL_ADDRESS_V 0x00000001U #define TRACE_FULL_ADDRESS_S 4 /** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0; - * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * Configure whether or not enable implicit exception mode. When enabled,, do not sent * exception address, only exception cause in exception packets.\\1: enabled\\0: * disabled\\ */ @@ -234,7 +234,7 @@ extern "C" { /** TRACE_FILTER_CONTROL_REG register * filter control register */ -#define TRACE_FILTER_CONTROL_REG (DR_REG_TRACE_BASE + 0x28) +#define TRACE_FILTER_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x28) /** TRACE_FILTER_EN : R/W; bitpos: [0]; default: 0; * Configure whether or not enable filter unit. \\1: enable filter.\\ 0: always match */ @@ -279,7 +279,7 @@ extern "C" { /** TRACE_FILTER_MATCH_CONTROL_REG register * filter match control register */ -#define TRACE_FILTER_MATCH_CONTROL_REG (DR_REG_TRACE_BASE + 0x2c) +#define TRACE_FILTER_MATCH_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x2c) /** TRACE_MATCH_CHOICE_PRIVILEGE : R/W; bitpos: [0]; default: 0; * Select match which privilege level when * \hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\1: @@ -309,7 +309,7 @@ extern "C" { /** TRACE_FILTER_COMPARATOR_CONTROL_REG register * filter comparator match control register */ -#define TRACE_FILTER_COMPARATOR_CONTROL_REG (DR_REG_TRACE_BASE + 0x30) +#define TRACE_FILTER_COMPARATOR_CONTROL_REG(i) (REG_TRACE_BASE(i) + 0x30) /** TRACE_P_INPUT : R/W; bitpos: [0]; default: 0; * Determines which input to compare against the primary comparator, \\0: iaddr, \\1: * tval. @@ -374,7 +374,7 @@ extern "C" { /** TRACE_FILTER_P_COMPARATOR_MATCH_REG register * primary comparator match value */ -#define TRACE_FILTER_P_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x34) +#define TRACE_FILTER_P_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x34) /** TRACE_P_MATCH : R/W; bitpos: [31:0]; default: 0; * primary comparator match value */ @@ -386,7 +386,7 @@ extern "C" { /** TRACE_FILTER_S_COMPARATOR_MATCH_REG register * secondary comparator match value */ -#define TRACE_FILTER_S_COMPARATOR_MATCH_REG (DR_REG_TRACE_BASE + 0x38) +#define TRACE_FILTER_S_COMPARATOR_MATCH_REG(i) (REG_TRACE_BASE(i) + 0x38) /** TRACE_S_MATCH : R/W; bitpos: [31:0]; default: 0; * secondary comparator match value */ @@ -398,7 +398,7 @@ extern "C" { /** TRACE_RESYNC_PROLONGED_REG register * resync configuration register */ -#define TRACE_RESYNC_PROLONGED_REG (DR_REG_TRACE_BASE + 0x3c) +#define TRACE_RESYNC_PROLONGED_REG(i) (REG_TRACE_BASE(i) + 0x3c) /** TRACE_RESYNC_PROLONGED : R/W; bitpos: [23:0]; default: 128; * count number, when count to this value, send a sync package */ @@ -417,7 +417,7 @@ extern "C" { /** TRACE_AHB_CONFIG_REG register * AHB config register */ -#define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40) +#define TRACE_AHB_CONFIG_REG(i) (REG_TRACE_BASE(i) + 0x40) /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0; * set hburst */ @@ -436,7 +436,7 @@ extern "C" { /** TRACE_CLOCK_GATE_REG register * Clock gate control register */ -#define TRACE_CLOCK_GATE_REG (DR_REG_TRACE_BASE + 0x44) +#define TRACE_CLOCK_GATE_REG(i) (REG_TRACE_BASE(i) + 0x44) /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; * The bit is used to enable clock gate when access all registers in this module. */ @@ -448,7 +448,7 @@ extern "C" { /** TRACE_DATE_REG register * Version control register */ -#define TRACE_DATE_REG (DR_REG_TRACE_BASE + 0x3fc) +#define TRACE_DATE_REG(i) (REG_TRACE_BASE(i) + 0x3fc) /** TRACE_DATE : R/W; bitpos: [27:0]; default: 35721984; * version control register. Note that this default value stored is the latest date * when the hardware logic was updated. diff --git a/components/soc/esp32p4/include/soc/trace_struct.h b/components/soc/esp32p4/include/soc/trace_struct.h index 08667b8cbc..976cc0c31a 100644 --- a/components/soc/esp32p4/include/soc/trace_struct.h +++ b/components/soc/esp32p4/include/soc/trace_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -159,7 +159,7 @@ typedef union { */ uint32_t trigger_off:1; /** mem_loop : R/W; bitpos: [2]; default: 1; - * Configure memory loop mode. \\1: trace will loop wrtie trace_mem. \\0: when + * Configure memory loop mode. \\1: trace will loop write trace_mem. \\0: when * mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\ */ uint32_t mem_loop:1; @@ -182,18 +182,18 @@ typedef union { */ uint32_t dm_trigger_ena:1; /** reset_ena : R/W; bitpos: [1]; default: 0; - * Configure whether or not enable trace cpu haverest, when enabeld, if cpu have + * Configure whether or not enable trace cpu haverest, when enabled, if cpu have * reset, the encoder will output a packet to report the address of the last - * instruction, and upon reset deassertion, the encoder start again.\\1: enabeld\\0: + * instruction, and upon reset deassertion, the encoder start again.\\1: enabled\\0: * disabled\\ */ uint32_t reset_ena:1; /** halt_ena : R/W; bitpos: [2]; default: 0; - * Configure whether or not enable trace cpu is halted, when enabeld, if the cpu + * Configure whether or not enable trace cpu is halted, when enabled, if the cpu * halted, the encoder will output a packet to report the address of the last * instruction, and upon halted deassertion, the encoder start again.When disabled, * encoder will not report the last address before halted and first address after - * halted, cpu halted information will not be tracked. \\1: enabeld\\0: disabled\\ + * halted, cpu halted information will not be tracked. \\1: enabled\\0: disabled\\ */ uint32_t halt_ena:1; /** stall_ena : R/W; bitpos: [3]; default: 0; @@ -208,7 +208,7 @@ typedef union { */ uint32_t full_address:1; /** implicit_except : R/W; bitpos: [5]; default: 0; - * Configure whether or not enabel implicit exception mode. When enabled,, do not sent + * Configure whether or not enable implicit exception mode. When enabled,, do not sent * exception address, only exception cause in exception packets.\\1: enabled\\0: * disabled\\ */ @@ -451,6 +451,8 @@ typedef struct { volatile trace_date_reg_t date; } trace_dev_t; +extern trace_dev_t TRACE0; +extern trace_dev_t TRACE1; #ifndef __cplusplus _Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure"); diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index a0ae5ba367..fd880fc50a 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -119,3 +119,5 @@ PROVIDE ( EMAC_MAC = 0x50098000 ); PROVIDE ( EMAC_DMA = 0x50099000 ); PROVIDE ( CACHE = 0x3FF10000); +PROVIDE ( TRACE0 = 0x3FF04000); +PROVIDE ( TRACE1 = 0x3FF05000); diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index 94f751b38c..cc0eafb3b6 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -55,6 +55,7 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg) /* Enable LP UART bus clock */ lp_uart_ll_enable_bus_clock(0, true); lp_uart_ll_set_source_clk(hal.dev, clk_src); + lp_uart_ll_sclk_enable(0); } /* Initialize LP UART HAL with default parameters */ diff --git a/components/usb/usb_phy_p4.c b/components/usb/usb_phy_p4.c index 8365cded17..b81e9be548 100644 --- a/components/usb/usb_phy_p4.c +++ b/components/usb/usb_phy_p4.c @@ -6,17 +6,25 @@ // TODO: Refactor during the IDF-9198 #include "sdkconfig.h" +#include "soc/soc_caps.h" #include "soc/usb_dwc_cfg.h" #include "hal/usb_utmi_ll.h" // We don't have usb_utmi_hal yet #include "esp_private/periph_ctrl.h" // TODO: Remove this file when proper support of P4 PHYs is implemented IDF-7323 #include "esp_private/usb_phy.h" +#include "esp_private/periph_ctrl.h" + +#if SOC_RCC_IS_INDEPENDENT +#define USB_UTMI_BUS_CLK_ATOMIC() +#else +#define USB_UTMI_BUS_CLK_ATOMIC() PERIPH_RCC_ATOMIC() +#endif esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_ret) { #if (OTG_HSPHY_INTERFACE != 0) #if CONFIG_IDF_TARGET_ESP32P4 - PERIPH_RCC_ATOMIC() { + USB_UTMI_BUS_CLK_ATOMIC() { usb_utmi_ll_enable_bus_clock(true); usb_utmi_ll_reset_register(); } @@ -35,6 +43,9 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r esp_err_t usb_del_phy(usb_phy_handle_t handle) { + USB_UTMI_BUS_CLK_ATOMIC() { + usb_utmi_ll_enable_bus_clock(false); + } return ESP_OK; } From 71fb3d2f3157a077cb6292024e4fe727470f7b33 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 Aug 2024 15:42:12 +0800 Subject: [PATCH 2/5] fix(esp_system): fix test rodata being prefetched into cache unexpectedly --- .../test_apps/cache_panic/main/test_cache_disabled.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c index 19fd6b9ef7..6dfc11af78 100644 --- a/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c +++ b/components/esp_system/test_apps/cache_panic/main/test_cache_disabled.c @@ -60,7 +60,9 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash // This needs to sufficiently large array, otherwise it may end up in // DRAM (e.g. size <= 8 bytes && ARCH == RISCV) -static const uint32_t s_in_rodata[8] = { 0x12345678, 0xfedcba98 }; +// And it needs to be >= and aligned to the cacheline size, otherwise it may be prefetched +// to cache data memory before accessing it because of accessing other rodata in the same cacheline. +static const __attribute__((aligned(128))) uint32_t s_in_rodata[32] = { 0x12345678, 0xfedcba98 }; static void reset_after_invalid_cache(void) { From c41d432397b25281054356514b6d827c203c8ed6 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 28 Aug 2024 22:05:29 +0800 Subject: [PATCH 3/5] fix(ulp): fix uart driver delete order in lp uart test case --- .../lp_core_basic_tests/main/test_lp_core_uart.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_uart.c b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_uart.c index ac5c196fc9..563f69ca1a 100644 --- a/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_uart.c +++ b/components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_uart.c @@ -352,6 +352,9 @@ static void hp_uart_write(void) /* Write data to LP UART */ uart_write_bytes(UART_NUM_1, (const char *)tx_data, TEST_DATA_LEN + sizeof(start_pattern) + sizeof(end_pattern)); + /* Wait for the LP UART receive data done */ + unity_wait_for_signal("LP UART recv data done"); + /* Uninstall the HP UART driver */ uart_driver_delete(UART_NUM_1); vTaskDelay(1); @@ -399,6 +402,9 @@ static void test_lp_uart_read(void) /* Verify test data */ ESP_LOGI(TAG, "Verify Rx data"); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_rx_data, rx_data + data_idx, TEST_DATA_LEN); + + /* Notify the HP UART data received done and delete the UART driver */ + unity_send_signal("LP UART recv data done"); } static void hp_uart_write_options(void) @@ -438,6 +444,9 @@ static void hp_uart_write_options(void) /* Write data to LP UART */ uart_write_bytes(UART_NUM_1, (const char *)tx_data, TEST_DATA_LEN + sizeof(start_pattern) + sizeof(end_pattern)); + /* Wait for the LP UART receive data done */ + unity_wait_for_signal("LP UART recv data done"); + /* Uninstall the HP UART driver */ uart_driver_delete(UART_NUM_1); vTaskDelay(1); @@ -485,6 +494,9 @@ static void test_lp_uart_read_options(void) /* Verify test data */ ESP_LOGI(TAG, "Verify Rx data"); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_rx_data, rx_data + data_idx, TEST_DATA_LEN); + + /* Notify the HP UART data received done and delete the UART driver */ + unity_send_signal("LP UART recv data done"); } static void test_lp_uart_read_multi_byte(void) @@ -531,6 +543,9 @@ static void test_lp_uart_read_multi_byte(void) * begin with garbage data which fills the initial part of the receive buffer. */ ESP_LOGI(TAG, "Verify Rx data"); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_rx_data, rx_data + data_idx, TEST_DATA_LEN - 10); + + /* Notify the HP UART data received done and delete the UART driver */ + unity_send_signal("LP UART recv data done"); } static void hp_uart_read_print(void) From 13e42707a0d4ba0d60c38a7e11fe3b60fc1c380b Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 5 Sep 2024 21:40:20 +0800 Subject: [PATCH 4/5] feat(esp_hw_support): add clk tree source gate management api --- components/driver/deprecated/adc_dma_legacy.c | 5 ++ components/driver/deprecated/adc_legacy.c | 4 + components/driver/deprecated/mcpwm_legacy.c | 4 + components/driver/deprecated/rmt_legacy.c | 4 + components/driver/deprecated/timer_legacy.c | 5 +- components/esp_adc/adc_continuous.c | 6 +- components/esp_adc/adc_oneshot.c | 11 +++ components/esp_adc/linker.lf | 6 ++ .../esp_driver_cam/csi/src/esp_cam_ctlr_csi.c | 3 + .../dvp/src/esp_cam_ctlr_dvp_cam.c | 3 + .../esp_driver_gptimer/src/gptimer_common.c | 3 + components/esp_driver_isp/src/isp_core.c | 3 + components/esp_driver_ledc/src/ledc.c | 3 + components/esp_driver_mcpwm/src/mcpwm_com.c | 5 +- components/esp_driver_parlio/src/parlio_rx.c | 3 + components/esp_driver_parlio/src/parlio_tx.c | 3 + components/esp_driver_rmt/src/rmt_common.c | 3 + components/esp_driver_sdmmc/src/sdmmc_host.c | 2 + components/esp_driver_uart/src/uart.c | 3 + .../include/esp_private/esp_clk_tree_common.h | 20 ++++- .../esp_hw_support/port/esp32/esp_clk_tree.c | 8 +- .../port/esp32c2/esp_clk_tree.c | 8 +- .../port/esp32c3/esp_clk_tree.c | 8 +- .../port/esp32c5/esp_clk_tree.c | 6 ++ .../port/esp32c6/esp_clk_tree.c | 8 +- .../port/esp32c61/esp_clk_tree.c | 6 ++ .../port/esp32h2/esp_clk_tree.c | 8 +- .../port/esp32p4/esp_clk_tree.c | 30 ++++++- .../esp_hw_support/port/esp32p4/io_mux.c | 4 + .../port/esp32s2/esp_clk_tree.c | 8 +- .../port/esp32s3/esp_clk_tree.c | 8 +- .../main/test_dport.c | 8 +- components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c | 2 + components/esp_lcd/dsi/esp_lcd_panel_dpi.c | 2 + components/esp_lcd/i80/esp_lcd_panel_io_i80.c | 2 + components/esp_lcd/rgb/esp_lcd_panel_rgb.c | 3 + components/esp_pm/pm_impl.c | 5 +- .../esp_system_unity_tests/main/test_sleep.c | 3 + components/hal/esp32p4/include/hal/adc_ll.h | 1 - components/hal/esp32p4/include/hal/cam_ll.h | 1 - .../hal/esp32p4/include/hal/clk_gate_ll.h | 80 +++++++++++++++++++ components/hal/esp32p4/include/hal/gpio_ll.h | 1 - components/hal/esp32p4/include/hal/isp_ll.h | 2 - components/hal/esp32p4/include/hal/lcd_ll.h | 1 - components/hal/esp32p4/include/hal/ledc_ll.h | 1 - components/hal/esp32p4/include/hal/mcpwm_ll.h | 1 - .../hal/esp32p4/include/hal/mipi_csi_ll.h | 2 - .../hal/esp32p4/include/hal/mipi_dsi_ll.h | 4 - .../hal/esp32p4/include/hal/parlio_ll.h | 2 - components/hal/esp32p4/include/hal/rmt_ll.h | 1 - components/hal/esp32p4/include/hal/sdmmc_ll.h | 1 - components/hal/esp32p4/include/hal/timer_ll.h | 1 - components/hal/esp32p4/include/hal/uart_ll.h | 1 - 53 files changed, 291 insertions(+), 35 deletions(-) diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c index 0106088ed8..7845b4bcc5 100644 --- a/components/driver/deprecated/adc_dma_legacy.c +++ b/components/driver/deprecated/adc_dma_legacy.c @@ -9,6 +9,7 @@ #include #include #include "sdkconfig.h" +#include "soc/soc_caps.h" #include "esp_intr_alloc.h" #include "esp_log.h" #include "esp_pm.h" @@ -18,6 +19,7 @@ #include "freertos/semphr.h" #include "freertos/timers.h" #include "freertos/ringbuf.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "esp_private/adc_share_hw_ctrl.h" #include "esp_private/sar_periph_ctrl.h" @@ -472,6 +474,9 @@ esp_err_t adc_digi_start(void) adc_hal_set_controller(ADC_UNIT_2, ADC_HAL_CONTINUOUS_READ_MODE); adc_hal_digi_init(&s_adc_digi_ctx->hal); +#if !CONFIG_IDF_TARGET_ESP32 + esp_clk_tree_enable_src((soc_module_clk_t)(s_adc_digi_ctx->hal_digi_ctrlr_cfg.clk_src), true); +#endif adc_hal_digi_controller_config(&s_adc_digi_ctx->hal, &s_adc_digi_ctx->hal_digi_ctrlr_cfg); adc_dma_stop(s_adc_digi_ctx); diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index 76277ac5e5..239bb5ac40 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -16,6 +16,7 @@ #include "esp_check.h" #include "esp_pm.h" #include "soc/rtc.h" +#include "soc/soc_caps.h" #include "driver/rtc_io.h" #include "sys/lock.h" #include "driver/gpio.h" @@ -26,6 +27,7 @@ #include "hal/adc_hal.h" #include "hal/adc_ll.h" #include "hal/adc_hal_common.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "driver/adc_types_legacy.h" #include "esp_clk_tree.h" @@ -775,6 +777,7 @@ int adc1_get_raw(adc1_channel_t channel) adc_apb_periph_claim(); sar_periph_ctrl_adc_oneshot_power_acquire(); + esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true); adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT); adc_atten_t atten = s_atten1_single[channel]; @@ -832,6 +835,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc_apb_periph_claim(); sar_periph_ctrl_adc_oneshot_power_acquire(); + esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true); adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT); adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT(); diff --git a/components/driver/deprecated/mcpwm_legacy.c b/components/driver/deprecated/mcpwm_legacy.c index 974402f949..87d5cdda7c 100644 --- a/components/driver/deprecated/mcpwm_legacy.c +++ b/components/driver/deprecated/mcpwm_legacy.c @@ -14,6 +14,7 @@ #include "esp_intr_alloc.h" #include "soc/mcpwm_periph.h" #include "soc/io_mux_reg.h" +#include "soc/soc_caps.h" #include "hal/mcpwm_hal.h" #include "hal/gpio_hal.h" #include "hal/mcpwm_ll.h" @@ -22,6 +23,7 @@ #include "esp_private/periph_ctrl.h" #include "esp_private/gpio.h" #include "esp_private/esp_clk.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_clk_tree.h" static const char *TAG = "mcpwm(legacy)"; @@ -467,6 +469,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw uint32_t group_pre_scale = clk_src_hz / group_resolution; uint32_t timer_pre_scale = group_resolution / timer_resolution; + esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT); mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale); @@ -864,6 +867,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num); uint32_t group_pre_scale = clk_src_hz / group_resolution; + esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT); mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale); diff --git a/components/driver/deprecated/rmt_legacy.c b/components/driver/deprecated/rmt_legacy.c index 6d28bb1193..d3c319d039 100644 --- a/components/driver/deprecated/rmt_legacy.c +++ b/components/driver/deprecated/rmt_legacy.c @@ -12,6 +12,7 @@ #include "esp_log.h" #include "esp_check.h" #include "driver/gpio.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "esp_private/gpio.h" #include "driver/rmt_types_legacy.h" @@ -19,6 +20,7 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/ringbuf.h" +#include "soc/soc_caps.h" #include "soc/soc_memory_layout.h" #include "soc/rmt_periph.h" #include "soc/rmt_struct.h" @@ -438,6 +440,7 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk) { ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); + esp_clk_tree_enable_src((soc_module_clk_t)base_clk, true); // `rmt_clock_source_t` and `rmt_source_clk_t` are binary compatible, as the underlying enum entries come from the same `soc_module_clk_t` RMT_CLOCK_SRC_ATOMIC() { rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, (rmt_clock_source_t)base_clk, 1, 0, 0); @@ -603,6 +606,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #endif } esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz); + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); RMT_CLOCK_SRC_ATOMIC() { rmt_ll_set_group_clock_src(dev, channel, clk_src, 1, 0, 0); rmt_ll_enable_group_clock(dev, true); diff --git a/components/driver/deprecated/timer_legacy.c b/components/driver/deprecated/timer_legacy.c index 08261f8dd1..2ee334bbeb 100644 --- a/components/driver/deprecated/timer_legacy.c +++ b/components/driver/deprecated/timer_legacy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,8 +15,10 @@ #include "hal/timer_ll.h" #include "hal/check.h" #include "soc/timer_periph.h" +#include "soc/soc_caps.h" #include "esp_clk_tree.h" #include "soc/timer_group_reg.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" static const char *TIMER_TAG = "timer_group"; @@ -326,6 +328,7 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer if (config->clk_src) { clk_src = config->clk_src; } + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); GPTIMER_CLOCK_SRC_ATOMIC() { // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`, // as the underlying enum entries come from the same `soc_module_clk_t` diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c index 381ad55f8d..8ef8bef917 100644 --- a/components/esp_adc/adc_continuous.c +++ b/components/esp_adc/adc_continuous.c @@ -23,6 +23,7 @@ #include "freertos/semphr.h" #include "freertos/timers.h" #include "freertos/ringbuf.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "esp_private/adc_private.h" #include "esp_private/adc_share_hw_ctrl.h" @@ -33,6 +34,7 @@ #include "hal/adc_types.h" #include "hal/adc_hal.h" #include "hal/dma_types.h" +#include "soc/soc_caps.h" #include "esp_memory_utils.h" #include "adc_continuous_internal.h" #include "esp_private/adc_dma.h" @@ -300,7 +302,9 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle) } adc_hal_digi_init(&handle->hal); - +#if !CONFIG_IDF_TARGET_ESP32 + esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), true); +#endif adc_hal_digi_controller_config(&handle->hal, &handle->hal_digi_ctrlr_cfg); adc_hal_digi_enable(false); diff --git a/components/esp_adc/adc_oneshot.c b/components/esp_adc/adc_oneshot.c index 2d622687c0..aabac9cfc1 100644 --- a/components/esp_adc/adc_oneshot.c +++ b/components/esp_adc/adc_oneshot.c @@ -24,11 +24,13 @@ #include "esp_private/adc_private.h" #include "esp_private/adc_share_hw_ctrl.h" #include "esp_private/sar_periph_ctrl.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_sleep_internal.h" #include "hal/adc_types.h" #include "hal/adc_oneshot_hal.h" #include "hal/adc_ll.h" #include "soc/adc_periph.h" +#include "soc/soc_caps.h" #if CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM #define ADC_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) @@ -159,6 +161,9 @@ esp_err_t adc_oneshot_config_channel(adc_oneshot_unit_handle_t handle, adc_chann portENTER_CRITICAL(&rtc_spinlock); adc_oneshot_hal_channel_config(hal, &cfg, channel); if (handle->ulp_mode) { +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + esp_clk_tree_enable_src((soc_module_clk_t)(hal->clk_src), true); +#endif adc_oneshot_hal_setup(hal, channel); } portEXIT_CRITICAL(&rtc_spinlock); @@ -176,6 +181,9 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan, } portENTER_CRITICAL(&rtc_spinlock); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true); +#endif adc_oneshot_hal_setup(&(handle->hal), chan); #if SOC_ADC_CALIBRATION_V1_SUPPORTED adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan); @@ -199,6 +207,9 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c portENTER_CRITICAL_SAFE(&rtc_spinlock); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true); +#endif adc_oneshot_hal_setup(&(handle->hal), chan); #if SOC_ADC_CALIBRATION_V1_SUPPORTED adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan); diff --git a/components/esp_adc/linker.lf b/components/esp_adc/linker.lf index 855ebe7cbd..24769b37a5 100644 --- a/components/esp_adc/linker.lf +++ b/components/esp_adc/linker.lf @@ -4,6 +4,12 @@ entries: if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y: adc_oneshot: adc_oneshot_read_isr (noflash) +[mapping:esp_hw_support_adc] +archive: libesp_hw_support.a +entries: + if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y: + esp_clk_tree: esp_clk_tree_enable_src (noflash) + [mapping:adc_hal] archive: libhal.a entries: diff --git a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c index 49aee4a745..2769a172d8 100644 --- a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c +++ b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c @@ -22,7 +22,9 @@ #include "esp_private/periph_ctrl.h" #include "esp_private/mipi_csi_share_hw_ctrl.h" #include "esp_private/esp_cache_private.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_cache.h" +#include "soc/soc_caps.h" #if CONFIG_CAM_CTLR_MIPI_CSI_ISR_IRAM_SAFE #define CSI_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT) @@ -123,6 +125,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_ #endif mipi_csi_phy_clock_source_t clk_src = !config->clk_src ? MIPI_CSI_PHY_CLK_SRC_DEFAULT : config->clk_src; + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PERIPH_RCC_ATOMIC() { // phy clock source setting mipi_csi_ll_set_phy_clock_source(ctlr->csi_id, clk_src); diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c index 992ea773cc..405d8f8cea 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c @@ -18,8 +18,10 @@ #include "esp_check.h" #include "esp_clk_tree.h" #include "soc/cam_periph.h" +#include "soc/soc_caps.h" #include "esp_cam_ctlr_dvp_cam.h" #include "esp_private/esp_cam_dvp.h" +#include "esp_private/esp_clk_tree_common.h" #include "../../dvp_share_ctrl.h" #ifdef CONFIG_CAM_CTLR_DVP_CAM_ISR_IRAM_SAFE @@ -329,6 +331,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e } } + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PERIPH_RCC_ATOMIC() { cam_ll_enable_clk(ctlr_id, true); cam_ll_select_clk_src(ctlr_id, clk_src); diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c index c81288e58b..a561f6195b 100644 --- a/components/esp_driver_gptimer/src/gptimer_common.c +++ b/components/esp_driver_gptimer/src/gptimer_common.c @@ -6,8 +6,10 @@ #include "esp_check.h" #include "esp_clk_tree.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/gptimer.h" #include "gptimer_priv.h" +#include "soc/soc_caps.h" static const char *TAG = "gptimer"; @@ -196,6 +198,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s } #endif // CONFIG_PM_ENABLE + esp_clk_tree_enable_src((soc_module_clk_t)src_clk, true); // !!! HARDWARE SHARED RESOURCE !!! // on some ESP chip, different peripheral's clock source setting are mixed in the same register // so we need to make this done in an atomic way diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c index 1f1e002d2f..f3ff71e625 100644 --- a/components/esp_driver_isp/src/isp_core.c +++ b/components/esp_driver_isp/src/isp_core.c @@ -19,6 +19,8 @@ #include "hal/hal_utils.h" #include "soc/mipi_csi_bridge_struct.h" #include "soc/isp_periph.h" +#include "soc/soc_caps.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/isp_private.h" typedef struct isp_platform_t { @@ -106,6 +108,7 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_ } ; isp_hal_init(&proc->hal, proc->proc_id); + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PERIPH_RCC_ATOMIC() { isp_ll_select_clk_source(proc->hal.hw, clk_src); isp_ll_set_clock_div(proc->hal.hw, &clk_div); diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index a9d93f904a..2a05db23e5 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -21,6 +21,7 @@ #include "clk_ctrl_os.h" #include "esp_private/periph_ctrl.h" #include "esp_private/gpio.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_gpio_reserve.h" #include "esp_memory_utils.h" @@ -563,6 +564,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n if (p_ledc_obj[speed_mode]->glb_clk != glb_clk) { // TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree] p_ledc_obj[speed_mode]->glb_clk = glb_clk; + esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true); LEDC_FUNC_CLOCK_ATOMIC() { ledc_ll_enable_clock(p_ledc_obj[speed_mode]->ledc_hal.dev, true); ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk); @@ -698,6 +700,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) else if (new_speed_mode_ctx_created) { portENTER_CRITICAL(&ledc_spinlock); if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_UNINIT) { + esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true); ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), LEDC_LL_GLOBAL_CLK_DEFAULT); } portEXIT_CRITICAL(&ledc_spinlock); diff --git a/components/esp_driver_mcpwm/src/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c index 60b5443b0f..d75ffb4f9d 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_com.c +++ b/components/esp_driver_mcpwm/src/mcpwm_com.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,8 +15,10 @@ #include "esp_log.h" #include "esp_check.h" #include "esp_clk_tree.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "soc/mcpwm_periph.h" +#include "soc/soc_caps.h" #include "hal/mcpwm_ll.h" #include "mcpwm_private.h" @@ -172,6 +174,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s ESP_LOGD(TAG, "install NO_LIGHT_SLEEP lock for MCPWM group(%d)", group->group_id); #endif // CONFIG_PM_ENABLE + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(group->group_id, clk_src); } diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c index c6e3eadf88..411ed2aea0 100644 --- a/components/esp_driver_parlio/src/parlio_rx.c +++ b/components/esp_driver_parlio/src/parlio_rx.c @@ -23,6 +23,7 @@ #include "esp_rom_gpio.h" #include "esp_pm.h" #include "soc/parlio_periph.h" +#include "soc/soc_caps.h" #include "hal/parlio_ll.h" #include "hal/gpio_hal.h" #include "hal/dma_types.h" @@ -33,6 +34,7 @@ #include "esp_memory_utils.h" #include "esp_clk_tree.h" #include "esp_attr.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/gdma.h" #include "esp_cache.h" @@ -537,6 +539,7 @@ static esp_err_t s_parlio_select_periph_clock(parlio_rx_unit_handle_t rx_unit, c } #endif + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); /* Set clock configuration */ PARLIO_CLOCK_SRC_ATOMIC() { parlio_ll_rx_set_clock_source(hal->regs, clk_src); diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index 0e22d96b2e..dcf073ed26 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -27,12 +27,14 @@ #include "esp_intr_alloc.h" #include "esp_pm.h" #include "soc/parlio_periph.h" +#include "soc/soc_caps.h" #include "hal/parlio_ll.h" #include "driver/gpio.h" #include "driver/parlio_tx.h" #include "parlio_private.h" #include "esp_memory_utils.h" #include "esp_clk_tree.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/gdma.h" #include "esp_private/gdma_link.h" @@ -253,6 +255,7 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par #else tx_unit->out_clk_freq_hz = hal_utils_calc_clk_div_integer(&clk_info, &clk_div.integer); #endif + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PARLIO_CLOCK_SRC_ATOMIC() { // turn on the tx module clock to sync the register configuration to the module parlio_ll_tx_enable_clock(hal->regs, true); diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c index c66880f9bb..d33dae1a6e 100644 --- a/components/esp_driver_rmt/src/rmt_common.c +++ b/components/esp_driver_rmt/src/rmt_common.c @@ -16,9 +16,11 @@ #include "rmt_private.h" #include "clk_ctrl_os.h" #include "soc/rtc.h" +#include "soc/soc_caps.h" #include "soc/rmt_periph.h" #include "hal/rmt_ll.h" #include "driver/gpio.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" static const char *TAG = "rmt"; @@ -207,6 +209,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed"); #endif // CONFIG_PM_ENABLE + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); // no division for group clock source, to achieve highest resolution RMT_CLOCK_SRC_ATOMIC() { rmt_ll_set_group_clock_src(group->hal.regs, channel_id, clk_src, 1, 1, 0); diff --git a/components/esp_driver_sdmmc/src/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c index e8459ea9f6..f322f8316f 100644 --- a/components/esp_driver_sdmmc/src/sdmmc_host.c +++ b/components/esp_driver_sdmmc/src/sdmmc_host.c @@ -18,6 +18,7 @@ #include "esp_rom_sys.h" #include "driver/gpio.h" #include "driver/sdmmc_host.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "sdmmc_private.h" #include "freertos/FreeRTOS.h" @@ -164,6 +165,7 @@ esp_err_t sdmmc_host_reset(void) */ static void sdmmc_host_set_clk_div(int div) { + esp_clk_tree_enable_src((soc_module_clk_t)SDMMC_CLK_SRC_DEFAULT, true); SDMMC_CLK_SRC_ATOMIC() { sdmmc_ll_set_clock_div(s_host_ctx.hal.dev, div); sdmmc_ll_select_clk_source(s_host_ctx.hal.dev, SDMMC_CLK_SRC_DEFAULT); diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index ebd7ee92d4..c8f5436ad2 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -21,9 +21,11 @@ #include "hal/uart_hal.h" #include "hal/gpio_hal.h" #include "soc/uart_periph.h" +#include "soc/soc_caps.h" #include "driver/uart.h" #include "driver/gpio.h" #include "driver/uart_select.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/gpio.h" #include "esp_private/uart_share_hw_ctrl.h" #include "esp_clk_tree.h" @@ -906,6 +908,7 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); uart_hal_init(&(uart_context[uart_num].hal), uart_num); if (uart_num < SOC_UART_HP_NUM) { + esp_clk_tree_enable_src((soc_module_clk_t)uart_sclk_sel, true); HP_UART_SRC_CLK_ATOMIC() { uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel); uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); diff --git a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h index c67660d1d9..4a3c895b4f 100644 --- a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h +++ b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include #include #include "esp_clk_tree.h" #include "soc/soc_caps.h" @@ -74,6 +75,23 @@ uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t prec */ uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision); +/** + * @brief Enable / Disable the clock gate of the clock source + * + * @param[in] clk_src Clock source available to modules, in soc_module_clk_t + * @param[in] enable Enable / Disable the clock gate + * + * @note !!! WARNING !!! + * There's no reference counter to protect the clock source status, the caller should use the interface + * with CAUTION to disable the clock source to avoid damaging other peripherals that are dependent on + * the clock source. + * + * @return + * - ESP_OK Success + * - ESP_ERR_INVALID_ARG Parameter error + */ +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable); + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32/esp_clk_tree.c b/components/esp_hw_support/port/esp32/esp_clk_tree.c index 8704be2c84..e748df5d4c 100644 --- a/components/esp_hw_support/port/esp32/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -69,3 +69,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c2/esp_clk_tree.c b/components/esp_hw_support/port/esp32c2/esp_clk_tree.c index 5426db1bea..50291204d3 100644 --- a/components/esp_hw_support/port/esp32c2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c2/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,3 +63,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c3/esp_clk_tree.c b/components/esp_hw_support/port/esp32c3/esp_clk_tree.c index 892b1fab1d..a3eaae3200 100644 --- a/components/esp_hw_support/port/esp32c3/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c3/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,3 +63,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index 62dfe1eddd..f91284e682 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -66,3 +66,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c6/esp_clk_tree.c b/components/esp_hw_support/port/esp32c6/esp_clk_tree.c index ef7621cef9..21d98303df 100644 --- a/components/esp_hw_support/port/esp32c6/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c6/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -63,3 +63,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c index 2ddaca24af..78352f59f3 100644 --- a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c @@ -60,3 +60,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32h2/esp_clk_tree.c b/components/esp_hw_support/port/esp32h2/esp_clk_tree.c index 3106efd679..b221582a10 100644 --- a/components/esp_hw_support/port/esp32h2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h2/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -60,3 +60,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c index 546f25c34b..880dff56f9 100644 --- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,11 @@ #include "esp_err.h" #include "esp_check.h" #include "soc/rtc.h" +#include "hal/clk_gate_ll.h" #include "hal/clk_tree_hal.h" #include "hal/clk_tree_ll.h" #include "esp_private/esp_clk_tree_common.h" +#include "esp_private/periph_ctrl.h" static const char *TAG = "esp_clk_tree"; @@ -85,3 +87,29 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + PERIPH_RCC_ATOMIC() { + switch (clk_src) { + case SOC_MOD_CLK_PLL_F20M: + clk_gate_ll_ref_20m_clk_en(enable); + break; + case SOC_MOD_CLK_PLL_F25M: + clk_gate_ll_ref_25m_clk_en(enable); + break; + case SOC_MOD_CLK_PLL_F80M: + clk_gate_ll_ref_80m_clk_en(enable); + break; + case SOC_MOD_CLK_PLL_F160M: + clk_gate_ll_ref_160m_clk_en(enable); + break; + case SOC_MOD_CLK_PLL_F240M: + clk_gate_ll_ref_240m_clk_en(enable); + break; + default: + break; + } + } + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32p4/io_mux.c b/components/esp_hw_support/port/esp32p4/io_mux.c index 5f3bf951ab..64cd2aa200 100644 --- a/components/esp_hw_support/port/esp32p4/io_mux.c +++ b/components/esp_hw_support/port/esp32p4/io_mux.c @@ -7,10 +7,12 @@ #include "sdkconfig.h" #include "esp_attr.h" #include "freertos/FreeRTOS.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/io_mux.h" #include "esp_private/periph_ctrl.h" #include "hal/gpio_ll.h" #include "hal/rtc_io_ll.h" +#include "soc/soc_caps.h" #define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC() @@ -40,6 +42,8 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) if (clk_conflict) { return ESP_ERR_INVALID_STATE; } + + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PERIPH_RCC_ATOMIC() { gpio_ll_iomux_set_clk_src(clk_src); } diff --git a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c index cbaf7760ab..ff9e20571d 100644 --- a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -67,3 +67,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/port/esp32s3/esp_clk_tree.c b/components/esp_hw_support/port/esp32s3/esp_clk_tree.c index c73f2d637d..d71373714b 100644 --- a/components/esp_hw_support/port/esp32s3/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s3/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -67,3 +67,9 @@ uint32_t *freq_value) *freq_value = clk_src_freq; return ESP_OK; } + +esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) +{ + (void)clk_src; (void)enable; + return ESP_OK; +} diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c index 72f4e6da26..834771d629 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "xtensa/hal.h" #include "esp_types.h" #include "esp_private/esp_clk.h" +#include "esp_private/esp_clk_tree_common.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" @@ -27,6 +28,7 @@ #include "soc/dport_reg.h" #include "dport_access.h" #include "soc/rtc.h" +#include "soc/soc_caps.h" #include "esp_cpu.h" #include "esp_intr_alloc.h" #include "esp_task.h" @@ -142,6 +144,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz) esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM); rtc_clk_cpu_freq_set_config(&new_config); + esp_clk_tree_enable_src((soc_module_clk_t)UART_SCLK_DEFAULT, true); uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT); uint32_t sclk_freq; @@ -158,6 +161,7 @@ void run_tasks_with_change_freq_cpu(int cpu_freq_mhz) // return old freq. esp_rom_output_tx_wait_idle(CONFIG_ESP_CONSOLE_ROM_SERIAL_PORT_NUM); rtc_clk_cpu_freq_set_config(&old_config); + esp_clk_tree_enable_src((soc_module_clk_t)UART_SCLK_DEFAULT, true); uart_ll_set_sclk(UART_LL_GET_HW(uart_num), UART_SCLK_DEFAULT); uint32_t sclk_freq; @@ -439,7 +443,7 @@ TEST_CASE("Check pre-read workaround DPORT and Hi-interrupt", "[esp32]") static uint32_t s_shift_counter; /* -The test_dport_access_reg_read() is similar DPORT_REG_READ() but has differents: +The test_dport_access_reg_read() is similar DPORT_REG_READ() but has difference: - generate an interrupt by SET_CCOMPARE - additional branch command helps get good reproducing an issue with breaking the DPORT pre-read workaround - uncomment (1) and comment (2) it allows seeing the broken pre-read workaround diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c index ca519162d6..26b75ad507 100644 --- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c +++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c @@ -9,6 +9,7 @@ #include "esp_check.h" #include "esp_lcd_mipi_dsi.h" #include "esp_clk_tree.h" +#include "esp_private/esp_clk_tree_common.h" #include "mipi_dsi_priv.h" static const char *TAG = "lcd.dsi.bus"; @@ -49,6 +50,7 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc if (phy_clk_src == 0) { phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT; } + esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true); // enable the clock source for DSI PHY DSI_CLOCK_SRC_ATOMIC() { // set clock source for DSI PHY diff --git a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c index e4fcdc7e54..4bec7273eb 100644 --- a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c +++ b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c @@ -17,6 +17,7 @@ #include "esp_async_fbcpy.h" #include "esp_memory_utils.h" #include "esp_private/dw_gdma.h" +#include "esp_private/esp_clk_tree_common.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" @@ -232,6 +233,7 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ &dpi_clk_src_freq_hz), err, TAG, "get clock source frequency failed"); // divide the source clock to get the final DPI clock uint32_t dpi_div = mipi_dsi_hal_host_dpi_calculate_divider(hal, dpi_clk_src_freq_hz / 1000 / 1000, panel_config->dpi_clock_freq_mhz); + esp_clk_tree_enable_src((soc_module_clk_t)dpi_clk_src, true); // set the clock source, set the divider, and enable the dpi clock DSI_CLOCK_SRC_ATOMIC() { mipi_dsi_ll_set_dpi_clock_source(bus_id, dpi_clk_src); diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c index 99af62c9c2..96b8fb4ca8 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c @@ -29,6 +29,7 @@ #include "esp_memory_utils.h" #include "esp_cache.h" #include "driver/gpio.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/gpio.h" #include "esp_private/gdma.h" #include "esp_private/gdma_link.h" @@ -583,6 +584,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); LCD_CLOCK_SRC_ATOMIC() { lcd_ll_select_clk_src(bus->hal.dev, clk_src); // force to use integer division, as fractional division might lead to clock jitter diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index f34bb2d2e3..60165fc1c5 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -32,11 +32,13 @@ #include "esp_private/gdma.h" #include "driver/gpio.h" #include "esp_bit_defs.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/periph_ctrl.h" #include "esp_psram.h" #include "esp_lcd_common.h" #include "esp_memory_utils.h" #include "soc/lcd_periph.h" +#include "soc/soc_caps.h" #include "hal/lcd_hal.h" #include "hal/lcd_ll.h" #include "hal/cache_hal.h" @@ -902,6 +904,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *panel, lcd_cloc ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); panel->src_clk_hz = src_clk_hz; + esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); LCD_CLOCK_SRC_ATOMIC() { lcd_ll_select_clk_src(panel->hal.dev, clk_src); } diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index 7b04a08013..f7ebc0601b 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -10,6 +10,7 @@ #include #include +#include "sdkconfig.h" #include "esp_attr.h" #include "esp_err.h" #include "esp_pm.h" @@ -41,6 +42,7 @@ #include "esp_private/pm_trace.h" #include "esp_private/esp_timer_private.h" #include "esp_private/esp_clk.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/sleep_cpu.h" #include "esp_private/sleep_gpio.h" #include "esp_private/sleep_modem.h" @@ -48,7 +50,6 @@ #include "esp_sleep.h" #include "esp_memory_utils.h" -#include "sdkconfig.h" #if SOC_PERIPH_CLK_CTRL_SHARED #define HP_UART_SRC_CLK_ATOMIC() PERIPH_RCC_ATOMIC() @@ -926,6 +927,8 @@ void esp_pm_impl_init(void) while (!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))) { ; } + + esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true); /* When DFS is enabled, override system setting and use REFTICK as UART clock source */ HP_UART_SRC_CLK_ATOMIC() { uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source); diff --git a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c index 10ac4c2f2c..4dda52f60f 100644 --- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c +++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_sleep.c @@ -20,6 +20,7 @@ #include "soc/rtc.h" // for wakeup trigger defines #include "soc/rtc_periph.h" // for read rtc registers directly (cause) #include "soc/soc.h" // for direct register read macros +#include "soc/soc_caps.h" #include "esp_newlib.h" #include "test_utils.h" #include "sdkconfig.h" @@ -27,6 +28,7 @@ #include "esp_rom_sys.h" #include "esp_timer.h" #include "esp_private/esp_clk.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/uart_share_hw_ctrl.h" #include "esp_random.h" #include "nvs_flash.h" @@ -176,6 +178,7 @@ TEST_CASE("light sleep and frequency switching", "[lightsleep]") #elif SOC_UART_SUPPORT_XTAL_CLK clk_source = UART_SCLK_XTAL; #endif + esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true); HP_UART_SRC_CLK_ATOMIC() { uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source); } diff --git a/components/hal/esp32p4/include/hal/adc_ll.h b/components/hal/esp32p4/include/hal/adc_ll.h index fb08fa93d9..881cfd0c63 100644 --- a/components/hal/esp32p4/include/hal/adc_ll.h +++ b/components/hal/esp32p4/include/hal/adc_ll.h @@ -223,7 +223,6 @@ static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src) HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1; break; case ADC_DIGI_CLK_SRC_PLL_F80M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/cam_ll.h b/components/hal/esp32p4/include/hal/cam_ll.h index 638b8f7ba5..a48dba2dc8 100644 --- a/components/hal/esp32p4/include/hal/cam_ll.h +++ b/components/hal/esp32p4/include/hal/cam_ll.h @@ -96,7 +96,6 @@ static inline void cam_ll_select_clk_src(int group_id, cam_clock_source_t src) HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 0; break; case CAM_CLK_SRC_PLL160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl119.reg_cam_clk_src_sel = 1; break; case CAM_CLK_SRC_APLL: diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index e69de29bb2..8c5fc05cfb 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -0,0 +1,80 @@ +/* + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "esp_attr.h" +#include "soc/hp_sys_clkrst_struct.h" + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_20m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_20m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_20m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_25m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_25m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_25m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_80m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_80m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_160m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_160m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_240m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_240m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32p4/include/hal/gpio_ll.h b/components/hal/esp32p4/include/hal/gpio_ll.h index 56f6d4d514..094cf73cb2 100644 --- a/components/hal/esp32p4/include/hal/gpio_ll.h +++ b/components/hal/esp32p4/include/hal/gpio_ll.h @@ -637,7 +637,6 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 0; break; case SOC_MOD_CLK_PLL_F80M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl26.reg_iomux_clk_src_sel = 1; break; default: diff --git a/components/hal/esp32p4/include/hal/isp_ll.h b/components/hal/esp32p4/include/hal/isp_ll.h index 1f96086bac..dcbf678933 100644 --- a/components/hal/esp32p4/include/hal/isp_ll.h +++ b/components/hal/esp32p4/include/hal/isp_ll.h @@ -198,11 +198,9 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr clk_val = 0; break; case ISP_CLK_SRC_PLL160: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_val = 1; break; case ISP_CLK_SRC_PLL240: - HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_240m_clk_en = 1; clk_val = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/lcd_ll.h b/components/hal/esp32p4/include/hal/lcd_ll.h index e10f8c8eee..99e41cfc68 100644 --- a/components/hal/esp32p4/include/hal/lcd_ll.h +++ b/components/hal/esp32p4/include/hal/lcd_ll.h @@ -102,7 +102,6 @@ static inline void lcd_ll_select_clk_src(lcd_cam_dev_t *dev, lcd_clock_source_t HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 0; break; case LCD_CLK_SRC_PLL160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl19.reg_lcd_clk_src_sel = 1; break; case LCD_CLK_SRC_APLL: diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h index 8d13cc6ee3..dea593b889 100644 --- a/components/hal/esp32p4/include/hal/ledc_ll.h +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -103,7 +103,6 @@ static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t clk_sel_val = 1; break; case LEDC_SLOW_CLK_PLL_DIV: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; clk_sel_val = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mcpwm_ll.h b/components/hal/esp32p4/include/hal/mcpwm_ll.h index 870f7ef23e..4031c06070 100644 --- a/components/hal/esp32p4/include/hal/mcpwm_ll.h +++ b/components/hal/esp32p4/include/hal/mcpwm_ll.h @@ -168,7 +168,6 @@ static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_ clk_id = 1; break; case SOC_MOD_CLK_PLL_F160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_id = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mipi_csi_ll.h b/components/hal/esp32p4/include/hal/mipi_csi_ll.h index 9c007b8884..c6c72f0c66 100644 --- a/components/hal/esp32p4/include/hal/mipi_csi_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_csi_ll.h @@ -69,14 +69,12 @@ static inline void mipi_csi_ll_set_phy_clock_source(int group_id, mipi_csi_phy_c (void)group_id; switch (source) { case MIPI_CSI_PHY_CLK_SRC_PLL_F20M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 0; break; case MIPI_CSI_PHY_CLK_SRC_RC_FAST: HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 1; break; case MIPI_CSI_PHY_CLK_SRC_PLL_F25M: - HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_csi_dphy_clk_src_sel = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h index 2021c636cc..e310ef7c8e 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_ll.h @@ -107,11 +107,9 @@ static inline void mipi_dsi_ll_set_dpi_clock_source(int group_id, mipi_dsi_dpi_c HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 0; break; case MIPI_DSI_DPI_CLK_SRC_PLL_F160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 2; break; case MIPI_DSI_DPI_CLK_SRC_PLL_F240M: - // PLL240 has no gating by default in esp_perip_clk_init. HP_SYS_CLKRST.peri_clk_ctrl03.reg_mipi_dsi_dpiclk_src_sel = 1; break; default: @@ -182,14 +180,12 @@ static inline void mipi_dsi_ll_set_phy_clock_source(int group_id, mipi_dsi_phy_c (void)group_id; switch (source) { case MIPI_DSI_PHY_CLK_SRC_PLL_F20M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_20m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 0; break; case MIPI_DSI_PHY_CLK_SRC_RC_FAST: HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 1; break; case MIPI_DSI_PHY_CLK_SRC_PLL_F25M: - HP_SYS_CLKRST.ref_clk_ctrl1.reg_ref_25m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl02.reg_mipi_dsi_dphy_clk_src_sel = 2; break; default: diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h index 46ffb279bb..c982049870 100644 --- a/components/hal/esp32p4/include/hal/parlio_ll.h +++ b/components/hal/esp32p4/include/hal/parlio_ll.h @@ -103,7 +103,6 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo clk_sel = 1; break; case PARLIO_CLK_SRC_PLL_F160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_sel = 2; break; case PARLIO_CLK_SRC_EXTERNAL: @@ -428,7 +427,6 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo clk_sel = 1; break; case PARLIO_CLK_SRC_PLL_F160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_sel = 2; break; case PARLIO_CLK_SRC_EXTERNAL: diff --git a/components/hal/esp32p4/include/hal/rmt_ll.h b/components/hal/esp32p4/include/hal/rmt_ll.h index 04c3052820..affcc3eeac 100644 --- a/components/hal/esp32p4/include/hal/rmt_ll.h +++ b/components/hal/esp32p4/include/hal/rmt_ll.h @@ -98,7 +98,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl22, reg_rmt_clk_div_denominator, divider_denominator); switch (src) { case RMT_CLK_SRC_PLL_F80M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; HP_SYS_CLKRST.peri_clk_ctrl22.reg_rmt_clk_src_sel = 2; break; case RMT_CLK_SRC_RC_FAST: diff --git a/components/hal/esp32p4/include/hal/sdmmc_ll.h b/components/hal/esp32p4/include/hal/sdmmc_ll.h index f859496af2..1141854f5c 100644 --- a/components/hal/esp32p4/include/hal/sdmmc_ll.h +++ b/components/hal/esp32p4/include/hal/sdmmc_ll.h @@ -135,7 +135,6 @@ static inline void sdmmc_ll_select_clk_source(sdmmc_dev_t *hw, soc_periph_sdmmc_ uint32_t clk_val = 0; switch (clk_src) { case SDMMC_CLK_SRC_PLL160M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_160m_clk_en = 1; clk_val = 0; break; // case SDMMC_CLK_SRC_PLL200M: // TODO: IDF-8886 diff --git a/components/hal/esp32p4/include/hal/timer_ll.h b/components/hal/esp32p4/include/hal/timer_ll.h index c13de5bda3..ba229bd0be 100644 --- a/components/hal/esp32p4/include/hal/timer_ll.h +++ b/components/hal/esp32p4/include/hal/timer_ll.h @@ -142,7 +142,6 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, clk_id = 0; break; case GPTIMER_CLK_SRC_PLL_F80M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; clk_id = 2; break; case GPTIMER_CLK_SRC_RC_FAST: diff --git a/components/hal/esp32p4/include/hal/uart_ll.h b/components/hal/esp32p4/include/hal/uart_ll.h index ed3e327c97..9b62cea267 100644 --- a/components/hal/esp32p4/include/hal/uart_ll.h +++ b/components/hal/esp32p4/include/hal/uart_ll.h @@ -431,7 +431,6 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ sel_value = 1; break; case UART_SCLK_PLL_F80M: - HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_80m_clk_en = 1; sel_value = 2; break; default: From 21f79616bdb7639360031e4d6079d72fc67d6d56 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Wed, 11 Sep 2024 10:52:19 +0800 Subject: [PATCH 5/5] change(esp_driver_spi): increase SPI_PER_TRANS_POLLING peformance tolerance --- .../components/spi_bench_mark/include/spi_performance.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h index 200370ad90..5dcb6f690f 100644 --- a/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h +++ b/components/esp_driver_spi/test_apps/components/spi_bench_mark/include/spi_performance.h @@ -70,7 +70,7 @@ #elif CONFIG_IDF_TARGET_ESP32P4 #define IDF_PERFORMANCE_MAX_SPI_CLK_FREQ 26*1000*1000 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING 44 -#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 27 +#define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING 28 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_NO_POLLING_NO_DMA 26 #define IDF_PERFORMANCE_MAX_SPI_PER_TRANS_POLLING_NO_DMA 12