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esp32h2: chip env support

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brownout init fixed
This commit is contained in:
wuzhenghui 2021-07-08 14:37:24 +08:00
parent f65c8249af
commit 6ab495b4dc
8 changed files with 11 additions and 13 deletions
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1
Kconfig
View File

@ -11,7 +11,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
config IDF_ENV_FPGA
# This option is for internal use only
bool
default "y" if IDF_TARGET="esp32h2" # ESP32H2-TODO: IDF-3378
option env="IDF_ENV_FPGA"
config IDF_TARGET_ARCH_RISCV

7
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
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@ -254,12 +254,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
// This check is always included in the bootloader so it can
// print the minimum revision error message later in the boot
if (bootloader_common_get_chip_revision() < 3) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
}
}
static inline void bootloader_glitch_reset_disable(void)

2
components/esp_hw_support/port/esp32h2/private_include/regi2c_bias.h
View File

@ -14,7 +14,7 @@
* bootloader_hardware_init function in bootloader_esp32c3.c.
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS 0x6a
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P1_PVT 1

2
components/esp_hw_support/port/esp32h2/private_include/regi2c_lp_bias.h
View File

@ -14,6 +14,8 @@
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* rtc_init function in rtc_init.c.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0

1
components/esp_hw_support/port/esp32h2/rtc_sleep.c
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@ -85,6 +85,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
// ESP32-H2 TO-DO: IDF-3693
if (cfg.deep_slp) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);

4
components/esp_system/port/soc/esp32h2/clk.c
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@ -82,7 +82,7 @@ static const char *TAG = "clk";
}
rtc_init(cfg);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_32M);
rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
#endif
@ -177,7 +177,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
}
}
} else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
rtc_clk_8m_enable(true, true);
// rtc_clk_8m_enable(true, true);
}
rtc_clk_slow_freq_set(rtc_slow_freq);

1
components/esp_system/startup.c
View File

@ -268,6 +268,7 @@ static void do_core_init(void)
CONFIG_ESP32S3_BROWNOUT_DET || \
CONFIG_ESP32C3_BROWNOUT_DET || \
CONFIG_ESP32H2_BROWNOUT_DET
// [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) ->
// malloc (newlib) -> heap_caps_malloc (heap), so heap must be at least initialized
esp_brownout_init();

4
components/soc/esp32h2/include/soc/soc.h
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@ -228,10 +228,10 @@
#if CONFIG_IDF_ENV_FPGA
#define APB_CLK_FREQ ( 32*1000000 )
#else
#define APB_CLK_FREQ ( 80*1000000 )
#define APB_CLK_FREQ ( 96*1000000 )
#endif
#define REF_CLK_FREQ ( 1000000 )
#define RTC_CLK_FREQ (20*1000000)
#define RTC_CLK_FREQ (17.5*1000000)
#define XTAL_CLK_FREQ (32*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ