Merge branch 'feature/esp32c5_mp_gpio_support' into 'master'

esp32c5 mp gpio support Closes IDF-9649 See merge request espressif/esp-idf!30474
2024-10-05 20:47:46 -04:00 · 2024-05-11 22:50:23 +08:00 · 2024-05-11 22:50:23 +08:00 · 6a57c26469
commit 6a57c26469
parent 0299e78272 cbef285352
43 changed files with 386 additions and 4394 deletions
--- a/components/esp_driver_gpio/test_apps/.build-test-rules.yml
+++ b/components/esp_driver_gpio/test_apps/.build-test-rules.yml
@ -1,10 +1,6 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps

 components/esp_driver_gpio/test_apps:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not support yet # TODO: [ESP32C5] IDF-8717
  disable_test:
    - if: IDF_TARGET == "esp32p4"
      temporary: true
--- a/components/esp_driver_gpio/test_apps/gpio/README.md
+++ b/components/esp_driver_gpio/test_apps/gpio/README.md
@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
--- a/components/esp_pm/Kconfig
+++ b/components/esp_pm/Kconfig
@ -2,7 +2,7 @@ menu "Power Management"
    config PM_ENABLE
        bool "Support for power management"
        # SMP FreeRTOS currently does not support power management IDF-4997
-        depends on !FREERTOS_SMP || __DOXYGEN__
+        depends on (!FREERTOS_SMP && SOC_PM_SUPPORTED) || __DOXYGEN__
        default n
        help
            If enabled, application is compiled with support for power management.
--- a/components/espcoredump/src/core_dump_uart.c
+++ b/components/espcoredump/src/core_dump_uart.c
@ -6,6 +6,7 @@
 #include <string.h>
 #include "soc/uart_reg.h"
 #include "soc/gpio_periph.h"
+#include "soc/uart_pins.h"
 #include "driver/gpio.h"
 #include "hal/gpio_hal.h"
 #include "esp_core_dump_types.h"
@ -147,17 +148,15 @@ static esp_err_t esp_core_dump_uart_hw_init(void)
    uint32_t tm_cur = 0;
    int ch = 0;

-    // TODO: move chip dependent code to portable part
+    gpio_hal_context_t gpio_hal = {
+        .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
+    };
+
    //Make sure txd/rxd are enabled
    // use direct reg access instead of gpio_pullup_dis which can cause exception when flash cache is disabled
    REG_CLR_BIT(GPIO_PIN_REG_1, FUN_PU);
-#if CONFIG_IDF_TARGET_ESP32P4
-    gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U_PAD_GPIO38, FUNC_GPIO38_UART0_RXD_PAD);
-    gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U_PAD_GPIO37, FUNC_GPIO37_UART0_TXD_PAD);
-#else
-    gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0RXD_U, FUNC_U0RXD_U0RXD);
-    gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD_U0TXD);
-#endif
+    gpio_hal_func_sel(&gpio_hal, U0RXD_GPIO_NUM, U0RXD_MUX_FUNC);
+    gpio_hal_func_sel(&gpio_hal, U0TXD_GPIO_NUM, U0TXD_MUX_FUNC);
    ESP_COREDUMP_LOGI("Press Enter to print core dump to UART...");
    const int cpu_ticks_per_ms = esp_clk_cpu_freq() / 1000;
    tm_end = esp_cpu_get_cycle_count() / cpu_ticks_per_ms + CONFIG_ESP_COREDUMP_UART_DELAY;
--- a/components/hal/esp32c5/include/hal/gpio_ll.h
+++ b/components/hal/esp32c5/include/hal/gpio_ll.h
@ -22,23 +22,17 @@
 #include "soc/gpio_struct.h"
 #include "soc/lp_aon_struct.h"
 #include "soc/pmu_struct.h"
+#include "soc/io_mux_struct.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "soc/usb_serial_jtag_struct.h"
+#include "hal/gpio_types.h"
+#include "hal/assert.h"
 #if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
 #include "soc/lp_io_struct.h"
-#include "soc/pcr_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/usb_serial_jtag_struct.h"
-#include "soc/io_mux_struct.h"
-#include "hal/gpio_types.h"
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
 #include "soc/lp_gpio_struct.h"
-#include "soc/usb_serial_jtag_reg.h"
-#include "soc/pcr_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/io_mux_struct.h"
-#include "hal/gpio_types.h"
-#include "hal/misc.h"
 #endif
-#include "hal/assert.h"

 #ifdef __cplusplus
 extern "C" {
@ -69,15 +63,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
                                         bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
                                         uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
 {
-    *pu = IOMUX.gpio[gpio_num].fun_wpu;
-    *pd = IOMUX.gpio[gpio_num].fun_wpd;
-    *ie = IOMUX.gpio[gpio_num].fun_ie;
+    *pu = IO_MUX.gpio[gpio_num].fun_wpu;
+    *pd = IO_MUX.gpio[gpio_num].fun_wpd;
+    *ie = IO_MUX.gpio[gpio_num].fun_ie;
    *oe = (hw->enable.val & (1 << gpio_num)) >> gpio_num;
    *od = hw->pin[gpio_num].pad_driver;
-    *drv = IOMUX.gpio[gpio_num].fun_drv;
-    *fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
+    *drv = IO_MUX.gpio[gpio_num].fun_drv;
+    *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
    *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
-    *slp_sel = IOMUX.gpio[gpio_num].slp_sel;
+    *slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
 }

 /**
@ -88,12 +82,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
  */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpu = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpu = 1;
 }

 /**
@ -105,12 +94,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpu = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PU);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpu = 0;
 }

 /**
@ -121,12 +105,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_wpd = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // REG_SET_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpd = 1;
 }

 /**
@ -143,20 +122,11 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
    // Note that esp32C5 has supported USB_EXCHG_PINS feature. If this efuse is burnt, the gpio pin
    // which should be checked is USB_INT_PHY0_DM_GPIO_NUM instead.
    // TODO: read the specific efuse with efuse_ll.h
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
    if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
        USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
        USB_SERIAL_JTAG.conf0.dp_pullup = 0;
    }
-    IOMUX.gpio[gpio_num].fun_wpd = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // if (gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
-    //     SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
-    // }
-    // REG_CLR_BIT(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_PD);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_wpd = 0;
 }

 /**
@ -182,11 +152,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
    (void)core_id;
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
    *status = hw->pcpu_int.procpu_int;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    abort();
-#endif
 }

 /**
@ -261,12 +227,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_ie = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_ie = 0;
 }

 /**
@ -277,12 +238,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_ie = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_ie = 1;
 }

 /**
@ -293,12 +249,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 */
 static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].filter_en = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_FILTER_EN(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].filter_en = 1;
 }

 /**
@ -309,15 +260,9 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 */
 static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].filter_en = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].filter_en = 0;
 }

-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
 /**
  * @brief Enable GPIO hysteresis
  *
@ -330,8 +275,8 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
    // We are not going to use the hardware control in IDF for C5.
    // Therefore, we need to always switch to use software control first.
    // i.e. Swt hys_sel to 1, so that hys_en determines whether hysteresis is enabled or not
-    IOMUX.gpio[gpio_num].hys_sel = 1;
-    IOMUX.gpio[gpio_num].hys_en = 1;
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 1;
 }

 /**
@ -342,10 +287,9 @@ static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t
  */
 static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].hys_sel = 1;
-    IOMUX.gpio[gpio_num].hys_en = 0;
+    IO_MUX.gpio[gpio_num].hys_sel = 1;
+    IO_MUX.gpio[gpio_num].hys_en = 0;
 }
-#endif

 /**
  * @brief Disable output mode on GPIO.
@ -461,12 +405,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].fun_drv = strength;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // SET_PERI_REG_BITS(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, strength, FUN_DRV_S);
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].fun_drv = strength;
 }

 /**
@ -478,12 +417,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    *strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
-    abort();
-#endif
+    *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
 }

 /**
@ -527,7 +461,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
 }

 /**
-  * @brief Set pad input to a peripheral signal through the IOMUX.
+  * @brief Set pad input to a peripheral signal through the IO_MUX.
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number of the pad.
@ -537,7 +471,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
-    IOMUX.gpio[gpio].fun_ie = 1;
+    IO_MUX.gpio[gpio].fun_ie = 1;
 }

 /**
@ -554,11 +488,10 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
    }
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
-    // if (pin_name == IO_MUX_GPIO12_REG || pin_name == IO_MUX_GPIO13_REG) {
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
-    // }
-    abort();
+    // Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
+    if (pin_name == IO_MUX_GPIO13_REG || pin_name == IO_MUX_GPIO14_REG) {
+        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+    }
 #endif
    PIN_FUNC_SELECT(pin_name, func);
 }
@ -590,19 +523,18 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
    if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
    }
-    IOMUX.gpio[gpio_num].mcu_sel = func;
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 #elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // // Disable USB Serial JTAG if pins 12 or pins 13 needs to select an IOMUX function
-    // if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
-    //     CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
-    // }
-    // PIN_FUNC_SELECT(IO_MUX_GPIO0_REG + (gpio_num * 4), func);
-    abort();
+    // Disable USB Serial JTAG if pins 13 or pins 14 needs to select an IOMUX function
+    if (gpio_num == USB_INT_PHY0_DM_GPIO_NUM || gpio_num == USB_INT_PHY0_DP_GPIO_NUM) {
+        USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+    }
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 #endif
 }

 /**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  * @brief Set peripheral output to an GPIO pad through the IO_MUX.
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num gpio_num GPIO number of the pad.
@ -625,7 +557,6 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
 static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
 {
    switch (src) {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
     case SOC_MOD_CLK_XTAL:
        PCR.iomux_clk_conf.iomux_func_clk_sel = 0;
        break;
@ -635,14 +566,6 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
    case SOC_MOD_CLK_PLL_F80M:
        PCR.iomux_clk_conf.iomux_func_clk_sel = 2;
        break;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    case SOC_MOD_CLK_XTAL:
-        PCR.iomux_clk_conf.iomux_func_clk_sel = 3;
-        break;
-    case SOC_MOD_CLK_PLL_F80M:
-        PCR.iomux_clk_conf.iomux_func_clk_sel = 1;
-        break;
-#endif
    default:
        // Unsupported IO_MUX clock source
        HAL_ASSERT(false);
@ -694,12 +617,7 @@ static inline void gpio_ll_force_unhold_all(void)
  */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].slp_sel = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_SEL_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].slp_sel = 1;
 }

 /**
@ -711,12 +629,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].slp_sel = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_SEL_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].slp_sel = 0;
 }

 /**
@ -727,12 +640,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpu = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLUP_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpu = 0;
 }

 /**
@ -743,12 +651,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpu = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLUP_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpu = 1;
 }

 /**
@ -759,12 +662,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpd = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLDOWN_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpd = 1;
 }

 /**
@ -775,12 +673,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_wpd = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_PULLDOWN_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_wpd = 0;
 }

 /**
@ -791,12 +684,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_ie = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_INPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_ie = 0;
 }

 /**
@ -807,12 +695,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
  */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_ie = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_INPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_ie = 1;
 }

 /**
@ -823,12 +706,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_oe = 0;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_OUTPUT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_oe = 0;
 }

 /**
@ -839,12 +717,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
  */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
-    IOMUX.gpio[gpio_num].mcu_oe = 1;
-#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
-    // PIN_SLP_OUTPUT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
-    abort();
-#endif
+    IO_MUX.gpio[gpio_num].mcu_oe = 1;
 }

 #ifdef __cplusplus
--- a/components/hal/esp32p4/include/hal/gpio_ll.h
+++ b/components/hal/esp32p4/include/hal/gpio_ll.h
@ -64,15 +64,15 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
 {
    uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32);
    uint32_t bit_mask = 1 << bit_shift;
-    *pu = IOMUX.gpio[gpio_num].fun_wpu;
-    *pd = IOMUX.gpio[gpio_num].fun_wpd;
-    *ie = IOMUX.gpio[gpio_num].fun_ie;
+    *pu = IO_MUX.gpio[gpio_num].fun_wpu;
+    *pd = IO_MUX.gpio[gpio_num].fun_wpd;
+    *ie = IO_MUX.gpio[gpio_num].fun_ie;
    *oe = (((gpio_num < 32) ? hw->enable.val : hw->enable1.val) & bit_mask) >> bit_shift;
    *od = hw->pin[gpio_num].pad_driver;
-    *drv = IOMUX.gpio[gpio_num].fun_drv;
-    *fun_sel = IOMUX.gpio[gpio_num].mcu_sel;
+    *drv = IO_MUX.gpio[gpio_num].fun_drv;
+    *fun_sel = IO_MUX.gpio[gpio_num].mcu_sel;
    *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
-    *slp_sel = IOMUX.gpio[gpio_num].slp_sel;
+    *slp_sel = IO_MUX.gpio[gpio_num].slp_sel;
 }

 /**
@ -83,7 +83,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
  */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpu = 1;
+    IO_MUX.gpio[gpio_num].fun_wpu = 1;
 }

 /**
@ -95,7 +95,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpu = 0;
+    IO_MUX.gpio[gpio_num].fun_wpu = 0;
 }

 /**
@ -106,7 +106,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_wpd = 1;
+    IO_MUX.gpio[gpio_num].fun_wpd = 1;
 }

 /**
@ -133,7 +133,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
        USB_WRAP.otg_conf.pad_pull_override = 1;
        USB_WRAP.otg_conf.dp_pullup = 0;
    }
-    IOMUX.gpio[gpio_num].fun_wpd = 0;
+    IO_MUX.gpio[gpio_num].fun_wpd = 0;
 }

 /**
@ -235,7 +235,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, uint32_t gpio_num)
 __attribute__((always_inline))
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_ie = 0;
+    IO_MUX.gpio[gpio_num].fun_ie = 0;
 }

 /**
@ -246,7 +246,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].fun_ie = 1;
+    IO_MUX.gpio[gpio_num].fun_ie = 1;
 }

 /**
@ -257,7 +257,7 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 */
 static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].filter_en = 1;
+    IO_MUX.gpio[gpio_num].filter_en = 1;
 }

 /**
@ -268,7 +268,7 @@ static inline void gpio_ll_pin_filter_enable(gpio_dev_t *hw, uint32_t gpio_num)
 */
 static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].filter_en = 0;
+    IO_MUX.gpio[gpio_num].filter_en = 0;
 }

 /**
@ -451,7 +451,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t strength)
 {
-    IOMUX.gpio[gpio_num].fun_drv = strength;
+    IO_MUX.gpio[gpio_num].fun_drv = strength;
 }

 /**
@ -463,7 +463,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = (gpio_drive_cap_t)(IOMUX.gpio[gpio_num].fun_drv);
+    *strength = (gpio_drive_cap_t)(IO_MUX.gpio[gpio_num].fun_drv);
 }

 /**
@ -547,7 +547,7 @@ static inline bool gpio_ll_is_digital_io_hold(gpio_dev_t *hw, uint32_t gpio_num)
 }

 /**
-  * @brief Set pad input to a peripheral signal through the IOMUX.
+  * @brief Set pad input to a peripheral signal through the IO_MUX.
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num GPIO number of the pad.
@ -557,7 +557,7 @@ __attribute__((always_inline))
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
-    IOMUX.gpio[gpio].fun_ie = 1;
+    IO_MUX.gpio[gpio].fun_ie = 1;
 }

 /**
@ -597,11 +597,11 @@ static inline void gpio_ll_func_sel(gpio_dev_t *hw, uint8_t gpio_num, uint32_t f
    } else if (gpio_num == USB_OTG_INT_PHY_DM_GPIO_NUM || gpio_num == USB_OTG_INT_PHY_DP_GPIO_NUM) {
        USB_WRAP.otg_conf.usb_pad_enable = 0;
    }
-    IOMUX.gpio[gpio_num].mcu_sel = func;
+    IO_MUX.gpio[gpio_num].mcu_sel = func;
 }

 /**
-  * @brief Set peripheral output to an GPIO pad through the IOMUX.
+  * @brief Set peripheral output to an GPIO pad through the IO_MUX.
  *
  * @param hw Peripheral GPIO hardware instance address.
  * @param gpio_num gpio_num GPIO number of the pad.
@ -685,7 +685,7 @@ static inline void gpio_ll_force_unhold_all(void)
  */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].slp_sel = 1;
+    IO_MUX.gpio[gpio_num].slp_sel = 1;
 }

 /**
@ -697,7 +697,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].slp_sel = 0;
+    IO_MUX.gpio[gpio_num].slp_sel = 0;
 }

 /**
@ -708,7 +708,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpu = 0;
+    IO_MUX.gpio[gpio_num].mcu_wpu = 0;
 }

 /**
@ -719,7 +719,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpu = 1;
+    IO_MUX.gpio[gpio_num].mcu_wpu = 1;
 }

 /**
@ -730,7 +730,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpd = 1;
+    IO_MUX.gpio[gpio_num].mcu_wpd = 1;
 }

 /**
@ -741,7 +741,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_wpd = 0;
+    IO_MUX.gpio[gpio_num].mcu_wpd = 0;
 }

 /**
@ -752,7 +752,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_ie = 0;
+    IO_MUX.gpio[gpio_num].mcu_ie = 0;
 }

 /**
@ -763,7 +763,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, uint32_t gpio_num
  */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_ie = 1;
+    IO_MUX.gpio[gpio_num].mcu_ie = 1;
 }

 /**
@ -774,7 +774,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, uint32_t gpio_num)
  */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_oe = 0;
+    IO_MUX.gpio[gpio_num].mcu_oe = 0;
 }

 /**
@ -785,7 +785,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, uint32_t gpio_nu
  */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, uint32_t gpio_num)
 {
-    IOMUX.gpio[gpio_num].mcu_oe = 1;
+    IO_MUX.gpio[gpio_num].mcu_oe = 1;
 }

 #ifdef __cplusplus
--- a/components/soc/esp32/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32/include/soc/Kconfig.soc_caps.in
@ -187,6 +187,10 @@ config SOC_LP_PERIPH_SHARE_INTERRUPT
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_DPORT_WORKAROUND_DIS_INTERRUPT_LVL
    int
    default 5
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@ -104,6 +104,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED   1
 #define SOC_DEEP_SLEEP_SUPPORTED    1
 #define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source
+#define SOC_PM_SUPPORTED            1

 #if SOC_CAPS_ECO_VER < 200
 #define SOC_DPORT_WORKAROUND                   1
--- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
@ -131,6 +131,10 @@ config SOC_LP_PERIPH_SHARE_INTERRUPT
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_26M
    bool
    default y
--- a/components/soc/esp32c2/include/soc/soc_caps.h
+++ b/components/soc/esp32c2/include/soc/soc_caps.h
@ -49,6 +49,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_26M            1
--- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
@ -183,6 +183,10 @@ config SOC_LP_PERIPH_SHARE_INTERRUPT
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@ -65,6 +65,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c5/beta3/include/soc/io_mux_struct.h
@ -34,7 +34,7 @@ typedef union {
        uint32_t reserved_15:17;
    };
    uint32_t val;
-} iomux_pin_ctrl_reg_t;
+} io_mux_pin_ctrl_reg_t;

 /** Type of gpio register
 *  IO MUX Configure Register for pad XTAL_32K_P
@ -102,13 +102,13 @@ typedef union {
        uint32_t hys_en:1;
        /** hys_sel : R/W; bitpos: [17]; default: 0;
         *  Select enabling signals of the pad from software and efuse hardware. 1: Select
-         *  enabling siganl from slftware. 0: Select enabling signal from efuse hardware.
+         *  enabling signal from slftware. 0: Select enabling signal from efuse hardware.
         */
        uint32_t hys_sel:1;
        uint32_t reserved_18:14;
    };
    uint32_t val;
-} iomux_gpio_reg_t;
+} io_mux_gpio_reg_t;

 /** Type of date register
 *  IO MUX Version Control Register
@ -122,20 +122,20 @@ typedef union {
        uint32_t reserved_28:4;
    };
    uint32_t val;
-} iomux_date_reg_t;
+} io_mux_date_reg_t;


-typedef struct iomux_dev_t {
-    volatile iomux_pin_ctrl_reg_t pin_ctrl;
-    volatile iomux_gpio_reg_t gpio[27];
+typedef struct io_mux_dev_t {
+    volatile io_mux_pin_ctrl_reg_t pin_ctrl;
+    volatile io_mux_gpio_reg_t gpio[27];
    uint32_t reserved_070[35];
-    volatile iomux_date_reg_t date;
-} iomux_dev_t;
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;

-extern iomux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;

 #ifndef __cplusplus
-_Static_assert(sizeof(iomux_dev_t) == 0x100, "Invalid size of iomux_dev_t structure");
+_Static_assert(sizeof(io_mux_dev_t) == 0x100, "Invalid size of io_mux_dev_t structure");
 #endif

 #ifdef __cplusplus
--- a/components/soc/esp32c5/beta3/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/beta3/include/soc/soc_caps.h
@ -81,6 +81,7 @@
 #define SOC_MODEM_CLOCK_SUPPORTED       1     // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
 #define SOC_BT_SUPPORTED                1
 #define SOC_PHY_SUPPORTED               1
+// #define SOC_PM_SUPPORTED                1  // TODO: [ESP32C5] IDF-8643

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
+++ b/components/soc/esp32c5/beta3/ld/esp32c5.peripherals.ld
@ -41,7 +41,7 @@ PROVIDE ( DS                  = 0x6008C000 );
 PROVIDE ( HMAC                = 0x6008D000 );
 PROVIDE ( ECDSA               = 0x6008E000 );

-PROVIDE ( IOMUX               = 0x60090000 );
+PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
 PROVIDE ( GPIO_EXT            = 0x60091f00 );
 PROVIDE ( SDM                 = 0x60091f00 );
--- a/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
@ -111,17 +111,41 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
    bool
    default y

+config SOC_GPIO_PORT
+    int
+    default 1
+
 config SOC_GPIO_PIN_COUNT
    int
    default 29

+config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
+    bool
+    default y
+
+config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
+    bool
+    default y
+
 config SOC_GPIO_IN_RANGE_MAX
    int
-    default 30
+    default 28

 config SOC_GPIO_OUT_RANGE_MAX
    int
-    default 30
+    default 28
+
+config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
+    int
+    default 0
+
+config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
+    hex
+    default 0x0000000001FFFF00
+
+config SOC_GPIO_SUPPORT_FORCE_HOLD
+    bool
+    default y

 config SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
    bool
--- a/components/soc/esp32c5/mp/include/soc/io_mux_reg.h
+++ b/components/soc/esp32c5/mp/include/soc/io_mux_reg.h
--- a/components/soc/esp32c5/mp/include/soc/io_mux_struct.h
+++ b/components/soc/esp32c5/mp/include/soc/io_mux_struct.h
@ -134,7 +134,7 @@ typedef struct {
    volatile io_mux_date_reg_t date;
 } io_mux_dev_t;

-extern io_mux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;

 #ifndef __cplusplus
 _Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
--- a/components/soc/esp32c5/mp/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/mp/include/soc/soc_caps.h
@ -72,6 +72,7 @@
 // #define SOC_KEY_MANAGER_SUPPORTED       1  // TODO: [ESP32C5] IDF-8621
 // #define SOC_HUK_SUPPORTED               1  // TODO: [ESP32C5] IDF-8617
 // #define SOC_MODEM_CLOCK_SUPPORTED       1  // TODO: [ESP32C5] IDF-8845
+// #define SOC_PM_SUPPORTED                1  // TODO: [ESP32C5] IDF-8643

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
@ -174,35 +175,35 @@
 // #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group

 /*-------------------------- GPIO CAPS ---------------------------------------*/
-// TODO: [ESP32C5] IDF-8717
 // ESP32-C5 has 1 GPIO peripheral
-// #define SOC_GPIO_PORT                      1U
+#define SOC_GPIO_PORT                      1U
 #define SOC_GPIO_PIN_COUNT                 29
 // #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
 // #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM    8
+#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER      1

 // GPIO peripheral has the ETM extension
 // #define SOC_GPIO_SUPPORT_ETM          1

 // Target has the full LP IO subsystem
 // On ESP32-C5, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-// #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
+#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
 // GPIO0~7 on ESP32C5 can support chip deep sleep wakeup
-// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)
+// #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)  // TODO: [ESP32C5] IDF-8719

 #define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK

-#define SOC_GPIO_IN_RANGE_MAX           30
-#define SOC_GPIO_OUT_RANGE_MAX          30
+#define SOC_GPIO_IN_RANGE_MAX           28
+#define SOC_GPIO_OUT_RANGE_MAX          28

-// #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)

-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
-// #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_28)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x0000000001FFFF00ULL

 // Support to force hold all IOs
-// #define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
+#define SOC_GPIO_SUPPORT_FORCE_HOLD              (1)
 // Support to hold a single digital I/O when the digital domain is powered off
 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP  (1)

--- a/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
+++ b/components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
@ -39,7 +39,7 @@ PROVIDE ( ECC                 = 0x6008B000 );
 PROVIDE ( DS                  = 0x6008C000 );
 PROVIDE ( HMAC                = 0x6008D000 );
 PROVIDE ( ECDSA               = 0x6008E000 );
-PROVIDE ( IOMUX               = 0x60090000 );
+PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
 PROVIDE ( GPIO_EXT            = 0x60091f00 );
 PROVIDE ( MEM_MONITOR         = 0x60092000 );
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@ -239,6 +239,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@ -76,6 +76,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_MODEM_CLOCK_SUPPORTED       1
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@ -74,6 +74,7 @@
 // #define SOC_PAU_SUPPORTED               0
 // #define SOC_LP_I2C_SUPPORTED            0    //TODO: [ESP32C61] IDF-9330, IDF-9337
 // #define SOC_ULP_LP_UART_SUPPORTED       0    //TODO: [ESP32C61] IDF-9329, IDF-9341
+// #define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@ -227,6 +227,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_32M
    bool
    default y
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@ -73,6 +73,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_MODEM_CLOCK_SUPPORTED       1
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_32M            1
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@ -271,6 +271,10 @@ config SOC_DEEP_SLEEP_SUPPORTED
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32p4/include/soc/io_mux_struct.h
+++ b/components/soc/esp32p4/include/soc/io_mux_struct.h
@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@ -11,7 +11,7 @@ extern "C" {
 #endif

 /** Type of GPIO register
- *  IOMUX gpio configuration register
+ *  IO MUX gpio configuration register
 */
 typedef union {
    struct {
@ -36,7 +36,7 @@ typedef union {
         */
        uint32_t mcu_ie:1;
        /** mcu_drv : R/W; bitpos: [5:6]; default: 0;
-         *  select drive strenth on sleep mode
+         *  select drive strength on sleep mode
         */
        uint32_t mcu_drv:2;
        /** fun_wpd : R/W; bitpos: [7]; default: 0;
@ -52,7 +52,7 @@ typedef union {
         */
        uint32_t fun_ie:1;
        /** fun_drv : R/W; bitpos: [10:11]; default: 2;
-         *  select drive strenth, 0:5mA, 1:10mA, 2:20mA, 3:40mA
+         *  select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA
         */
        uint32_t fun_drv:2;
        /** mcu_sel : R/W; bitpos: [12:14]; default: 0;
@ -66,10 +66,10 @@ typedef union {
        uint32_t reserved16 :16;
    };
    uint32_t val;
-} iomux_gpio_reg_t;
+} io_mux_gpio_reg_t;

 /** Type of date register
- *  IOMUX version register
+ *  IO_MUX version register
 */
 typedef union {
    struct {
@ -80,20 +80,20 @@ typedef union {
        uint32_t reserved_28:4;
    };
    uint32_t val;
-} iomux_date_reg_t;
+} io_mux_date_reg_t;


-typedef struct iomux_dev_t {
+typedef struct io_mux_dev_t {
    uint32_t reserved_0;
-    volatile iomux_gpio_reg_t gpio[57];
+    volatile io_mux_gpio_reg_t gpio[57];
    uint32_t reserved_e8[7];
-    volatile iomux_date_reg_t date;
-} iomux_dev_t;
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;

-extern iomux_dev_t IOMUX;
+extern io_mux_dev_t IO_MUX;

 #ifndef __cplusplus
-_Static_assert(sizeof(iomux_dev_t) == 0x108, "Invalid size of iomux_dev_t structure");
+_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure");
 #endif

 #ifdef __cplusplus
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@ -91,6 +91,7 @@
 // #define SOC_PPA_SUPPORTED               1  //TODO: IDF-6878
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld
+++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld
@ -61,7 +61,7 @@ PROVIDE ( GPIO_EXT       = 0x500E0F00 );
 PROVIDE ( SDM            = 0x500E0F00 );
 PROVIDE ( GLITCH_FILTER  = 0x500E0F30 );
 PROVIDE ( GPIO_ETM       = 0x500E0F60 );
-PROVIDE ( IOMUX          = 0x500E1000 );
+PROVIDE ( IO_MUX         = 0x500E1000 );
 PROVIDE ( MSPI_IOMUX     = 0x500E1200 );

 PROVIDE ( HP_SYSTEM         = 0x500E5000 );
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@ -211,6 +211,10 @@ config SOC_LP_PERIPH_SHARE_INTERRUPT
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@ -89,6 +89,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
@ -251,6 +251,10 @@ config SOC_LP_PERIPH_SHARE_INTERRUPT
    bool
    default y

+config SOC_PM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
    bool
    default y
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@ -79,6 +79,7 @@
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
 #define SOC_DEEP_SLEEP_SUPPORTED        1
 #define SOC_LP_PERIPH_SHARE_INTERRUPT   1   // LP peripherals sharing the same interrupt source
+#define SOC_PM_SUPPORTED                1

 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1
--- a/docs/docs_not_updated/esp32c5.txt
+++ b/docs/docs_not_updated/esp32c5.txt
@ -112,7 +112,6 @@ api-reference/peripherals/usb_host/usb_host_notes_design.rst
 api-reference/peripherals/usb_host/usb_host_notes_usbh.rst
 api-reference/peripherals/hmac.rst
 api-reference/peripherals/usb_device.rst
-api-reference/peripherals/gpio.rst
 api-reference/peripherals/sdspi_host.rst
 api-reference/peripherals/spi_slave.rst
 api-reference/peripherals/etm.rst
--- a/docs/en/api-reference/peripherals/gpio.rst
+++ b/docs/en/api-reference/peripherals/gpio.rst
@ -73,7 +73,9 @@ In addition, if you would like to dump the configurations of all IOs, you can us

 If an IO pin is routed to a peripheral signal through the GPIO matrix, the signal ID printed in the dump information is defined in the :component_file:`soc/{IDF_TARGET_PATH_NAME}/include/soc/gpio_sig_map.h` header file. The word ``**RESERVED**`` indicates the IO is occupied by either SPI flash or PSRAM. It is strongly not recommended to reconfigure them for other application purposes.

-.. only:: esp32c3 or esp32c6 or esp32h2 or esp32p4 or esp32s2 or esp32s3
+Do not rely on the default configurations values in the Technical Reference Manual, because it may be changed in the bootloader or application startup code before app_main.
+
+.. only:: esp32c3 or esp32c6 or esp32h2 or esp32p4 or esp32s2 or esp32s3 or esp32c5

    Configure USB PHY Pins to GPIO
    -------------------------------
--- a/docs/en/api-reference/peripherals/gpio/esp32c5.inc
+++ b/docs/en/api-reference/peripherals/gpio/esp32c5.inc
@ -9,8 +9,6 @@

 .. gpio-summary

-Current GPIOs are for {IDF_TARGET_NAME} beta3 version. {IDF_TARGET_NAME} MP version would have 2 more available IOs, and some pin functions are changed. The {IDF_TARGET_NAME} MP version will be updated later.
-
 The {IDF_TARGET_NAME} chip features 27 physical GPIO pins (GPIO0 ~ GPIO26). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].

 The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@ -42,7 +40,7 @@ The table below provides more information on pin usage, and please note the comm
    * - GPIO3
      - ADC1_CH2
      - LP_GPIO3
-      - Strapping pin
+      -

    * - GPIO4
      - ADC1_CH3
@ -57,7 +55,7 @@ The table below provides more information on pin usage, and please note the comm
    * - GPIO6
      - ADC1_CH5
      - LP_GPIO6
-      - Strapping pin
+      -

    * - GPIO7
      -
@ -92,12 +90,12 @@ The table below provides more information on pin usage, and please note the comm
    * - GPIO13
      -
      -
-      -
+      - USB-JTAG

    * - GPIO14
      -
      -
-      -
+      - USB-JTAG

    * - GPIO15
      -
@ -107,12 +105,12 @@ The table below provides more information on pin usage, and please note the comm
    * - GPIO16
      -
      -
-      -
+      - SPI0/1

    * - GPIO17
      -
      -
-      -
+      - SPI0/1

    * - GPIO18
      -
@ -142,27 +140,37 @@ The table below provides more information on pin usage, and please note the comm
    * - GPIO23
      -
      -
-      - SPI0/1
+      -

    * - GPIO24
      -
      -
-      - SPI0/1
+      -

    * - GPIO25
      -
      -
-      - USB-JTAG
+      -

    * - GPIO26
      -
      -
-      - USB-JTAG
+      -
+
+    * - GPIO27
+      -
+      -
+      - Strapping pin
+
+    * - GPIO28
+      -
+      -
+      - Strapping pin

 .. note::

-    - Strapping pin: GPIO2, GPIO3, GPIO6, and GPIO7 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
-	  - SPI0/1: GPIO18 ~ GPIO24 are usually used for SPI flash and not recommended for other uses.
-	  - USB-JTAG: GPIO25 and GPIO26 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.
+    - Strapping pin: GPIO2, GPIO7, GPIO27, and GPIO28 are strapping pins. For more information, please refer to `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__.
+	  - SPI0/1: GPIO16 ~ GPIO22 are usually used for SPI flash and not recommended for other uses.
+	  - USB-JTAG: GPIO13 and GPIO14 are used by USB-JTAG by default. If they are reconfigured to operate as normal GPIOs, USB-JTAG functionality will be disabled.

 ---
--- a/docs/zh_CN/api-reference/peripherals/gpio.rst
+++ b/docs/zh_CN/api-reference/peripherals/gpio.rst
@ -73,7 +73,9 @@ GPIO 驱动提供了一个函数 :cpp:func:`gpio_dump_io_configuration` 用来

 如果 IO 管脚通过 GPIO 交换矩阵连接到内部外设信号，输出信息打印中的外设信号 ID 定义可以在 :component_file:`soc/{IDF_TARGET_PATH_NAME}/include/soc/gpio_sig_map.h` 头文件中查看。``**RESERVED**`` 字样则表示此 IO 用于连接 SPI flash 或 PSRAM，强烈建议不要重新配置这些管脚用于其他功能。

-.. only:: esp32c3 or esp32c6 or esp32h2 or esp32p4 or esp32s2 or esp32s3
+请不要依赖技术参考手册中记录的GPIO默认配置状态，因为特殊用途的GPIO可能会在app_main之前被引导程序或应用程序启动阶段的代码更改。
+
+.. only:: esp32c3 or esp32c6 or esp32h2 or esp32p4 or esp32s2 or esp32s3 or esp32c5

    配置 USB PHY 管脚 为普通 GPIO 管脚
    ---------------------------------------
--- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc
+++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c5.inc
@ -9,9 +9,7 @@

 .. gpio-summary

-当前的 GPIO 适用于 {IDF_TARGET_NAME} beta3 版本。{IDF_TARGET_NAME} MP 版本将会增加 2 个可用的 IO，并且一些引脚功能将会改变。{IDF_TARGET_NAME} MP 版本将会在以后更新。
-
-{IDF_TARGET_NAME} 芯片具有 27 个物理 GPIO 管脚（GPIO0 ~ GPIO26）。每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。
+{IDF_TARGET_NAME} 芯片具有 29 个物理 GPIO 管脚（GPIO0 ~ GPIO28）。每个管脚都可用作一个通用 IO，或连接一个内部的外设信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。

 下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。

@ -42,7 +40,7 @@
    * - GPIO3
      - ADC1_CH2
      - LP_GPIO3
-      - Strapping 管脚
+      -

    * - GPIO4
      - ADC1_CH3
@ -57,7 +55,7 @@
    * - GPIO6
      - ADC1_CH5
      - LP_GPIO6
-      - Strapping 管脚
+      -

    * - GPIO7
      -
@ -92,12 +90,12 @@
    * - GPIO13
      -
      -
-      -
+      - USB-JTAG

    * - GPIO14
      -
      -
-      -
+      - USB-JTAG

    * - GPIO15
      -
@ -107,12 +105,12 @@
    * - GPIO16
      -
      -
-      -
+      - SPI0/1

    * - GPIO17
      -
      -
-      -
+      - SPI0/1

    * - GPIO18
      -
@ -142,27 +140,37 @@
    * - GPIO23
      -
      -
-      - SPI0/1
+      -

    * - GPIO24
      -
      -
-      - SPI0/1
+      -

    * - GPIO25
      -
      -
-      - USB-JTAG
+      -

    * - GPIO26
      -
      -
-      - USB-JTAG
+      -
+
+    * - GPIO27
+      -
+      -
+      - Strapping 管脚
+
+    * - GPIO28
+      -
+      -
+      - Strapping 管脚

 .. note::

-    - Strapping 管脚：GPIO2、GPIO3、GPIO6 和 GPIO7 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
-    - SPI0/1：GPIO18 ~ GPIO24 通常用于 SPI flash，不推荐用于其他用途。
-    - USB-JTAG：GPIO25 和 GPIO26 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。
+    - Strapping 管脚：GPIO2、GPIO7、GPIO27 和 GPIO28 是 Strapping 管脚。更多信息请参考 `ESP32-C5 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_。
+    - SPI0/1：GPIO16 ~ GPIO22 通常用于 SPI flash，不推荐用于其他用途。
+    - USB-JTAG：GPIO13 和 GPIO14 默认用于 USB-JTAG。如果将它们配置为普通 GPIO，驱动程序将禁用 USB-JTAG 功能。

 ---
--- a/examples/peripherals/.build-test-rules.yml
+++ b/examples/peripherals/.build-test-rules.yml
@ -46,10 +46,6 @@ examples/peripherals/dac/dac_cosine_wave:
    - esp_driver_dac

 examples/peripherals/gpio:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: GPIO is not supported on ESP32-C5  # TODO: [ESP32C5] IDF-8717
  depends_components:
    - esp_driver_gpio

--- a/examples/peripherals/gpio/generic_gpio/README.md
+++ b/examples/peripherals/gpio/generic_gpio/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

 # Example: GPIO

--- a/examples/storage/.build-test-rules.yml
+++ b/examples/storage/.build-test-rules.yml
@ -46,10 +46,6 @@ examples/storage/nvs_rw_blob:
  depends_components:
    - nvs_flash
    - driver
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not supported yet  # TODO: [ESP32C5] IDF-8717
  disable_test:
    - if: IDF_TARGET not in ["esp32", "esp32c3"]
      reason: only one target per arch needed
--- a/examples/storage/nvs_rw_blob/README.md
+++ b/examples/storage/nvs_rw_blob/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

 # Non-Volatile Storage (NVS) Read and Write Example

--- a/examples/system/.build-test-rules.yml
+++ b/examples/system/.build-test-rules.yml
@ -79,10 +79,6 @@ examples/system/freertos:
    - freertos

 examples/system/gcov:
-  disable:
-    - if: IDF_TARGET == "esp32c5"
-      temporary: true
-      reason: not supported yet #TODO: IDF-8717
  disable_test:
    - if: IDF_TARGET != "esp32"
      temporary: true