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docs(spi_master): fixed timing comments that only apply for ESP32
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@ -89,7 +89,8 @@ typedef spi_common_dma_t spi_dma_chan_t;
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*
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* You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the
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* GPIO matrix to route the signals. An exception is made when all signals either can be routed through
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* the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds.
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* the IO_MUX or are -1. In that case, the IO_MUX is used. On ESP32, using GPIO matrix will bring about 25ns of input
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* delay, which may cause incorrect read for >40MHz speeds.
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*
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* @note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized.
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*/
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@ -165,8 +165,13 @@ typedef struct spi_device_t *spi_device_handle_t; ///< Handle for a device on a
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* peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control
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* up to three devices.
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*
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* @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are
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* supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz.
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* @note On ESP32, due to the delay of GPIO matrix, the maximum frequency SPI Master can correctly samples the slave's
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* output is lower than the case using IOMUX. Typical maximum frequency communicating with an ideal slave
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* without data output delay: 80MHz (IOMUX pins) and 26MHz (GPIO matrix pins). With the help of extra dummy
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* cycles in half-duplex mode, the delay can be compensated by setting `input_delay_ns` in `dev_config` structure
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* correctly.
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*
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* There's no notable delay on chips other than ESP32.
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*
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* @param host_id SPI peripheral to allocate device on
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* @param dev_config SPI interface protocol config for the device
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