mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
esp32s2: Support bootloader_random_enable()
This commit is contained in:
Angus Gratton
parent
a416452657
commit
699742acc6
@ -42,6 +42,7 @@ SECTIONS
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*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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@ -29,6 +29,7 @@ SECTIONS
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*libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
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*libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
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*libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
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@ -5,6 +5,7 @@ set(srcs
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"src/bootloader_flash.c"
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"src/bootloader_mem.c"
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"src/bootloader_random.c"
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"src/bootloader_random_${IDF_TARGET}.c"
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"src/bootloader_utility.c"
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"src/esp_image_format.c"
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"src/flash_encrypt.c"
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@ -24,9 +24,10 @@ COMPONENT_OBJEXCLUDE := src/bootloader_init.o \
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endif
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COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \
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src/bootloader_flash_config_esp32s3.o \
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src/bootloader_efuse_esp32s2.o \
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src/bootloader_efuse_esp32s3.o \
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src/bootloader_flash_config_esp32s3.o \
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src/bootloader_efuse_esp32s2.o \
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src/bootloader_efuse_esp32s3.o \
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src/bootloader_random_esp32s2.o
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ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
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ifndef CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
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@ -1,4 +1,4 @@
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@ -15,16 +15,6 @@
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#include "bootloader_random.h"
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#include "soc/cpu.h"
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#include "soc/wdev_reg.h"
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#include "soc/rtc_periph.h"
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#include "soc/sens_periph.h"
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#include "soc/syscon_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/i2s_periph.h"
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#include "esp_log.h"
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#include "soc/io_mux_reg.h"
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#include "soc/apb_saradc_reg.h"
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#endif
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#ifndef BOOTLOADER_BUILD
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#include "esp_system.h"
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@ -64,177 +54,3 @@
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}
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}
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#endif // BOOTLOADER_BUILD
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void bootloader_random_enable(void)
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{
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/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
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never disabled while the CPU is running), this is a "belts and braces" type check.
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*/
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#ifdef BOOTLOADER_BUILD
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#if CONFIG_IDF_TARGET_ESP32S3
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SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_RNG_EN);
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#else
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
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#endif
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#else
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
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reference via I2S into the RNG entropy input.
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Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
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in early bootloader startup must have been made.
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*/
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
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SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_enable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
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#elif CONFIG_IDF_TARGET_ESP32S2
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/* Disable IO1 digital function for random function. */
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PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U);
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WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF);
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SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP);
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#elif CONFIG_IDF_TARGET_ESP32S3
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/* Disable IO1 digital function for random function. */
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PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U);
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PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U);
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WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF);
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SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
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SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP);
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#endif
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// Test pattern configuration byte 0xAD:
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//--[7:4] channel_sel: 10-->en_test
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//--[3:2] bit_width : 3-->12bit
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//--[1:0] atten : 1-->3dB attenuation
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#if CONFIG_IDF_TARGET_ESP32
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
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WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
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WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
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WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
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WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
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SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
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SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
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SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
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SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
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#elif CONFIG_IDF_TARGET_ESP32S2
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SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S);
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SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */
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SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S);
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SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL);
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CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_SAR_SEL);
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SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
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SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S);
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#endif
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#if !CONFIG_IDF_TARGET_ESP32S3
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
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SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
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#endif
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}
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void bootloader_random_disable(void)
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{
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#if !CONFIG_IDF_TARGET_ESP32S3
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/* Reset some i2s configuration (possibly redundant as we reset entire
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I2S peripheral further down). */
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
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SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
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CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
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#endif
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/* Disable i2s clock */
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#ifdef BOOTLOADER_BUILD
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#if CONFIG_IDF_TARGET_ESP32S3
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CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN);
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#else
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#endif
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#else
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periph_module_disable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Restore SYSCON mode registers */
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#if CONFIG_IDF_TARGET_ESP32
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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/* Restore SAR ADC mode */
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CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
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| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST);
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CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S);
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
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#endif
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/* Reset i2s peripheral */
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#ifdef BOOTLOADER_BUILD
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#if CONFIG_IDF_TARGET_ESP32S3
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SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST);
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CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST);
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#else
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
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#endif
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#else
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periph_module_reset(PERIPH_I2S0_MODULE);
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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/* Disable pull supply voltage to SAR ADC */
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CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
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#endif
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}
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128
components/bootloader_support/src/bootloader_random_esp32.c
Normal file
128
components/bootloader_support/src/bootloader_random_esp32.c
Normal file
@ -0,0 +1,128 @@
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// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/rtc_periph.h"
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#include "soc/sens_periph.h"
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#include "soc/syscon_periph.h"
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#include "soc/dport_reg.h"
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#include "soc/i2s_periph.h"
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#include "esp_log.h"
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#include "soc/io_mux_reg.h"
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#ifndef BOOTLOADER_BUILD
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#include "driver/periph_ctrl.h"
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#endif
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void bootloader_random_enable(void)
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{
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/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
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never disabled while the CPU is running), this is a "belts and braces" type check.
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*/
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
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#else
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periph_module_enable(PERIPH_RNG_MODULE);
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#endif // BOOTLOADER_BUILD
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/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
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reference via I2S into the RNG entropy input.
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Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M)
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in early bootloader startup must have been made.
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*/
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SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S);
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SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
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SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
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#ifdef BOOTLOADER_BUILD
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
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#else
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periph_module_enable(PERIPH_I2S0_MODULE);
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#endif // BOOTLOADER_BUILD
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
|
||||
|
||||
// Test pattern configuration byte 0xAD:
|
||||
//--[7:4] channel_sel: 10-->en_test
|
||||
//--[3:2] bit_width : 3-->12bit
|
||||
//--[1:0] atten : 1-->3dB attenuation
|
||||
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD);
|
||||
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD);
|
||||
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD);
|
||||
WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
|
||||
SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
|
||||
|
||||
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX);
|
||||
SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S);
|
||||
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */
|
||||
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S);
|
||||
SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S);
|
||||
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL);
|
||||
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL);
|
||||
SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S);
|
||||
SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S);
|
||||
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
|
||||
SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
|
||||
SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
|
||||
SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
|
||||
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
/* Reset some i2s configuration (possibly redundant as we reset entire
|
||||
I2S peripheral further down). */
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START);
|
||||
SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET);
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN);
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN);
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN);
|
||||
CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE);
|
||||
|
||||
/* Disable i2s clock */
|
||||
#ifdef BOOTLOADER_BUILD
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
|
||||
#else
|
||||
periph_module_disable(PERIPH_I2S0_MODULE);
|
||||
#endif // BOOTLOADER_BUILD
|
||||
|
||||
/* Restore SYSCON mode registers */
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE);
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE);
|
||||
|
||||
/* Restore SAR ADC mode */
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
|
||||
CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX
|
||||
| SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S);
|
||||
SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
|
||||
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
|
||||
|
||||
/* Reset i2s peripheral */
|
||||
#ifdef BOOTLOADER_BUILD
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
|
||||
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
|
||||
#else
|
||||
periph_module_reset(PERIPH_I2S0_MODULE);
|
||||
#endif
|
||||
|
||||
/* Disable pull supply voltage to SAR ADC */
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
|
||||
SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S);
|
||||
}
|
||||
@ -0,0 +1,97 @@
|
||||
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#include "sdkconfig.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "soc/rtc_periph.h"
|
||||
#include "soc/sens_periph.h"
|
||||
#include "soc/syscon_periph.h"
|
||||
#include "soc/dport_reg.h"
|
||||
#include "soc/i2s_periph.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/io_mux_reg.h"
|
||||
#include "soc/apb_saradc_reg.h"
|
||||
#include "regi2c_ctrl.h"
|
||||
#include "hal/adc_ll.h"
|
||||
|
||||
#ifndef BOOTLOADER_BUILD
|
||||
#include "driver/periph_ctrl.h"
|
||||
#endif
|
||||
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
/* Ensure the Wifi clock for RNG modiule is enabled following a soft reset. This should always be the case already
|
||||
(this clock is never disabled while the CPU is running), this is a "belt and braces" type check.
|
||||
*/
|
||||
#ifdef BOOTLOADER_BUILD
|
||||
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
|
||||
#else
|
||||
periph_module_enable(PERIPH_RNG_MODULE);
|
||||
#endif // BOOTLOADER_BUILD
|
||||
|
||||
// Enable SAR ADC to read a disconnected input for additional entropy
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG,DPORT_APB_SARADC_CLK_EN);
|
||||
|
||||
REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2);
|
||||
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
|
||||
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
|
||||
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
|
||||
SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
|
||||
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x4);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x4);
|
||||
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 1);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
|
||||
|
||||
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0);
|
||||
WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffffff); // set adc1 channel & bitwidth & atten
|
||||
|
||||
REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0);
|
||||
WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffffff); //set adc2 channel & bitwidth & atten
|
||||
|
||||
SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG,SENS_SAR1_DIG_FORCE);
|
||||
|
||||
REG_SET_FIELD(APB_SARADC_CTRL_REG,APB_SARADC_WORK_MODE, 1);
|
||||
|
||||
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_MEAS_NUM_LIMIT);
|
||||
|
||||
REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3);
|
||||
|
||||
SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_SEL);
|
||||
|
||||
REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100);
|
||||
|
||||
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG,APB_SARADC_START_FORCE);
|
||||
|
||||
SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN);
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
/* Restore internal I2C bus state */
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x1);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x1);
|
||||
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 0);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
|
||||
REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
|
||||
|
||||
/* Restore SARADC to default mode */
|
||||
CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
|
||||
SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG, DPORT_APB_SARADC_CLK_EN);
|
||||
SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
|
||||
CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN);
|
||||
}
|
||||
@ -69,6 +69,66 @@ typedef enum {
|
||||
ADC2_CTRL_FORCE_DIG = 6, /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
|
||||
} adc_controller_t;
|
||||
|
||||
/* ADC calibration defines. */
|
||||
#define ADC_LL_I2C_ADC 0X69
|
||||
#define ADC_LL_I2C_ADC_HOSTID 0
|
||||
|
||||
#define ADC_LL_ANA_CONFIG2_REG 0x6000E048
|
||||
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
|
||||
#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
|
||||
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
|
||||
#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
|
||||
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR 0x0
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_LL_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_LL_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_LL_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1
|
||||
#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0
|
||||
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2
|
||||
#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2
|
||||
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3
|
||||
#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3
|
||||
|
||||
#define ADC_LL_SARADC_ENCAL_REF_ADDR 0x7
|
||||
#define ADC_LL_SARADC_ENCAL_REF_ADDR_MSB 4
|
||||
#define ADC_LL_SARADC_ENCAL_REF_ADDR_LSB 4
|
||||
|
||||
/* ADC calibration defines end. */
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Digital controller setting
|
||||
---------------------------------------------------------------*/
|
||||
@ -1252,4 +1312,4 @@ static inline void adc_ll_vref_output(adc_ll_num_t adc, adc_channel_t channel, b
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user