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Enable IO20 on ESP32

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Some newer ESP32 variants (like ESP32-PICO-V3 and ESP32-PICO-MINI-02)
do implement this pin and it can be used as a normal GPIO.

Fixes #6016
Fixes #6837

Closes https://github.com/espressif/esp-idf/pull/6918

(cherry picked from commit 6deaefde69)
This commit is contained in:
Alberto García Hierro 2021-04-21 22:01:14 +01:00 committed by songruojing
parent f80c0e8d31
commit 68f8b999bb
2 changed files with 3 additions and 3 deletions
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2
components/soc/esp32/gpio_periph.c
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@ -35,7 +35,7 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
IO_MUX_GPIO17_REG,
IO_MUX_GPIO18_REG,
IO_MUX_GPIO19_REG,
0,
IO_MUX_GPIO20_REG, // This corresponding pin is only available on ESP32-PICO-V3 chip package
IO_MUX_GPIO21_REG,
IO_MUX_GPIO22_REG,
IO_MUX_GPIO23_REG,

4
components/soc/esp32/include/soc/soc_caps.h
View File

@ -114,8 +114,8 @@
// set pullup/down/capability via RTC register. On ESP32-S2, Digital IOs have their own registers to
// control pullup/down/capability, independent with RTC registers.
// 0~39 except from 20, 24, 28~31 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT20 | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// 0~39 except from 24, 28~31 are valid
#define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFULL & ~(0ULL | BIT24 | BIT28 | BIT29 | BIT30 | BIT31))
// GPIO >= 34 are input only
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT34 | BIT35 | BIT36 | BIT37 | BIT38 | BIT39))