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change(cpu_start): added note about internal ram only stage

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This commit is contained in:
Armando 2023-11-03 12:14:06 +08:00
parent 168ff6e268
commit 687064b2f8
3 changed files with 16 additions and 8 deletions
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2
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
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@ -22,7 +22,7 @@
#include "hal/cache_hal.h" #include "hal/cache_hal.h"
#include "hal/cache_ll.h" #include "hal/cache_ll.h"
void bootloader_flash_update_id() void IRAM_ATTR bootloader_flash_update_id()
{ {
esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip; esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
chip->device_id = bootloader_read_flash_id(); chip->device_id = bootloader_read_flash_id();

15
components/esp_system/port/cpu_start.c
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@ -90,6 +90,7 @@
#include "esp_private/spi_flash_os.h" #include "esp_private/spi_flash_os.h"
#include "esp_private/mspi_timing_tuning.h" #include "esp_private/mspi_timing_tuning.h"
#include "esp_private/esp_gpio_reserve.h"
#include "bootloader_flash_config.h" #include "bootloader_flash_config.h"
#include "bootloader_flash.h" #include "bootloader_flash.h"
#include "esp_private/crosscore_int.h" #include "esp_private/crosscore_int.h"
@ -576,6 +577,20 @@ void IRAM_ATTR call_start_cpu0(void)
#endif #endif
} }
#endif #endif
//----------------------------------Separator-----------------------------//
/**
* @note
* After this stage, you can place non-internal ram code
*/
/* Reserve the GPIO pins */
uint64_t reserve_pin_mask = 0;
for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
}
esp_gpio_reserve_pins(reserve_pin_mask);
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

7
components/spi_flash/flash_ops.c
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@ -24,7 +24,6 @@
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "esp_private/spi_flash_os.h" #include "esp_private/spi_flash_os.h"
#include "esp_private/esp_clk.h" #include "esp_private/esp_clk.h"
#include "esp_private/esp_gpio_reserve.h"
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h" #include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h" #include "esp32/rom/spi_flash.h"
@ -150,12 +149,6 @@ void IRAM_ATTR esp_mspi_pin_init(void)
} }
//Set F4R4 board pin drive strength. TODO: IDF-3663 //Set F4R4 board pin drive strength. TODO: IDF-3663
#endif #endif
/* Reserve the GPIO pins */
uint64_t reserve_pin_mask = 0;
for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
}
esp_gpio_reserve(reserve_pin_mask);
} }
esp_err_t IRAM_ATTR spi_flash_init_chip_state(void) esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)