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change(cpu_start): added note about internal ram only stage
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168ff6e268
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687064b2f8
@ -22,7 +22,7 @@
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#include "hal/cache_hal.h"
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#include "hal/cache_ll.h"
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void bootloader_flash_update_id()
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void IRAM_ATTR bootloader_flash_update_id()
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{
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esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
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chip->device_id = bootloader_read_flash_id();
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@ -90,6 +90,7 @@
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/mspi_timing_tuning.h"
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#include "esp_private/esp_gpio_reserve.h"
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#include "bootloader_flash_config.h"
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#include "bootloader_flash.h"
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#include "esp_private/crosscore_int.h"
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@ -576,6 +577,20 @@ void IRAM_ATTR call_start_cpu0(void)
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#endif
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}
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#endif
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//----------------------------------Separator-----------------------------//
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/**
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* @note
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* After this stage, you can place non-internal ram code
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*/
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/* Reserve the GPIO pins */
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uint64_t reserve_pin_mask = 0;
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for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
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reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
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}
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esp_gpio_reserve_pins(reserve_pin_mask);
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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@ -24,7 +24,6 @@
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#include "esp_private/system_internal.h"
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#include "esp_private/spi_flash_os.h"
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#include "esp_private/esp_clk.h"
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#include "esp_private/esp_gpio_reserve.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#include "esp32/rom/spi_flash.h"
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@ -150,12 +149,6 @@ void IRAM_ATTR esp_mspi_pin_init(void)
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}
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//Set F4R4 board pin drive strength. TODO: IDF-3663
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#endif
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/* Reserve the GPIO pins */
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uint64_t reserve_pin_mask = 0;
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for (esp_mspi_io_t i = 0; i < ESP_MSPI_IO_MAX; i++) {
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reserve_pin_mask |= BIT64(esp_mspi_get_io(i));
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}
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esp_gpio_reserve(reserve_pin_mask);
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}
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esp_err_t IRAM_ATTR spi_flash_init_chip_state(void)
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