feat(cache): supported cache on c61

components/esp_mm/test_apps/mm/main/test_cache_msync.c

@@ -40,6 +40,12 @@ const static char *TAG = "CACHE_TEST";
 #elif CONFIG_IDF_TARGET_ESP32P4
 #define TEST_SYNC_START   (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
 #define TEST_SYNC_SIZE    CONFIG_CACHE_L2_CACHE_SIZE
+#elif CONFIG_IDF_TARGET_ESP32C5
+#define TEST_SYNC_START   (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
+#define TEST_SYNC_SIZE    CONFIG_CACHE_L1_CACHE_SIZE
+#elif CONFIG_IDF_TARGET_ESP32C61
+#define TEST_SYNC_START   (SOC_DRAM_PSRAM_ADDRESS_LOW + TEST_OFFSET)
+#define TEST_SYNC_SIZE    CONFIG_CACHE_L1_CACHE_SIZE
 #endif
 
 #define RECORD_TIME_PREPARE()   uint32_t __t1, __t2

components/esp_system/port/soc/esp32c5/Kconfig.cache

@@ -0,0 +1,11 @@
+menu "Cache config"
+
+    config CACHE_L1_CACHE_SIZE
+        hex
+        default 0x8000
+
+    config CACHE_L1_CACHE_LINE_SIZE
+        int
+        default 32
+
+endmenu  # Cache config

components/esp_system/port/soc/esp32c61/Kconfig.cache

@@ -0,0 +1,11 @@
+menu "Cache config"
+
+    config CACHE_L1_CACHE_SIZE
+        hex
+        default 0x8000
+
+    config CACHE_L1_CACHE_LINE_SIZE
+        int
+        default 32
+
+endmenu  # Cache config

components/hal/esp32c5/include/hal/cache_ll.h

@@ -128,6 +128,23 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Writeback cache supported addr
+ *
+ * Writeback a cache item
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ * @param vaddr             start address of the region to be written back
+ * @param size              size of the region to be written back
+ */
+__attribute__((always_inline))
+static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
+{
+    Cache_WriteBack_Addr(vaddr, size);
+}
+
 /**
  * @brief Freeze Cache
  *

components/hal/esp32c61/include/hal/cache_ll.h

@@ -15,8 +15,6 @@
 #include "hal/assert.h"
 #include "esp32c61/rom/cache.h"
 
-//TODO: [ESP32C61] IDF-9253, inherit from c6
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -129,6 +127,23 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t
     Cache_Invalidate_Addr(vaddr, size);
 }
 
+/**
+ * @brief Writeback cache supported addr
+ *
+ * Writeback a cache item
+ *
+ * @param cache_level       level of the cache
+ * @param type              see `cache_type_t`
+ * @param cache_id          id of the cache in this type and level
+ * @param vaddr             start address of the region to be written back
+ * @param size              size of the region to be written back
+ */
+__attribute__((always_inline))
+static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
+{
+    Cache_WriteBack_Addr(vaddr, size);
+}
+
 /**
  * @brief Freeze Cache
  *
@@ -192,7 +207,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
 
     uint32_t vaddr_end = vaddr_start + len - 1;
     if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW && vaddr_end < SOC_IRAM0_CACHE_ADDRESS_HIGH) {
-        //c6 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
+        //c61 the I/D bus memory are shared, so we always return `CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0`
         mask = (cache_bus_mask_t)(mask | (CACHE_BUS_IBUS0 | CACHE_BUS_DBUS0));
     } else {
         HAL_ASSERT(0);          //Out of region
@@ -212,7 +227,6 @@ __attribute__((always_inline))
 #endif
 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
 {
-    //TODO: [ESP32C61] IDF-9253, inherit from c6
     HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
     //On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
     HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -235,7 +249,6 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
 __attribute__((always_inline))
 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
 {
-    //TODO: [ESP32C61] IDF-9253, inherit from c6
     HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
     //On esp32c61, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
     HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
@@ -287,6 +300,7 @@ static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32
  */
 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
+    // TODO: [ESP32C61] IDF-9252 (inherit from C6)
     SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG, mask);
 }
 
@@ -298,6 +312,7 @@ static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint3
  */
 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
 {
+    // TODO: [ESP32C61] IDF-9252 (inherit from C6)
     SET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, mask);
 }
 
@@ -311,6 +326,7 @@ static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32
  */
 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
 {
+    // TODO: [ESP32C61] IDF-9252 (inherit from C6)
     return GET_PERI_REG_MASK(CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG, mask);
 }
 

components/heap/port/esp32c61/memory_layout.c

@@ -12,8 +12,6 @@
 #include "heap_memory_layout.h"
 #include "esp_heap_caps.h"
 
-//TODO: [ESP32C61] IDF-9253
-
 /**
  * @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
  * Each type of memory map consists of one or more regions in the address space.

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -315,6 +315,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y
 
+config SOC_CACHE_WRITEBACK_SUPPORTED
+    bool
+    default y
+
 config SOC_CACHE_FREEZE_SUPPORTED
     bool
     default y

components/soc/esp32c5/include/soc/ext_mem_defs.h

@@ -32,6 +32,12 @@ extern "C" {
 #define SOC_DRAM_FLASH_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
 #define SOC_DRAM_FLASH_ADDRESS_HIGH                  SOC_DRAM0_CACHE_ADDRESS_HIGH
 
+#define SOC_IRAM_PSRAM_ADDRESS_LOW                   SOC_IRAM0_CACHE_ADDRESS_LOW
+#define SOC_IRAM_PSRAM_ADDRESS_HIGH                  SOC_IRAM0_CACHE_ADDRESS_HIGH
+
+#define SOC_DRAM_PSRAM_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
+#define SOC_DRAM_PSRAM_ADDRESS_HIGH                  SOC_DRAM0_CACHE_ADDRESS_HIGH
+
 #define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
 #define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 

components/soc/esp32c5/include/soc/soc_caps.h

@@ -144,6 +144,7 @@
 
 /*-------------------------- CACHE CAPS --------------------------------------*/
 #define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_WRITEBACK_SUPPORTED           1
 #define SOC_CACHE_FREEZE_SUPPORTED              1
 
 /*-------------------------- CPU CAPS ----------------------------------------*/

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -99,6 +99,10 @@ config SOC_SHARED_IDCACHE_SUPPORTED
     bool
     default y
 
+config SOC_CACHE_WRITEBACK_SUPPORTED
+    bool
+    default y
+
 config SOC_CACHE_FREEZE_SUPPORTED
     bool
     default y

components/soc/esp32c61/include/soc/ext_mem_defs.h

@@ -32,6 +32,12 @@ extern "C" {
 #define SOC_DRAM_FLASH_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
 #define SOC_DRAM_FLASH_ADDRESS_HIGH                  SOC_DRAM0_CACHE_ADDRESS_HIGH
 
+#define SOC_IRAM_PSRAM_ADDRESS_LOW                   SOC_IRAM0_CACHE_ADDRESS_LOW
+#define SOC_IRAM_PSRAM_ADDRESS_HIGH                  SOC_IRAM0_CACHE_ADDRESS_HIGH
+
+#define SOC_DRAM_PSRAM_ADDRESS_LOW                   SOC_DRAM0_CACHE_ADDRESS_LOW
+#define SOC_DRAM_PSRAM_ADDRESS_HIGH                  SOC_DRAM0_CACHE_ADDRESS_HIGH
+
 #define SOC_BUS_SIZE(bus_name)                       (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
 #define SOC_ADDRESS_IN_BUS(bus_name, vaddr)          ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
 
@@ -128,26 +134,6 @@ extern "C" {
 _Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
 #endif
 
-
-/**
- * ROM flash mmap driver needs below definitions
- */
-#define CACHE_IROM_MMU_START            0
-#define CACHE_IROM_MMU_END              Cache_Get_IROM_MMU_End()
-#define CACHE_IROM_MMU_SIZE             (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
-
-#define CACHE_DROM_MMU_START            CACHE_IROM_MMU_END
-#define CACHE_DROM_MMU_END              Cache_Get_DROM_MMU_End()
-#define CACHE_DROM_MMU_SIZE             (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
-
-#define CACHE_DROM_MMU_MAX_END          0x400
-
-#define ICACHE_MMU_SIZE                 0x200
-#define DCACHE_MMU_SIZE                 0x200
-
-#define MMU_BUS_START(i)                0
-#define MMU_BUS_SIZE(i)                 0x200
-
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c61/include/soc/soc_caps.h

@@ -134,6 +134,7 @@
 
 /*-------------------------- CACHE CAPS --------------------------------------*/
 #define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_CACHE_WRITEBACK_SUPPORTED           1
 #define SOC_CACHE_FREEZE_SUPPORTED              1
 
 /*-------------------------- CPU CAPS ----------------------------------------*/

components/spi_flash/cache_utils.c

@@ -501,7 +501,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
     int i;
     bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
     uint32_t drom0_in_icache = 1;//always 1 in esp32s2
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C61 //TODO: [ESP32C61] IDF-9253
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C61 //TODO: IDF-4307
     drom0_in_icache = 0;
 #endif
 

components/spi_flash/spi_flash_os_func_noos.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -59,7 +59,6 @@ static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
 
 static IRAM_ATTR esp_err_t start(void *arg)
 {
-    // TODO: [ESP32C5] IDF-8646
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Disable(0);
     Cache_Read_Disable(1);
@@ -70,19 +69,20 @@ static IRAM_ATTR esp_err_t start(void *arg)
 #elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
     spi_noos_arg_t *spi_arg = arg;
     spi_arg->icache_autoload = Cache_Suspend_ICache();
-#elif CONFIG_IDF_TARGET_ESP32C61    // TODO: [ESP32C61] IDF-9253
+#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
     spi_noos_arg_t *spi_arg = arg;
     spi_arg->icache_autoload = Cache_Suspend_Cache();
 #elif CONFIG_IDF_TARGET_ESP32P4
     spi_noos_arg_t *spi_arg = arg;
     spi_arg->icache_autoload = Cache_Suspend_L2_Cache();
+#else
+    abort();
 #endif
     return ESP_OK;
 }
 
 static IRAM_ATTR esp_err_t end(void *arg)
 {
-    // TODO: [ESP32C5] IDF-8646
 #if CONFIG_IDF_TARGET_ESP32
     Cache_Read_Enable(0);
     Cache_Read_Enable(1);
@@ -95,7 +95,7 @@ static IRAM_ATTR esp_err_t end(void *arg)
     spi_noos_arg_t *spi_arg = arg;
     Cache_Invalidate_ICache_All();
     Cache_Resume_ICache(spi_arg->icache_autoload);
-#elif CONFIG_IDF_TARGET_ESP32C61
+#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C5
     spi_noos_arg_t *spi_arg = arg;
     Cache_Invalidate_All();
     Cache_Resume_Cache(spi_arg->icache_autoload);
@@ -103,6 +103,8 @@ static IRAM_ATTR esp_err_t end(void *arg)
     spi_noos_arg_t *spi_arg = arg;
     Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
     Cache_Resume_L2_Cache(spi_arg->icache_autoload);
+#else
+    abort();
 #endif
     return ESP_OK;
 }