spi_slave: support spi slave hd append mode on chips other than s2

components/driver/include/esp_private/spi_common_internal.h

@@ -13,6 +13,10 @@
 #include "freertos/FreeRTOS.h"
 #include "hal/spi_types.h"
 #include "esp_pm.h"
+#if SOC_GDMA_SUPPORTED
+#include "esp_private/gdma.h"
+#endif
+
 
 #ifdef __cplusplus
 extern "C"
@@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma
  */
 esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id);
 
+#if SOC_GDMA_SUPPORTED
+/**
+ * @brief Get SPI GDMA Handle for GMDA Supported Chip
+ *
+ * @param host_id           SPI host ID
+ * @param gdma_handle       GDMA Handle to Return
+ * @param gdma_direction    GDMA Channel Direction in Enum
+ *                          - GDMA_CHANNEL_DIRECTION_TX
+ *                          - GDMA_CHANNEL_DIRECTION_RX
+ *
+ * @return
+ *        - ESP_OK: On success
+ */
+esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction);
+#endif
+
 /**
  * @brief Connect a SPI peripheral to GPIO pins
  *

components/driver/spi/gpspi/spi_common.c

@@ -7,24 +7,20 @@
 
 #include <string.h>
 #include "sdkconfig.h"
-#include "driver/spi_master.h"
+#include "stdatomic.h"
-#include "soc/spi_periph.h"
 #include "esp_types.h"
 #include "esp_attr.h"
-#include "esp_log.h"
+#include "esp_check.h"
-#include "esp_err.h"
+#include "esp_rom_gpio.h"
-#include "soc/soc.h"
-#include "soc/soc_caps.h"
-#include "soc/soc_pins.h"
-#include "soc/lldesc.h"
-#include "driver/gpio.h"
-#include "esp_private/periph_ctrl.h"
 #include "esp_heap_caps.h"
+#include "soc/lldesc.h"
+#include "soc/spi_periph.h"
+#include "driver/gpio.h"
+#include "driver/spi_master.h"
+#include "esp_private/periph_ctrl.h"
 #include "esp_private/spi_common_internal.h"
-#include "stdatomic.h"
 #include "hal/spi_hal.h"
 #include "hal/gpio_hal.h"
-#include "esp_rom_gpio.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
 #endif
@@ -34,12 +30,7 @@
 
 static const char *SPI_TAG = "spi";
 
-#define SPI_CHECK(a, str, ret_val) do { \
+#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str)
-    if (!(a)) { \
-        ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
-        return (ret_val); \
-    } \
-    } while(0)
 
 #define SPI_CHECK_PIN(pin_num, pin_name, check_output) if (check_output) { \
             SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \
@@ -309,6 +300,25 @@ cleanup:
     return ret;
 }
 
+#if SOC_GDMA_SUPPORTED
+esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction)
+{
+    assert(is_valid_host(host_id));
+    ESP_RETURN_ON_FALSE((gdma_direction == GDMA_CHANNEL_DIRECTION_TX) || \
+                        (gdma_direction == GDMA_CHANNEL_DIRECTION_RX), \
+                        ESP_ERR_INVALID_ARG, SPI_TAG, "GDMA Direction not supported!");
+
+
+    if (gdma_direction == GDMA_CHANNEL_DIRECTION_TX) {
+        *gdma_handle = bus_ctx[host_id]->tx_channel;
+    }
+    if (gdma_direction == GDMA_CHANNEL_DIRECTION_RX) {
+        *gdma_handle = bus_ctx[host_id]->rx_channel;
+    }
+    return ESP_OK;
+}
+#endif // SOC_GDMA_SUPPORTED
+
 //----------------------------------------------------------free dma periph-------------------------------------------------------//
 static esp_err_t dma_chan_free(spi_host_device_t host_id)
 {

components/driver/spi/gpspi/spi_slave_hd.c

@@ -29,6 +29,10 @@ typedef struct {
     uint32_t flags;
     portMUX_TYPE int_spinlock;
     intr_handle_t intr;
+#if SOC_GDMA_SUPPORTED
+    gdma_channel_handle_t gdma_handle_tx;   //varible for storge gdma handle
+    gdma_channel_handle_t gdma_handle_rx;
+#endif
     intr_handle_t intr_dma;
     spi_slave_hd_callback_config_t callback;
     spi_slave_hd_hal_context_t hal;
@@ -41,8 +45,8 @@ typedef struct {
     QueueHandle_t tx_cnting_sem;
     QueueHandle_t rx_cnting_sem;
 
-    spi_slave_hd_data_t* tx_desc;
+    spi_slave_hd_data_t *tx_desc;
-    spi_slave_hd_data_t* rx_desc;
+    spi_slave_hd_data_t *rx_desc;
 #ifdef CONFIG_PM_ENABLE
     esp_pm_lock_handle_t pm_lock;
 #endif
@@ -51,11 +55,12 @@ typedef struct {
 static spi_slave_hd_slot_t *spihost[SOC_SPI_PERIPH_NUM];
 static const char TAG[] = "slave_hd";
 
-static void spi_slave_hd_intr_segment(void *arg);
+#if SOC_GDMA_SUPPORTED
-#if CONFIG_IDF_TARGET_ESP32S2
+static bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
-//Append mode is only supported on ESP32S2 now
+#endif // SOC_GDMA_SUPPORTED
+
 static void spi_slave_hd_intr_append(void *arg);
-#endif
+static void spi_slave_hd_intr_segment(void *arg);
 
 esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config,
                             const spi_slave_hd_slot_config_t *config)
@@ -72,15 +77,11 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
 #elif SOC_GDMA_SUPPORTED
     SPIHD_CHECK(config->dma_chan == SPI_DMA_DISABLED || config->dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG);
 #endif
-#if !CONFIG_IDF_TARGET_ESP32S2
-//Append mode is only supported on ESP32S2 now
-    SPIHD_CHECK(append_mode == 0, "Append mode is only supported on ESP32S2 now", ESP_ERR_INVALID_ARG);
-#endif
 
     spi_chan_claimed = spicommon_periph_claim(host_id, "slave_hd");
     SPIHD_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
 
-    spi_slave_hd_slot_t* host = calloc(1, sizeof(spi_slave_hd_slot_t));
+    spi_slave_hd_slot_t *host = heap_caps_calloc(1, sizeof(spi_slave_hd_slot_t), MALLOC_CAP_INTERNAL);
     if (host == NULL) {
         ret = ESP_ERR_NO_MEM;
         goto cleanup;
@@ -102,7 +103,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
     }
     gpio_set_direction(config->spics_io_num, GPIO_MODE_INPUT);
     spicommon_cs_initialize(host_id, config->spics_io_num, 0,
-            !(bus_config->flags & SPICOMMON_BUSFLAG_NATIVE_PINS));
+                            !(bus_config->flags & SPICOMMON_BUSFLAG_NATIVE_PINS));
     host->append_mode = append_mode;
 
     spi_slave_hd_hal_config_t hal_config = {
@@ -157,10 +158,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
             ret = ESP_ERR_NO_MEM;
             goto cleanup;
         }
-    }
+    } else {
-#if CONFIG_IDF_TARGET_ESP32S2
-//Append mode is only supported on ESP32S2 now
-    else {
         host->tx_cnting_sem = xSemaphoreCreateCounting(config->queue_size, config->queue_size);
         host->rx_cnting_sem = xSemaphoreCreateCounting(config->queue_size, config->queue_size);
         if (!host->tx_cnting_sem || !host->rx_cnting_sem) {
@@ -168,44 +166,51 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
             goto cleanup;
         }
     }
-#endif  //#if CONFIG_IDF_TARGET_ESP32S2
 
     //Alloc intr
     if (!host->append_mode) {
+        //Seg mode
         ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_segment,
-                         (void *)host, &host->intr);
+                                (void *)host, &host->intr);
         if (ret != ESP_OK) {
             goto cleanup;
         }
         ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_segment,
-                            (void *)host, &host->intr_dma);
+                                (void *)host, &host->intr_dma);
         if (ret != ESP_OK) {
             goto cleanup;
         }
-    }
+    } else {
-#if CONFIG_IDF_TARGET_ESP32S2
+        //Append mode
-//Append mode is only supported on ESP32S2 now
+        //On ESP32S2, `cmd7` and `cmd8` interrupts registered as spi rx & tx interrupt are from SPI DMA interrupt source.
-    else {
+        //although the `cmd7` and `cmd8` interrupt on spi are registered independently here
         ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_append,
-                         (void *)host, &host->intr);
+                                (void *)host, &host->intr);
         if (ret != ESP_OK) {
             goto cleanup;
         }
+#if SOC_GDMA_SUPPORTED
+        // config gmda and ISR callback for gdma supported chip
+        spicommon_gdma_get_handle(host_id, &host->gdma_handle_tx, GDMA_CHANNEL_DIRECTION_TX);
+        gdma_tx_event_callbacks_t tx_cbs = {
+            .on_trans_eof = spi_gdma_tx_channel_callback
+        };
+        gdma_register_tx_event_callbacks(host->gdma_handle_tx, &tx_cbs, host);
+#else
         ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_append,
-                            (void *)host, &host->intr_dma);
+                                (void *)host, &host->intr_dma);
         if (ret != ESP_OK) {
             goto cleanup;
         }
+#endif  //#if SOC_GDMA_SUPPORTED
     }
-#endif  //#if CONFIG_IDF_TARGET_ESP32S2
-
     //Init callbacks
-    memcpy((uint8_t*)&host->callback, (uint8_t*)&config->cb_config, sizeof(spi_slave_hd_callback_config_t));
+    memcpy((uint8_t *)&host->callback, (uint8_t *)&config->cb_config, sizeof(spi_slave_hd_callback_config_t));
     spi_event_t event = 0;
-    if (host->callback.cb_buffer_tx!=NULL) event |= SPI_EV_BUF_TX;
+    if (host->callback.cb_buffer_tx != NULL) event |= SPI_EV_BUF_TX;
-    if (host->callback.cb_buffer_rx!=NULL) event |= SPI_EV_BUF_RX;
+    if (host->callback.cb_buffer_rx != NULL) event |= SPI_EV_BUF_RX;
-    if (host->callback.cb_cmd9!=NULL) event |= SPI_EV_CMD9;
+    if (host->callback.cb_cmd9 != NULL) event |= SPI_EV_CMD9;
-    if (host->callback.cb_cmdA!=NULL) event |= SPI_EV_CMDA;
+    if (host->callback.cb_cmdA != NULL) event |= SPI_EV_CMDA;
     spi_slave_hd_hal_enable_event_intr(&host->hal, event);
 
     return ESP_OK;
@@ -249,21 +254,21 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id)
     return ESP_OK;
 }
 
-static void tx_invoke(spi_slave_hd_slot_t* host)
+static void tx_invoke(spi_slave_hd_slot_t *host)
 {
     portENTER_CRITICAL(&host->int_spinlock);
     spi_slave_hd_hal_invoke_event_intr(&host->hal, SPI_EV_SEND);
     portEXIT_CRITICAL(&host->int_spinlock);
 }
 
-static void rx_invoke(spi_slave_hd_slot_t* host)
+static void rx_invoke(spi_slave_hd_slot_t *host)
 {
     portENTER_CRITICAL(&host->int_spinlock);
     spi_slave_hd_hal_invoke_event_intr(&host->hal, SPI_EV_RECV);
     portEXIT_CRITICAL(&host->int_spinlock);
 }
 
-static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t* host, spi_event_t ev, slave_cb_t cb)
+static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t *host, spi_event_t ev, slave_cb_t cb)
 {
     BaseType_t cb_awoken = pdFALSE;
     if (spi_slave_hd_hal_check_clear_event(&host->hal, ev) && cb) {
@@ -275,7 +280,7 @@ static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t
 
 static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg)
 {
-    spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
+    spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg;
     spi_slave_hd_callback_config_t *callback = &host->callback;
     spi_slave_hd_hal_context_t *hal = &host->hal;
     BaseType_t awoken = pdFALSE;
@@ -380,12 +385,10 @@ static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg)
     }
     portEXIT_CRITICAL_ISR(&host->int_spinlock);
 
-    if (awoken==pdTRUE) portYIELD_FROM_ISR();
+    if (awoken == pdTRUE) portYIELD_FROM_ISR();
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2
+static IRAM_ATTR void spi_slave_hd_append_tx_isr(void *arg)
-//Append mode is only supported on ESP32S2 now
-static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
 {
     spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
     spi_slave_hd_callback_config_t *callback = &host->callback;
@@ -393,82 +396,113 @@ static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
     BaseType_t awoken = pdFALSE;
     BaseType_t ret __attribute__((unused));
 
-    bool tx_done = false;
+    spi_slave_hd_data_t *trans_desc;
-    bool rx_done = false;
+    while (1) {
-    portENTER_CRITICAL_ISR(&host->int_spinlock);
+        bool trans_finish = false;
-    if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_SEND)) {
+        trans_finish = spi_slave_hd_hal_get_tx_finished_trans(hal, (void **)&trans_desc);
-        tx_done = true;
+        if (!trans_finish) {
+            break;
+        }
+
+        bool ret_queue = true;
+        if (callback->cb_sent) {
+            spi_slave_hd_event_t ev = {
+                .event = SPI_EV_SEND,
+                .trans = trans_desc,
+            };
+            BaseType_t cb_awoken = pdFALSE;
+            ret_queue = callback->cb_sent(callback->arg, &ev, &cb_awoken);
+            awoken |= cb_awoken;
+        }
+
+        if (ret_queue) {
+            ret = xQueueSendFromISR(host->tx_ret_queue, &trans_desc, &awoken);
+            assert(ret == pdTRUE);
+
+            ret = xSemaphoreGiveFromISR(host->tx_cnting_sem, &awoken);
+            assert(ret == pdTRUE);
+        }
     }
+    if (awoken==pdTRUE) portYIELD_FROM_ISR();
+}
+
+static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg)
+{
+    spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
+    spi_slave_hd_callback_config_t *callback = &host->callback;
+    spi_slave_hd_hal_context_t *hal = &host->hal;
+    BaseType_t awoken = pdFALSE;
+    BaseType_t ret __attribute__((unused));
+
+    spi_slave_hd_data_t *trans_desc;
+    size_t trans_len;
+    while (1) {
+        bool trans_finish = false;
+        trans_finish = spi_slave_hd_hal_get_rx_finished_trans(hal, (void **)&trans_desc, &trans_len);
+        if (!trans_finish) {
+            break;
+        }
+        trans_desc->trans_len = trans_len;
+
+        bool ret_queue = true;
+        if (callback->cb_recv) {
+            spi_slave_hd_event_t ev = {
+                .event = SPI_EV_RECV,
+                .trans = trans_desc,
+            };
+            BaseType_t cb_awoken = pdFALSE;
+            ret_queue = callback->cb_recv(callback->arg, &ev, &cb_awoken);
+            awoken |= cb_awoken;
+        }
+
+        if (ret_queue) {
+            ret = xQueueSendFromISR(host->rx_ret_queue, &trans_desc, &awoken);
+            assert(ret == pdTRUE);
+
+            ret = xSemaphoreGiveFromISR(host->rx_cnting_sem, &awoken);
+            assert(ret == pdTRUE);
+        }
+    }
+    if (awoken==pdTRUE) portYIELD_FROM_ISR();
+}
+
+#if SOC_GDMA_SUPPORTED
+// 'spi_gdma_tx_channel_callback' used as spi tx interrupt of append mode on gdma supported target
+static IRAM_ATTR bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
+{
+    assert(event_data);
+    spi_slave_hd_append_tx_isr(user_data);
+    return true;
+}
+#endif // SOC_GDMA_SUPPORTED
+
+// SPI slave hd append isr entrance
+static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
+{
+    spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg;
+    spi_slave_hd_hal_context_t *hal = &host->hal;
+    bool rx_done = false;
+    bool tx_done = false;
+
+    // Append Mode
+    portENTER_CRITICAL_ISR(&host->int_spinlock);
     if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_RECV)) {
         rx_done = true;
     }
+    if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_SEND)) {
+        // NOTE: on gdma supported chips, this flag should NOT checked out, handle entrance is only `spi_gdma_tx_channel_callback`,
+        // otherwise, here should be target limited.
+        tx_done = true;
+    }
     portEXIT_CRITICAL_ISR(&host->int_spinlock);
 
-    if (tx_done) {
-        spi_slave_hd_data_t *trans_desc;
-        while (1) {
-            bool trans_finish = false;
-            trans_finish = spi_slave_hd_hal_get_tx_finished_trans(hal, (void **)&trans_desc);
-            if (!trans_finish) {
-                break;
-            }
-
-            bool ret_queue = true;
-            if (callback->cb_sent) {
-                spi_slave_hd_event_t ev = {
-                    .event = SPI_EV_SEND,
-                    .trans = trans_desc,
-                };
-                BaseType_t cb_awoken = pdFALSE;
-                ret_queue = callback->cb_sent(callback->arg, &ev, &cb_awoken);
-                awoken |= cb_awoken;
-            }
-
-            if (ret_queue) {
-                ret = xQueueSendFromISR(host->tx_ret_queue, &trans_desc, &awoken);
-                assert(ret == pdTRUE);
-
-                ret = xSemaphoreGiveFromISR(host->tx_cnting_sem, &awoken);
-                assert(ret == pdTRUE);
-            }
-        }
-    }
-
     if (rx_done) {
-        spi_slave_hd_data_t *trans_desc;
+        spi_slave_hd_append_rx_isr(arg);
-        size_t trans_len;
+    }
-        while (1) {
+    if (tx_done) {
-            bool trans_finish = false;
+        spi_slave_hd_append_tx_isr(arg);
-            trans_finish = spi_slave_hd_hal_get_rx_finished_trans(hal, (void **)&trans_desc, &trans_len);
-            if (!trans_finish) {
-                break;
-            }
-            trans_desc->trans_len = trans_len;
-
-            bool ret_queue = true;
-            if (callback->cb_recv) {
-                spi_slave_hd_event_t ev = {
-                    .event = SPI_EV_RECV,
-                    .trans = trans_desc,
-                };
-                BaseType_t cb_awoken = pdFALSE;
-                ret_queue = callback->cb_recv(callback->arg, &ev, &cb_awoken);
-                awoken |= cb_awoken;
-            }
-
-            if (ret_queue) {
-                ret = xQueueSendFromISR(host->rx_ret_queue, &trans_desc, &awoken);
-                assert(ret == pdTRUE);
-
-                ret = xSemaphoreGiveFromISR(host->rx_cnting_sem, &awoken);
-                assert(ret == pdTRUE);
-            }
-        }
     }
-
-    if (awoken==pdTRUE) portYIELD_FROM_ISR();
 }
-#endif //#if CONFIG_IDF_TARGET_ESP32S2
 
 static esp_err_t get_ret_queue_result(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
 {
@@ -490,9 +524,9 @@ static esp_err_t get_ret_queue_result(spi_host_device_t host_id, spi_slave_chan_
 }
 
 //---------------------------------------------------------Segment Mode Transaction APIs-----------------------------------------------------------//
-esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t* trans, TickType_t timeout)
+esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t *trans, TickType_t timeout)
 {
-    spi_slave_hd_slot_t* host = spihost[host_id];
+    spi_slave_hd_slot_t *host = spihost[host_id];
 
     SPIHD_CHECK(host->append_mode == 0, "This API should be used for SPI Slave HD Segment Mode", ESP_ERR_INVALID_STATE);
     SPIHD_CHECK(esp_ptr_dma_capable(trans->data), "The buffer should be DMA capable.", ESP_ERR_INVALID_ARG);
@@ -515,10 +549,10 @@ esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t c
     return ESP_OK;
 }
 
-esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t** out_trans, TickType_t timeout)
+esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
 {
     esp_err_t ret;
-    spi_slave_hd_slot_t* host = spihost[host_id];
+    spi_slave_hd_slot_t *host = spihost[host_id];
 
     SPIHD_CHECK(host->append_mode == 0, "This API should be used for SPI Slave HD Segment Mode", ESP_ERR_INVALID_STATE);
     SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG);
@@ -537,8 +571,6 @@ void spi_slave_hd_write_buffer(spi_host_device_t host_id, int addr, uint8_t *dat
     spi_slave_hd_hal_write_buffer(&spihost[host_id]->hal, addr, data, len);
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2
-//Append mode is only supported on ESP32S2 now
 //---------------------------------------------------------Append Mode Transaction APIs-----------------------------------------------------------//
 esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t *trans, TickType_t timeout)
 {
@@ -575,7 +607,7 @@ esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t
 esp_err_t spi_slave_hd_get_append_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
 {
     esp_err_t ret;
-    spi_slave_hd_slot_t* host = spihost[host_id];
+    spi_slave_hd_slot_t *host = spihost[host_id];
 
     SPIHD_CHECK(host->append_mode == 1, "This API should be used for SPI Slave HD Append Mode", ESP_ERR_INVALID_STATE);
     SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG);
@@ -583,4 +615,3 @@ esp_err_t spi_slave_hd_get_append_trans_res(spi_host_device_t host_id, spi_slave
 
     return ret;
 }
-#endif //#if CONFIG_IDF_TARGET_ESP32S2

components/hal/include/hal/spi_slave_hd_hal.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 /*******************************************************************************
  * NOTICE
@@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal);
  */
 int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal);
 
-#if CONFIG_IDF_TARGET_ESP32S2
+
-//Append mode is only supported on ESP32S2 now
 ////////////////////////////////////////////////////////////////////////////////
 // Append Mode
 ////////////////////////////////////////////////////////////////////////////////
@@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
  *        - ESP_ERR_INVALID_STATE: Function called in invalid state.
  */
 esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg);
-#endif  //#if CONFIG_IDF_TARGET_ESP32S2

components/hal/spi_slave_hd_hal.c

@@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
+/*
-//
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
-// Licensed under the Apache License, Version 2.0 (the "License");
+ *
-// you may not use this file except in compliance with the License.
+ * SPDX-License-Identifier: Apache-2.0
-// You may obtain a copy of the License at
+ */
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 
 // The HAL layer for SPI Slave HD
 
@@ -29,7 +21,8 @@
 #if SOC_GDMA_SUPPORTED
 #include "soc/gdma_struct.h"
 #include "hal/gdma_ll.h"
-
+#define spi_dma_ll_tx_restart(dev, chan)                           gdma_ll_tx_restart(&GDMA, chan)
+#define spi_dma_ll_rx_restart(dev, chan)                           gdma_ll_rx_restart(&GDMA, chan)
 #define spi_dma_ll_rx_reset(dev, chan)                             gdma_ll_rx_reset_channel(&GDMA, chan)
 #define spi_dma_ll_tx_reset(dev, chan)                             gdma_ll_tx_reset_channel(&GDMA, chan)
 #define spi_dma_ll_rx_enable_burst_data(dev, chan, enable)         gdma_ll_rx_enable_data_burst(&GDMA, chan, enable)
@@ -62,7 +55,7 @@ static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t
 
 void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
 {
-    spi_dev_t* hw = SPI_LL_GET_HW(hal_config->host_id);
+    spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id);
     hal->dev = hw;
     hal->dma_in = hal_config->dma_in;
     hal->dma_out = hal_config->dma_out;
@@ -107,13 +100,14 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h
             //Workaround if the previous interrupts are not writable
             spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE);
         }
-    }
+    } else {
-#if CONFIG_IDF_TARGET_ESP32S2
+#if SOC_GDMA_SUPPORTED
-    //Append mode is only supported on ESP32S2 now
+        spi_ll_enable_intr(hw, SPI_LL_INTR_CMD7);
-    else {
+#else
+        spi_ll_clear_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7);
         spi_ll_enable_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7);
+#endif //SOC_GDMA_SUPPORTED
     }
-#endif
 
     spi_ll_slave_hd_set_len_cond(hw,    SPI_LL_TRANS_LEN_COND_WRBUF |
                                         SPI_LL_TRANS_LEN_COND_WRDMA |
@@ -172,7 +166,6 @@ static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t
 {
     spi_ll_intr_t intr = 0;
 #if CONFIG_IDF_TARGET_ESP32S2
-//Append mode is only supported on ESP32S2 now
     if ((ev & SPI_EV_SEND) && hal->append_mode) intr |= SPI_LL_INTR_OUT_EOF;
 #endif
     if ((ev & SPI_EV_SEND) && !hal->append_mode) intr |= SPI_LL_INTR_CMD8;
@@ -221,13 +214,13 @@ bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t *hal, spi_e
     return false;
 }
 
-void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
+void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
 {
     spi_ll_intr_t intr = get_event_intr(hal, ev);
     spi_ll_enable_intr(hal->dev, intr);
 }
 
-void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
+void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
 {
     spi_ll_intr_t intr = get_event_intr(hal, ev);
 
@@ -262,7 +255,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
 
 int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal)
 {
-    lldesc_t* desc = &hal->dmadesc_rx->desc;
+    lldesc_t *desc = &hal->dmadesc_rx->desc;
     return lldesc_get_received_len(desc, NULL);
 }
 
@@ -293,8 +286,6 @@ bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, voi
     return true;
 }
 
-#if CONFIG_IDF_TARGET_ESP32S2
-//Append mode is only supported on ESP32S2 now
 static void spi_slave_hd_hal_link_append_desc(spi_slave_hd_hal_desc_append_t *dmadesc, const void *data, int len, bool isrx, void *arg)
 {
     HAL_ASSERT(len <= LLDESC_MAX_NUM_PER_DESC);     //TODO: Add support for transaction with length larger than 4092, IDF-2660
@@ -342,7 +333,6 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
         hal->tx_dma_started = true;
         //start a link
         hal->tx_dma_tail = hal->tx_cur_desc;
-        spi_ll_clear_intr(hal->dev, SPI_LL_INTR_OUT_EOF);
         spi_ll_dma_tx_fifo_reset(hal->dma_out);
         spi_ll_outfifo_empty_clr(hal->dev);
         spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan);
@@ -383,7 +373,6 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
         hal->rx_dma_started = true;
         //start a link
         hal->rx_dma_tail = hal->rx_cur_desc;
-        spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
         spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan);
         spi_ll_dma_rx_fifo_reset(hal->dma_in);
         spi_ll_infifo_full_clr(hal->dev);
@@ -407,4 +396,3 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
 
     return ESP_OK;
 }
-#endif  //#if CONFIG_IDF_TARGET_ESP32S2

examples/peripherals/spi_slave_hd/append_mode/master/main/app_main.c

@@ -163,6 +163,7 @@ void app_main(void)
 
     ESP_ERROR_CHECK(receiver(essl));
     ESP_ERROR_CHECK(sender(essl));
+    ESP_LOGI("Append", "Example done.");
 
     ESP_ERROR_CHECK(essl_spi_deinit_dev(essl));
     ESP_ERROR_CHECK(spi_bus_remove_device(spi));

tools/ci/check_copyright_ignore.txt

@@ -666,7 +666,6 @@ components/hal/include/hal/rtc_io_types.h
 components/hal/include/hal/sdio_slave_ll.h
 components/hal/include/hal/sha_hal.h
 components/hal/include/hal/spi_flash_encrypt_hal.h
-components/hal/include/hal/spi_slave_hd_hal.h
 components/hal/include/hal/uhci_types.h
 components/hal/include/hal/usb_hal.h
 components/hal/include/hal/usb_types_private.h
@@ -676,7 +675,6 @@ components/hal/spi_flash_encrypt_hal_iram.c
 components/hal/spi_flash_hal_gpspi.c
 components/hal/spi_slave_hal.c
 components/hal/spi_slave_hal_iram.c
-components/hal/spi_slave_hd_hal.c
 components/hal/test/test_mpu.c
 components/hal/touch_sensor_hal.c
 components/hal/uart_hal_iram.c