mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-19 14:26:01 -04:00
spi_slave: support spi slave hd append mode on chips other than s2
This commit is contained in:
parent
bd87e61e6f
commit
66ca403bc6
@ -13,6 +13,10 @@
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#include "freertos/FreeRTOS.h"
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#include "hal/spi_types.h"
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#include "esp_pm.h"
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#if SOC_GDMA_SUPPORTED
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#include "esp_private/gdma.h"
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#endif
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#ifdef __cplusplus
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extern "C"
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@ -130,6 +134,22 @@ esp_err_t spicommon_dma_chan_alloc(spi_host_device_t host_id, spi_dma_chan_t dma
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*/
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esp_err_t spicommon_dma_chan_free(spi_host_device_t host_id);
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#if SOC_GDMA_SUPPORTED
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/**
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* @brief Get SPI GDMA Handle for GMDA Supported Chip
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*
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* @param host_id SPI host ID
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* @param gdma_handle GDMA Handle to Return
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* @param gdma_direction GDMA Channel Direction in Enum
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* - GDMA_CHANNEL_DIRECTION_TX
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* - GDMA_CHANNEL_DIRECTION_RX
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*
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* @return
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* - ESP_OK: On success
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*/
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esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction);
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#endif
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/**
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* @brief Connect a SPI peripheral to GPIO pins
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*
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@ -7,24 +7,20 @@
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#include <string.h>
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#include "sdkconfig.h"
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#include "driver/spi_master.h"
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#include "soc/spi_periph.h"
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#include "stdatomic.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "soc/soc_pins.h"
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#include "soc/lldesc.h"
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#include "driver/gpio.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_check.h"
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#include "esp_rom_gpio.h"
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#include "esp_heap_caps.h"
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#include "soc/lldesc.h"
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#include "soc/spi_periph.h"
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#include "driver/gpio.h"
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#include "driver/spi_master.h"
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#include "esp_private/periph_ctrl.h"
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#include "esp_private/spi_common_internal.h"
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#include "stdatomic.h"
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#include "hal/spi_hal.h"
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#include "hal/gpio_hal.h"
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#include "esp_rom_gpio.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "soc/dport_reg.h"
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#endif
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@ -34,12 +30,7 @@
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static const char *SPI_TAG = "spi";
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#define SPI_CHECK(a, str, ret_val) do { \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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} \
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} while(0)
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#define SPI_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, SPI_TAG, str)
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#define SPI_CHECK_PIN(pin_num, pin_name, check_output) if (check_output) { \
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SPI_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(pin_num), pin_name" not valid", ESP_ERR_INVALID_ARG); \
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@ -309,6 +300,25 @@ cleanup:
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return ret;
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}
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#if SOC_GDMA_SUPPORTED
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esp_err_t spicommon_gdma_get_handle(spi_host_device_t host_id, gdma_channel_handle_t *gdma_handle, gdma_channel_direction_t gdma_direction)
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{
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assert(is_valid_host(host_id));
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ESP_RETURN_ON_FALSE((gdma_direction == GDMA_CHANNEL_DIRECTION_TX) || \
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(gdma_direction == GDMA_CHANNEL_DIRECTION_RX), \
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ESP_ERR_INVALID_ARG, SPI_TAG, "GDMA Direction not supported!");
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if (gdma_direction == GDMA_CHANNEL_DIRECTION_TX) {
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*gdma_handle = bus_ctx[host_id]->tx_channel;
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}
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if (gdma_direction == GDMA_CHANNEL_DIRECTION_RX) {
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*gdma_handle = bus_ctx[host_id]->rx_channel;
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}
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return ESP_OK;
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}
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#endif // SOC_GDMA_SUPPORTED
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//----------------------------------------------------------free dma periph-------------------------------------------------------//
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static esp_err_t dma_chan_free(spi_host_device_t host_id)
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{
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@ -29,6 +29,10 @@ typedef struct {
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uint32_t flags;
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portMUX_TYPE int_spinlock;
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intr_handle_t intr;
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#if SOC_GDMA_SUPPORTED
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gdma_channel_handle_t gdma_handle_tx; //varible for storge gdma handle
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gdma_channel_handle_t gdma_handle_rx;
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#endif
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intr_handle_t intr_dma;
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spi_slave_hd_callback_config_t callback;
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spi_slave_hd_hal_context_t hal;
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@ -41,8 +45,8 @@ typedef struct {
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QueueHandle_t tx_cnting_sem;
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QueueHandle_t rx_cnting_sem;
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spi_slave_hd_data_t* tx_desc;
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spi_slave_hd_data_t* rx_desc;
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spi_slave_hd_data_t *tx_desc;
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spi_slave_hd_data_t *rx_desc;
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock;
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#endif
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@ -51,11 +55,12 @@ typedef struct {
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static spi_slave_hd_slot_t *spihost[SOC_SPI_PERIPH_NUM];
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static const char TAG[] = "slave_hd";
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static void spi_slave_hd_intr_segment(void *arg);
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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#if SOC_GDMA_SUPPORTED
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static bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
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#endif // SOC_GDMA_SUPPORTED
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static void spi_slave_hd_intr_append(void *arg);
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#endif
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static void spi_slave_hd_intr_segment(void *arg);
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esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *bus_config,
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const spi_slave_hd_slot_config_t *config)
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@ -72,15 +77,11 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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#elif SOC_GDMA_SUPPORTED
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SPIHD_CHECK(config->dma_chan == SPI_DMA_DISABLED || config->dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG);
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#endif
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#if !CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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SPIHD_CHECK(append_mode == 0, "Append mode is only supported on ESP32S2 now", ESP_ERR_INVALID_ARG);
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#endif
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spi_chan_claimed = spicommon_periph_claim(host_id, "slave_hd");
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SPIHD_CHECK(spi_chan_claimed, "host already in use", ESP_ERR_INVALID_STATE);
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spi_slave_hd_slot_t* host = calloc(1, sizeof(spi_slave_hd_slot_t));
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spi_slave_hd_slot_t *host = heap_caps_calloc(1, sizeof(spi_slave_hd_slot_t), MALLOC_CAP_INTERNAL);
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if (host == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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@ -102,7 +103,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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}
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gpio_set_direction(config->spics_io_num, GPIO_MODE_INPUT);
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spicommon_cs_initialize(host_id, config->spics_io_num, 0,
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!(bus_config->flags & SPICOMMON_BUSFLAG_NATIVE_PINS));
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!(bus_config->flags & SPICOMMON_BUSFLAG_NATIVE_PINS));
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host->append_mode = append_mode;
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spi_slave_hd_hal_config_t hal_config = {
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@ -157,10 +158,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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else {
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} else {
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host->tx_cnting_sem = xSemaphoreCreateCounting(config->queue_size, config->queue_size);
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host->rx_cnting_sem = xSemaphoreCreateCounting(config->queue_size, config->queue_size);
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if (!host->tx_cnting_sem || !host->rx_cnting_sem) {
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@ -168,44 +166,51 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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goto cleanup;
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}
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}
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#endif //#if CONFIG_IDF_TARGET_ESP32S2
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//Alloc intr
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if (!host->append_mode) {
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//Seg mode
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ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_segment,
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(void *)host, &host->intr);
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(void *)host, &host->intr);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_segment,
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(void *)host, &host->intr_dma);
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(void *)host, &host->intr_dma);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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else {
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} else {
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//Append mode
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//On ESP32S2, `cmd7` and `cmd8` interrupts registered as spi rx & tx interrupt are from SPI DMA interrupt source.
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//although the `cmd7` and `cmd8` interrupt on spi are registered independently here
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ret = esp_intr_alloc(spicommon_irqsource_for_host(host_id), 0, spi_slave_hd_intr_append,
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(void *)host, &host->intr);
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(void *)host, &host->intr);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#if SOC_GDMA_SUPPORTED
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// config gmda and ISR callback for gdma supported chip
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spicommon_gdma_get_handle(host_id, &host->gdma_handle_tx, GDMA_CHANNEL_DIRECTION_TX);
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gdma_tx_event_callbacks_t tx_cbs = {
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.on_trans_eof = spi_gdma_tx_channel_callback
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};
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gdma_register_tx_event_callbacks(host->gdma_handle_tx, &tx_cbs, host);
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#else
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ret = esp_intr_alloc(spicommon_irqdma_source_for_host(host_id), 0, spi_slave_hd_intr_append,
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(void *)host, &host->intr_dma);
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(void *)host, &host->intr_dma);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#endif //#if SOC_GDMA_SUPPORTED
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}
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#endif //#if CONFIG_IDF_TARGET_ESP32S2
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//Init callbacks
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memcpy((uint8_t*)&host->callback, (uint8_t*)&config->cb_config, sizeof(spi_slave_hd_callback_config_t));
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memcpy((uint8_t *)&host->callback, (uint8_t *)&config->cb_config, sizeof(spi_slave_hd_callback_config_t));
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spi_event_t event = 0;
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if (host->callback.cb_buffer_tx!=NULL) event |= SPI_EV_BUF_TX;
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if (host->callback.cb_buffer_rx!=NULL) event |= SPI_EV_BUF_RX;
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if (host->callback.cb_cmd9!=NULL) event |= SPI_EV_CMD9;
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if (host->callback.cb_cmdA!=NULL) event |= SPI_EV_CMDA;
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if (host->callback.cb_buffer_tx != NULL) event |= SPI_EV_BUF_TX;
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if (host->callback.cb_buffer_rx != NULL) event |= SPI_EV_BUF_RX;
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if (host->callback.cb_cmd9 != NULL) event |= SPI_EV_CMD9;
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if (host->callback.cb_cmdA != NULL) event |= SPI_EV_CMDA;
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spi_slave_hd_hal_enable_event_intr(&host->hal, event);
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return ESP_OK;
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@ -249,21 +254,21 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id)
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return ESP_OK;
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}
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static void tx_invoke(spi_slave_hd_slot_t* host)
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static void tx_invoke(spi_slave_hd_slot_t *host)
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{
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portENTER_CRITICAL(&host->int_spinlock);
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spi_slave_hd_hal_invoke_event_intr(&host->hal, SPI_EV_SEND);
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portEXIT_CRITICAL(&host->int_spinlock);
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}
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static void rx_invoke(spi_slave_hd_slot_t* host)
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static void rx_invoke(spi_slave_hd_slot_t *host)
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{
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portENTER_CRITICAL(&host->int_spinlock);
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spi_slave_hd_hal_invoke_event_intr(&host->hal, SPI_EV_RECV);
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portEXIT_CRITICAL(&host->int_spinlock);
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}
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static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t* host, spi_event_t ev, slave_cb_t cb)
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static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t *host, spi_event_t ev, slave_cb_t cb)
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{
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BaseType_t cb_awoken = pdFALSE;
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if (spi_slave_hd_hal_check_clear_event(&host->hal, ev) && cb) {
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@ -275,7 +280,7 @@ static inline IRAM_ATTR BaseType_t intr_check_clear_callback(spi_slave_hd_slot_t
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static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg)
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{
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spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
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spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg;
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spi_slave_hd_callback_config_t *callback = &host->callback;
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spi_slave_hd_hal_context_t *hal = &host->hal;
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BaseType_t awoken = pdFALSE;
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@ -380,12 +385,10 @@ static IRAM_ATTR void spi_slave_hd_intr_segment(void *arg)
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}
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portEXIT_CRITICAL_ISR(&host->int_spinlock);
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if (awoken==pdTRUE) portYIELD_FROM_ISR();
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if (awoken == pdTRUE) portYIELD_FROM_ISR();
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//Append mode is only supported on ESP32S2 now
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static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
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static IRAM_ATTR void spi_slave_hd_append_tx_isr(void *arg)
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{
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spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
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spi_slave_hd_callback_config_t *callback = &host->callback;
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@ -393,82 +396,113 @@ static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
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BaseType_t awoken = pdFALSE;
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BaseType_t ret __attribute__((unused));
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bool tx_done = false;
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bool rx_done = false;
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portENTER_CRITICAL_ISR(&host->int_spinlock);
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if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_SEND)) {
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tx_done = true;
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spi_slave_hd_data_t *trans_desc;
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while (1) {
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bool trans_finish = false;
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trans_finish = spi_slave_hd_hal_get_tx_finished_trans(hal, (void **)&trans_desc);
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if (!trans_finish) {
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break;
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}
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bool ret_queue = true;
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if (callback->cb_sent) {
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spi_slave_hd_event_t ev = {
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.event = SPI_EV_SEND,
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.trans = trans_desc,
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};
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BaseType_t cb_awoken = pdFALSE;
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ret_queue = callback->cb_sent(callback->arg, &ev, &cb_awoken);
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awoken |= cb_awoken;
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}
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if (ret_queue) {
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ret = xQueueSendFromISR(host->tx_ret_queue, &trans_desc, &awoken);
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assert(ret == pdTRUE);
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ret = xSemaphoreGiveFromISR(host->tx_cnting_sem, &awoken);
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assert(ret == pdTRUE);
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}
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}
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if (awoken==pdTRUE) portYIELD_FROM_ISR();
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}
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static IRAM_ATTR void spi_slave_hd_append_rx_isr(void *arg)
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{
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spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t*)arg;
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spi_slave_hd_callback_config_t *callback = &host->callback;
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spi_slave_hd_hal_context_t *hal = &host->hal;
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BaseType_t awoken = pdFALSE;
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BaseType_t ret __attribute__((unused));
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spi_slave_hd_data_t *trans_desc;
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size_t trans_len;
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while (1) {
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bool trans_finish = false;
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trans_finish = spi_slave_hd_hal_get_rx_finished_trans(hal, (void **)&trans_desc, &trans_len);
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if (!trans_finish) {
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break;
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}
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trans_desc->trans_len = trans_len;
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bool ret_queue = true;
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if (callback->cb_recv) {
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spi_slave_hd_event_t ev = {
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.event = SPI_EV_RECV,
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.trans = trans_desc,
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};
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BaseType_t cb_awoken = pdFALSE;
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ret_queue = callback->cb_recv(callback->arg, &ev, &cb_awoken);
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awoken |= cb_awoken;
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}
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if (ret_queue) {
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ret = xQueueSendFromISR(host->rx_ret_queue, &trans_desc, &awoken);
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assert(ret == pdTRUE);
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ret = xSemaphoreGiveFromISR(host->rx_cnting_sem, &awoken);
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assert(ret == pdTRUE);
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}
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}
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if (awoken==pdTRUE) portYIELD_FROM_ISR();
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}
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#if SOC_GDMA_SUPPORTED
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// 'spi_gdma_tx_channel_callback' used as spi tx interrupt of append mode on gdma supported target
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static IRAM_ATTR bool spi_gdma_tx_channel_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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||||
assert(event_data);
|
||||
spi_slave_hd_append_tx_isr(user_data);
|
||||
return true;
|
||||
}
|
||||
#endif // SOC_GDMA_SUPPORTED
|
||||
|
||||
// SPI slave hd append isr entrance
|
||||
static IRAM_ATTR void spi_slave_hd_intr_append(void *arg)
|
||||
{
|
||||
spi_slave_hd_slot_t *host = (spi_slave_hd_slot_t *)arg;
|
||||
spi_slave_hd_hal_context_t *hal = &host->hal;
|
||||
bool rx_done = false;
|
||||
bool tx_done = false;
|
||||
|
||||
// Append Mode
|
||||
portENTER_CRITICAL_ISR(&host->int_spinlock);
|
||||
if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_RECV)) {
|
||||
rx_done = true;
|
||||
}
|
||||
if (spi_slave_hd_hal_check_clear_event(hal, SPI_EV_SEND)) {
|
||||
// NOTE: on gdma supported chips, this flag should NOT checked out, handle entrance is only `spi_gdma_tx_channel_callback`,
|
||||
// otherwise, here should be target limited.
|
||||
tx_done = true;
|
||||
}
|
||||
portEXIT_CRITICAL_ISR(&host->int_spinlock);
|
||||
|
||||
if (tx_done) {
|
||||
spi_slave_hd_data_t *trans_desc;
|
||||
while (1) {
|
||||
bool trans_finish = false;
|
||||
trans_finish = spi_slave_hd_hal_get_tx_finished_trans(hal, (void **)&trans_desc);
|
||||
if (!trans_finish) {
|
||||
break;
|
||||
}
|
||||
|
||||
bool ret_queue = true;
|
||||
if (callback->cb_sent) {
|
||||
spi_slave_hd_event_t ev = {
|
||||
.event = SPI_EV_SEND,
|
||||
.trans = trans_desc,
|
||||
};
|
||||
BaseType_t cb_awoken = pdFALSE;
|
||||
ret_queue = callback->cb_sent(callback->arg, &ev, &cb_awoken);
|
||||
awoken |= cb_awoken;
|
||||
}
|
||||
|
||||
if (ret_queue) {
|
||||
ret = xQueueSendFromISR(host->tx_ret_queue, &trans_desc, &awoken);
|
||||
assert(ret == pdTRUE);
|
||||
|
||||
ret = xSemaphoreGiveFromISR(host->tx_cnting_sem, &awoken);
|
||||
assert(ret == pdTRUE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (rx_done) {
|
||||
spi_slave_hd_data_t *trans_desc;
|
||||
size_t trans_len;
|
||||
while (1) {
|
||||
bool trans_finish = false;
|
||||
trans_finish = spi_slave_hd_hal_get_rx_finished_trans(hal, (void **)&trans_desc, &trans_len);
|
||||
if (!trans_finish) {
|
||||
break;
|
||||
}
|
||||
trans_desc->trans_len = trans_len;
|
||||
|
||||
bool ret_queue = true;
|
||||
if (callback->cb_recv) {
|
||||
spi_slave_hd_event_t ev = {
|
||||
.event = SPI_EV_RECV,
|
||||
.trans = trans_desc,
|
||||
};
|
||||
BaseType_t cb_awoken = pdFALSE;
|
||||
ret_queue = callback->cb_recv(callback->arg, &ev, &cb_awoken);
|
||||
awoken |= cb_awoken;
|
||||
}
|
||||
|
||||
if (ret_queue) {
|
||||
ret = xQueueSendFromISR(host->rx_ret_queue, &trans_desc, &awoken);
|
||||
assert(ret == pdTRUE);
|
||||
|
||||
ret = xSemaphoreGiveFromISR(host->rx_cnting_sem, &awoken);
|
||||
assert(ret == pdTRUE);
|
||||
}
|
||||
}
|
||||
spi_slave_hd_append_rx_isr(arg);
|
||||
}
|
||||
if (tx_done) {
|
||||
spi_slave_hd_append_tx_isr(arg);
|
||||
}
|
||||
|
||||
if (awoken==pdTRUE) portYIELD_FROM_ISR();
|
||||
}
|
||||
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
||||
|
||||
static esp_err_t get_ret_queue_result(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
|
||||
{
|
||||
@ -490,9 +524,9 @@ static esp_err_t get_ret_queue_result(spi_host_device_t host_id, spi_slave_chan_
|
||||
}
|
||||
|
||||
//---------------------------------------------------------Segment Mode Transaction APIs-----------------------------------------------------------//
|
||||
esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t* trans, TickType_t timeout)
|
||||
esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t *trans, TickType_t timeout)
|
||||
{
|
||||
spi_slave_hd_slot_t* host = spihost[host_id];
|
||||
spi_slave_hd_slot_t *host = spihost[host_id];
|
||||
|
||||
SPIHD_CHECK(host->append_mode == 0, "This API should be used for SPI Slave HD Segment Mode", ESP_ERR_INVALID_STATE);
|
||||
SPIHD_CHECK(esp_ptr_dma_capable(trans->data), "The buffer should be DMA capable.", ESP_ERR_INVALID_ARG);
|
||||
@ -515,10 +549,10 @@ esp_err_t spi_slave_hd_queue_trans(spi_host_device_t host_id, spi_slave_chan_t c
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t** out_trans, TickType_t timeout)
|
||||
esp_err_t spi_slave_hd_get_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
|
||||
{
|
||||
esp_err_t ret;
|
||||
spi_slave_hd_slot_t* host = spihost[host_id];
|
||||
spi_slave_hd_slot_t *host = spihost[host_id];
|
||||
|
||||
SPIHD_CHECK(host->append_mode == 0, "This API should be used for SPI Slave HD Segment Mode", ESP_ERR_INVALID_STATE);
|
||||
SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG);
|
||||
@ -537,8 +571,6 @@ void spi_slave_hd_write_buffer(spi_host_device_t host_id, int addr, uint8_t *dat
|
||||
spi_slave_hd_hal_write_buffer(&spihost[host_id]->hal, addr, data, len);
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
//---------------------------------------------------------Append Mode Transaction APIs-----------------------------------------------------------//
|
||||
esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t *trans, TickType_t timeout)
|
||||
{
|
||||
@ -575,7 +607,7 @@ esp_err_t spi_slave_hd_append_trans(spi_host_device_t host_id, spi_slave_chan_t
|
||||
esp_err_t spi_slave_hd_get_append_trans_res(spi_host_device_t host_id, spi_slave_chan_t chan, spi_slave_hd_data_t **out_trans, TickType_t timeout)
|
||||
{
|
||||
esp_err_t ret;
|
||||
spi_slave_hd_slot_t* host = spihost[host_id];
|
||||
spi_slave_hd_slot_t *host = spihost[host_id];
|
||||
|
||||
SPIHD_CHECK(host->append_mode == 1, "This API should be used for SPI Slave HD Append Mode", ESP_ERR_INVALID_STATE);
|
||||
SPIHD_CHECK(chan == SPI_SLAVE_CHAN_TX || chan == SPI_SLAVE_CHAN_RX, "Invalid channel", ESP_ERR_INVALID_ARG);
|
||||
@ -583,4 +615,3 @@ esp_err_t spi_slave_hd_get_append_trans_res(spi_host_device_t host_id, spi_slave
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
||||
|
@ -1,16 +1,8 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
@ -258,8 +250,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal);
|
||||
*/
|
||||
int spi_slave_hd_hal_get_last_addr(spi_slave_hd_hal_context_t *hal);
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Append Mode
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
@ -315,4 +306,3 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
||||
* - ESP_ERR_INVALID_STATE: Function called in invalid state.
|
||||
*/
|
||||
esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg);
|
||||
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
||||
|
@ -1,16 +1,8 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for SPI Slave HD
|
||||
|
||||
@ -29,7 +21,8 @@
|
||||
#if SOC_GDMA_SUPPORTED
|
||||
#include "soc/gdma_struct.h"
|
||||
#include "hal/gdma_ll.h"
|
||||
|
||||
#define spi_dma_ll_tx_restart(dev, chan) gdma_ll_tx_restart(&GDMA, chan)
|
||||
#define spi_dma_ll_rx_restart(dev, chan) gdma_ll_rx_restart(&GDMA, chan)
|
||||
#define spi_dma_ll_rx_reset(dev, chan) gdma_ll_rx_reset_channel(&GDMA, chan)
|
||||
#define spi_dma_ll_tx_reset(dev, chan) gdma_ll_tx_reset_channel(&GDMA, chan)
|
||||
#define spi_dma_ll_rx_enable_burst_data(dev, chan, enable) gdma_ll_rx_enable_data_burst(&GDMA, chan, enable)
|
||||
@ -62,7 +55,7 @@ static void s_spi_slave_hd_hal_dma_init_config(const spi_slave_hd_hal_context_t
|
||||
|
||||
void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config)
|
||||
{
|
||||
spi_dev_t* hw = SPI_LL_GET_HW(hal_config->host_id);
|
||||
spi_dev_t *hw = SPI_LL_GET_HW(hal_config->host_id);
|
||||
hal->dev = hw;
|
||||
hal->dma_in = hal_config->dma_in;
|
||||
hal->dma_out = hal_config->dma_out;
|
||||
@ -107,13 +100,14 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h
|
||||
//Workaround if the previous interrupts are not writable
|
||||
spi_ll_set_intr(hw, SPI_LL_INTR_TRANS_DONE);
|
||||
}
|
||||
}
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
else {
|
||||
} else {
|
||||
#if SOC_GDMA_SUPPORTED
|
||||
spi_ll_enable_intr(hw, SPI_LL_INTR_CMD7);
|
||||
#else
|
||||
spi_ll_clear_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7);
|
||||
spi_ll_enable_intr(hw, SPI_LL_INTR_OUT_EOF | SPI_LL_INTR_CMD7);
|
||||
#endif //SOC_GDMA_SUPPORTED
|
||||
}
|
||||
#endif
|
||||
|
||||
spi_ll_slave_hd_set_len_cond(hw, SPI_LL_TRANS_LEN_COND_WRBUF |
|
||||
SPI_LL_TRANS_LEN_COND_WRDMA |
|
||||
@ -172,7 +166,6 @@ static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t
|
||||
{
|
||||
spi_ll_intr_t intr = 0;
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
if ((ev & SPI_EV_SEND) && hal->append_mode) intr |= SPI_LL_INTR_OUT_EOF;
|
||||
#endif
|
||||
if ((ev & SPI_EV_SEND) && !hal->append_mode) intr |= SPI_LL_INTR_CMD8;
|
||||
@ -221,13 +214,13 @@ bool spi_slave_hd_hal_check_disable_event(spi_slave_hd_hal_context_t *hal, spi_e
|
||||
return false;
|
||||
}
|
||||
|
||||
void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
|
||||
void spi_slave_hd_hal_enable_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
|
||||
{
|
||||
spi_ll_intr_t intr = get_event_intr(hal, ev);
|
||||
spi_ll_enable_intr(hal->dev, intr);
|
||||
}
|
||||
|
||||
void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t* hal, spi_event_t ev)
|
||||
void spi_slave_hd_hal_invoke_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
|
||||
{
|
||||
spi_ll_intr_t intr = get_event_intr(hal, ev);
|
||||
|
||||
@ -262,7 +255,7 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
|
||||
|
||||
int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal)
|
||||
{
|
||||
lldesc_t* desc = &hal->dmadesc_rx->desc;
|
||||
lldesc_t *desc = &hal->dmadesc_rx->desc;
|
||||
return lldesc_get_received_len(desc, NULL);
|
||||
}
|
||||
|
||||
@ -293,8 +286,6 @@ bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, voi
|
||||
return true;
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32S2
|
||||
//Append mode is only supported on ESP32S2 now
|
||||
static void spi_slave_hd_hal_link_append_desc(spi_slave_hd_hal_desc_append_t *dmadesc, const void *data, int len, bool isrx, void *arg)
|
||||
{
|
||||
HAL_ASSERT(len <= LLDESC_MAX_NUM_PER_DESC); //TODO: Add support for transaction with length larger than 4092, IDF-2660
|
||||
@ -342,7 +333,6 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
||||
hal->tx_dma_started = true;
|
||||
//start a link
|
||||
hal->tx_dma_tail = hal->tx_cur_desc;
|
||||
spi_ll_clear_intr(hal->dev, SPI_LL_INTR_OUT_EOF);
|
||||
spi_ll_dma_tx_fifo_reset(hal->dma_out);
|
||||
spi_ll_outfifo_empty_clr(hal->dev);
|
||||
spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan);
|
||||
@ -383,7 +373,6 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
||||
hal->rx_dma_started = true;
|
||||
//start a link
|
||||
hal->rx_dma_tail = hal->rx_cur_desc;
|
||||
spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
|
||||
spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan);
|
||||
spi_ll_dma_rx_fifo_reset(hal->dma_in);
|
||||
spi_ll_infifo_full_clr(hal->dev);
|
||||
@ -407,4 +396,3 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
||||
|
||||
return ESP_OK;
|
||||
}
|
||||
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
||||
|
@ -163,6 +163,7 @@ void app_main(void)
|
||||
|
||||
ESP_ERROR_CHECK(receiver(essl));
|
||||
ESP_ERROR_CHECK(sender(essl));
|
||||
ESP_LOGI("Append", "Example done.");
|
||||
|
||||
ESP_ERROR_CHECK(essl_spi_deinit_dev(essl));
|
||||
ESP_ERROR_CHECK(spi_bus_remove_device(spi));
|
||||
|
@ -666,7 +666,6 @@ components/hal/include/hal/rtc_io_types.h
|
||||
components/hal/include/hal/sdio_slave_ll.h
|
||||
components/hal/include/hal/sha_hal.h
|
||||
components/hal/include/hal/spi_flash_encrypt_hal.h
|
||||
components/hal/include/hal/spi_slave_hd_hal.h
|
||||
components/hal/include/hal/uhci_types.h
|
||||
components/hal/include/hal/usb_hal.h
|
||||
components/hal/include/hal/usb_types_private.h
|
||||
@ -676,7 +675,6 @@ components/hal/spi_flash_encrypt_hal_iram.c
|
||||
components/hal/spi_flash_hal_gpspi.c
|
||||
components/hal/spi_slave_hal.c
|
||||
components/hal/spi_slave_hal_iram.c
|
||||
components/hal/spi_slave_hd_hal.c
|
||||
components/hal/test/test_mpu.c
|
||||
components/hal/touch_sensor_hal.c
|
||||
components/hal/uart_hal_iram.c
|
||||
|
Loading…
Reference in New Issue
Block a user