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Merge branch 'feature/remove_psram_cs_clk_pin_settings_config_s2_s3' into 'master'

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PSRAM: remove CS/CLK pin settings in kconfig on ESP32S2/S3

Closes IDF-5966

See merge request espressif/esp-idf!20162
This commit is contained in:
Armando (Dou Yiwen) 2022-11-14 17:36:44 +08:00
commit 66b1c34095
7 changed files with 27 additions and 35 deletions
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21
components/esp_psram/esp32s2/Kconfig.spiram
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@ -40,22 +40,13 @@ menu "SPI RAM config"
This should only be used for tasks where the stack is never accessed while the cache is disabled. This should only be used for tasks where the stack is never accessed while the cache is disabled.
Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH. Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH.
menu "PSRAM clock and cs IO for ESP32S2" config SPIRAM_CLK_IO
depends on SPIRAM int
config DEFAULT_PSRAM_CLK_IO default 30
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
config DEFAULT_PSRAM_CS_IO config SPIRAM_CS_IO
int "PSRAM CS IO number" int
range 0 33 default 26
default 26
help
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS config SPIRAM_FETCH_INSTRUCTIONS
bool "Move Instructions in Flash to PSRAM" bool "Move Instructions in Flash to PSRAM"

4
components/esp_psram/esp32s2/esp_psram_impl_quad.c
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@ -72,8 +72,8 @@ static const char* TAG = "quad_psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design. // PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM

21
components/esp_psram/esp32s3/Kconfig.spiram
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@ -49,22 +49,13 @@ menu "SPI RAM config"
This should only be used for tasks where the stack is never accessed while the cache is disabled. This should only be used for tasks where the stack is never accessed while the cache is disabled.
Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH. Cannot be used together with ESP_COREDUMP_ENABLE_TO_FLASH.
menu "PSRAM Clock and CS IO for ESP32S3" config SPIRAM_CLK_IO
depends on SPIRAM int
config DEFAULT_PSRAM_CLK_IO default 30
int "PSRAM CLK IO number"
range 0 33
default 30
help
The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design.
config DEFAULT_PSRAM_CS_IO config SPIRAM_CS_IO
int "PSRAM CS IO number" int
range 0 33 default 26
default 26
help
The PSRAM CS IO can be any unused GPIO, please refer to your hardware design.
endmenu
config SPIRAM_FETCH_INSTRUCTIONS config SPIRAM_FETCH_INSTRUCTIONS
bool "Move Instructions in Flash to PSRAM" bool "Move Instructions in Flash to PSRAM"

2
components/esp_psram/esp32s3/esp_psram_impl_octal.c
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@ -29,7 +29,7 @@
#define OCT_PSRAM_ADDR_BITLEN 32 #define OCT_PSRAM_ADDR_BITLEN 32
#define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1)) #define OCT_PSRAM_RD_DUMMY_BITLEN (2*(10-1))
#define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1)) #define OCT_PSRAM_WR_DUMMY_BITLEN (2*(5-1))
#define OCT_PSRAM_CS1_IO CONFIG_DEFAULT_PSRAM_CS_IO #define OCT_PSRAM_CS1_IO SPI_CS1_GPIO_NUM
#define OCT_PSRAM_CS_SETUP_TIME 3 #define OCT_PSRAM_CS_SETUP_TIME 3
#define OCT_PSRAM_CS_HOLD_TIME 3 #define OCT_PSRAM_CS_HOLD_TIME 3

4
components/esp_psram/esp32s3/esp_psram_impl_quad.c
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@ -68,8 +68,8 @@ static const char* TAG = "quad_psram";
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM #define FLASH_CS_IO SPI_CS0_GPIO_NUM
// PSRAM clock and cs IO should be configured based on hardware design. // PSRAM clock and cs IO should be configured based on hardware design.
#define PSRAM_CLK_IO CONFIG_DEFAULT_PSRAM_CLK_IO // Default value is 30 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
#define PSRAM_CS_IO CONFIG_DEFAULT_PSRAM_CS_IO // Default value is 26 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
#define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
#define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
#define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM

5
components/esp_psram/sdkconfig.rename.esp32s2 Normal file
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@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO

5
components/esp_psram/sdkconfig.rename.esp32s3 Normal file
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@ -0,0 +1,5 @@
# sdkconfig replacement configurations for deprecated options formatted as
# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
CONFIG_DEFAULT_PSRAM_CLK_IO CONFIG_SPIRAM_CLK_IO
CONFIG_DEFAULT_PSRAM_CS_IO CONFIG_SPIRAM_CS_IO