diff --git a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld
index 14d68cf777..e430d04575 100644
--- a/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld
+++ b/components/bootloader/subproject/main/ld/esp32p4/bootloader.ld
@@ -9,9 +9,9 @@
  *  Make sure the bootloader can load into main memory without overwriting itself.
  *
  *  ESP32-P4 ROM static data usage is as follows:
- *  - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
- *  - 0x4087c610 - 0x4087e610: CPU1 stack, can be reclaimed as heap after RTOS startup
- *  - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
+ *  - 0x4ff296b8 - 0x4ff3afc0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4ff3afc0 - 0x4ff3fba4: CPU1 stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4ff3fba4 - 0x4ff40000: ROM .bss and .data (not easily reclaimable)
  *
  *  The 2nd stage bootloader can take space up to the end of ROM shared
  *  buffers area (0x4087c610).
@@ -217,34 +217,38 @@ SECTIONS
 /**
  *  Appendix: Memory Usage of ROM bootloader
  *
- * 0x4086ad08 ------------------> _dram0_0_start
+ * 0x4ff296b8 ------------------> _dram0_0_start
  *            |               |
  *            |               |
  *            |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
  *            |               |
  *            |               |
- * 0x4087c610 ------------------> __stack_sentry
+ * 0x4ff3afc0 ------------------> __stack_sentry
  *            |               |
  *            |               |   2. Startup pro cpu stack (freed when IDF app is running)
  *            |               |
- * 0x4087e610 ------------------> __stack (pro cpu)
+ * 0x4ff3cfc0 ------------------> __stack (pro cpu)
+ *            |               |
+ *            |               |      Startup app cpu stack
+ *            |               |
+ * 0x4ff3efc0 ------------------> __stack_app (app cpu)
  *            |               |
  *            |               |
  *            |               |   3. Shared memory only used in startup code or nonos/early boot*
  *            |               |      (can be freed when IDF runs)
  *            |               |
  *            |               |
- * 0x4087f564 ------------------> _dram0_rtos_reserved_start
+ * 0x4ff3fba4 ------------------> _dram0_rtos_reserved_start
  *            |               |
  *            |               |
  *            |               |   4. Shared memory used in startup code and when IDF runs
  *            |               |
  *            |               |
- * 0x4087fab0 ------------------> _dram0_rtos_reserved_end
+ * 0x4ff3ff94 ------------------> _dram0_rtos_reserved_end
  *            |               |
- * 0x4087fce8 ------------------> _data_start_interface
+ * 0x4ff3ffc8 ------------------> _data_start_interface
  *            |               |
  *            |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
  *            |               |
- * 0x40880000 ------------------> _data_end_interface
+ * 0x4ff40000 ------------------> _data_end_interface
  */
diff --git a/components/heap/port/esp32p4/memory_layout.c b/components/heap/port/esp32p4/memory_layout.c
index eb29b5fb22..dc5afa7496 100644
--- a/components/heap/port/esp32p4/memory_layout.c
+++ b/components/heap/port/esp32p4/memory_layout.c
@@ -71,26 +71,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 /**
  * Register the shared buffer area of the last memory block into the heap during heap initialization
  */
-#define APP_USABLE_DRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
+#define APP_USABLE_DIRAM_END    (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
+#define STARTUP_DATA_SIZE      (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
 
 const soc_memory_region_t soc_memory_regions[] = {
 #ifdef CONFIG_SPIRAM
-    { SOC_EXTRAM_LOW,   SOC_EXTRAM_SIZE,    SOC_MEMORY_TYPE_SPIRAM, 0,             false}, //PSRAM, if available
-#endif
-    // base 192k is always avaible, even if we config l2 cache size to 512k
-    { 0x4ff00000,       0x30000,            SOC_MEMORY_TYPE_L2MEM,  0x4ff00000,    false},
-    // 64k for rom startup stack
-    { 0x4ff30000,       0x10000,            SOC_MEMORY_TYPE_L2MEM,  0x4ff30000,    true},
-#if CONFIG_ESP32P4_L2_CACHE_256KB // 768-256 = 512k avaible for l2 memory, add extra 256k
-    { 0x4ff40000,       0x40000,            SOC_MEMORY_TYPE_L2MEM,  0x4ff40000,    false},
-#endif
-#if CONFIG_ESP32P4_L2_CACHE_128KB // 768 - 128 = 640k avaible for l2 memory, add extra 384k
-    { 0x4ff40000,       0x60000,            SOC_MEMORY_TYPE_L2MEM,  0x4ff40000,    false},
+    { SOC_EXTRAM_LOW,       SOC_EXTRAM_SIZE,                        SOC_MEMORY_TYPE_SPIRAM, 0,                      false}, //PSRAM, if available
 #endif
+    { SOC_DRAM_LOW,         APP_USABLE_DIRAM_END - SOC_DRAM_LOW,    SOC_MEMORY_TYPE_L2MEM,  SOC_IRAM_LOW,           false},
+    { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE,                      SOC_MEMORY_TYPE_L2MEM,  APP_USABLE_DIRAM_END,   true},
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50108000,       0x8000,             SOC_MEMORY_TYPE_RTCRAM, 0,             false}, //LPRAM
+    { 0x50108000,           0x8000,                                 SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
 #endif
-    { 0x30100000,       0x2000,             SOC_MEMORY_TYPE_TCM,    0,             false},
+    { 0x30100000,           0x2000,                                 SOC_MEMORY_TYPE_TCM,    0,                      false},
 };
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
@@ -98,6 +91,7 @@ const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_m
 
 extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
 extern int _tcm_text_start, _tcm_data_end;
+extern int _rtc_reserved_start, _rtc_reserved_end;
 
 /**
  * Reserved memory regions.
@@ -118,6 +112,7 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region);
 #endif
 
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-// TODO: IDF-6019 check reserved lp mem region
 SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_slow_end, rtcram_data);
 #endif
+
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_rtc_reserved_start, (intptr_t)&_rtc_reserved_end, rtc_reserved_data);
diff --git a/components/heap/port/memory_layout_utils.c b/components/heap/port/memory_layout_utils.c
index ee875fb6ce..af4cb5bfb7 100644
--- a/components/heap/port/memory_layout_utils.c
+++ b/components/heap/port/memory_layout_utils.c
@@ -71,8 +71,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
     /* Get the ROM layout to find which part of DRAM is reserved */
     const ets_rom_layout_t *layout = ets_rom_layout_p;
     reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
-#if CONFIG_IDF_TARGET_ESP32P4
-    //TODO: IDF-7921
+#ifdef SOC_DIRAM_ROM_RESERVE_HIGH
     reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH;
 #else
     reserved[0].end = SOC_DIRAM_DRAM_HIGH;
diff --git a/components/soc/esp32p4/include/soc/soc.h b/components/soc/esp32p4/include/soc/soc.h
index 7bbcd0618b..2c274fae9b 100644
--- a/components/soc/esp32p4/include/soc/soc.h
+++ b/components/soc/esp32p4/include/soc/soc.h
@@ -225,7 +225,7 @@
 #define SOC_DEBUG_HIGH 0x28000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
-#define SOC_ROM_STACK_START         0x4ff5abd0
+#define SOC_ROM_STACK_START         0x4ff3cfc0
 #define SOC_ROM_STACK_SIZE          0x2000
 
 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.