From f8d439dee308cf7b3a61e7f7698a68bb1a2f3c35 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 3 Aug 2022 15:22:49 +0200 Subject: [PATCH 1/2] replace CAN with TWAI in the esp_isr_names table --- components/soc/esp32/interrupts.c | 20 ++++++-------------- components/soc/esp32s2/interrupts.c | 20 ++++++-------------- tools/ci/check_copyright_ignore.txt | 2 -- 3 files changed, 12 insertions(+), 30 deletions(-) diff --git a/components/soc/esp32/interrupts.c b/components/soc/esp32/interrupts.c index ed23bbd42b..76b3032a19 100644 --- a/components/soc/esp32/interrupts.c +++ b/components/soc/esp32/interrupts.c @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/interrupts.h" @@ -60,7 +52,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [42] = "PWM3", [43] = "LEDC", [44] = "EFUSE", - [45] = "CAN", + [45] = "TWAI", [46] = "RTC_CORE", [47] = "RMT", [48] = "PCNT", diff --git a/components/soc/esp32s2/interrupts.c b/components/soc/esp32s2/interrupts.c index d84a9dac57..460c907ef0 100644 --- a/components/soc/esp32s2/interrupts.c +++ b/components/soc/esp32s2/interrupts.c @@ -1,16 +1,8 @@ -// Copyright 2019 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/interrupts.h" @@ -62,7 +54,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [44] = "PWM3", [45] = "LEDC", [46] = "EFUSE", - [47] = "CAN", + [47] = "TWAI", [48] = "USB", [49] = "RTC_CORE", [50] = "RMT", diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 2de1bea9a5..5dbddc2771 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1032,7 +1032,6 @@ components/soc/esp32/include/soc/uart_struct.h components/soc/esp32/include/soc/uhci_reg.h components/soc/esp32/include/soc/uhci_struct.h components/soc/esp32/include/soc/wdev_reg.h -components/soc/esp32/interrupts.c components/soc/esp32/ledc_periph.c components/soc/esp32/sdio_slave_periph.c components/soc/esp32/sdmmc_periph.c @@ -1174,7 +1173,6 @@ components/soc/esp32s2/include/soc/usb_wrap_reg.h components/soc/esp32s2/include/soc/usb_wrap_struct.h components/soc/esp32s2/include/soc/usbh_struct.h components/soc/esp32s2/include/soc/wdev_reg.h -components/soc/esp32s2/interrupts.c components/soc/esp32s2/ledc_periph.c components/soc/esp32s2/spi_periph.c components/soc/esp32s2/uart_periph.c From 66e3a6f6a343cc0d73c2d74491e0e9e3efadef85 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 3 Aug 2022 14:55:11 +0200 Subject: [PATCH 2/2] esp32s3: fix interrupt names used by SystemView --- .../soc/esp32s3/include/soc/periph_defs.h | 2 +- components/soc/esp32s3/interrupts.c | 178 ++++++++++-------- tools/ci/check_copyright_ignore.txt | 1 - 3 files changed, 99 insertions(+), 82 deletions(-) diff --git a/components/soc/esp32s3/include/soc/periph_defs.h b/components/soc/esp32s3/include/soc/periph_defs.h index 78510ca83f..0d16f7fda7 100644 --- a/components/soc/esp32s3/include/soc/periph_defs.h +++ b/components/soc/esp32s3/include/soc/periph_defs.h @@ -151,7 +151,7 @@ typedef enum { ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_USB_SERIAL_JTAG_INTR_SOURCE, - ETS_PREI_BACKUP_INTR_SOURCE, + ETS_PERI_BACKUP_INTR_SOURCE, ETS_DMA_EXTMEM_REJECT_SOURCE, ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ } periph_interrput_t; diff --git a/components/soc/esp32s3/interrupts.c b/components/soc/esp32s3/interrupts.c index 1de9d9057b..3f074b00b9 100644 --- a/components/soc/esp32s3/interrupts.c +++ b/components/soc/esp32s3/interrupts.c @@ -1,87 +1,105 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "soc/interrupts.h" const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { [0] = "WIFI_MAC", [1] = "WIFI_NMI", - [2] = "WIFI_BB", - [3] = "BT_MAC", - [4] = "BT_BB", - [5] = "BT_BB_NMI", - [6] = "RWBT", - [7] = "RWBLE", - [8] = "RWBT_NMI", - [9] = "RWBLE_NMI", - [10] = "SLC0", - [11] = "SLC1", - [12] = "UHCI0", - [13] = "UHCI1", - [14] = "TG0_T0_LEVEL", - [15] = "TG0_T1_LEVEL", - [16] = "TG0_WDT_LEVEL", - [17] = "TG0_LACT_LEVEL", - [18] = "TG1_T0_LEVEL", - [19] = "TG1_T1_LEVEL", - [20] = "TG1_WDT_LEVEL", - [21] = "TG1_LACT_LEVEL", - [22] = "GPIO", - [23] = "GPIO_NMI", - [24] = "FROM_CPU0", - [25] = "FROM_CPU1", - [26] = "FROM_CPU2", - [27] = "FROM_CPU3", - [28] = "SPI0", - [29] = "SPI1", - [30] = "SPI2", - [31] = "SPI3", - [32] = "I2S0", - [33] = "I2S1", - [34] = "UART0", - [35] = "UART1", - [36] = "UART2", - [37] = "SDIO_HOST", - [38] = "ETH_MAC", - [39] = "PWM0", - [40] = "PWM1", - [41] = "PWM2", - [42] = "PWM3", - [43] = "LEDC", - [44] = "EFUSE", - [45] = "TWAI", - [46] = "RTC_CORE", - [47] = "RMT", - [48] = "PCNT", - [49] = "I2C_EXT0", - [50] = "I2C_EXT1", - [51] = "RSA", - [52] = "SPI1_DMA", - [53] = "SPI2_DMA", - [54] = "SPI3_DMA", - [55] = "WDT", - [56] = "TIMER1", - [57] = "TIMER2", - [58] = "TG0_T0_EDGE", - [59] = "TG0_T1_EDGE", - [60] = "TG0_WDT_EDGE", - [61] = "TG0_LACT_EDGE", - [62] = "TG1_T0_EDGE", - [63] = "TG1_T1_EDGE", - [64] = "TG1_WDT_EDGE", - [65] = "TG1_LACT_EDGE", - [66] = "MMU_IA", - [67] = "MPU_IA", - [68] = "CACHE_IA", + [2] = "WIFI_PWR", + [3] = "WIFI_BB", + [4] = "BT_MAC", + [5] = "BT_BB", + [6] = "BT_BB_NMI", + [7] = "RWBT", + [8] = "RWBLE", + [9] = "RWBT_NMI", + [10] = "RWBLE_NMI", + [11] = "I2C_MASTER", + [12] = "SLC0", + [13] = "SLC1", + [14] = "UHCI0", + [15] = "UHCI1", + [16] = "GPIO", + [17] = "GPIO_NMI", + [18] = "GPIO_INTR_2", + [19] = "GPIO_NMI_2", + [20] = "SPI1", + [21] = "SPI2", + [22] = "SPI3", + [24] = "LCD_CAM", + [25] = "I2S0", + [26] = "I2S1", + [27] = "UART0", + [28] = "UART1", + [29] = "UART2", + [30] = "SDIO_HOST", + [31] = "PWM0", + [32] = "PWM1", + [35] = "LEDC", + [36] = "EFUSE", + [37] = "TWAI", + [38] = "USB", + [39] = "RTC_CORE", + [40] = "RMT", + [41] = "PCNT", + [42] = "I2C_EXT0", + [43] = "I2C_EXT1", + [44] = "SPI2_DMA", + [45] = "SPI3_DMA", + [47] = "WDT", + [48] = "TIMER1", + [49] = "TIMER2", + [50] = "TG0_T0_LEVEL", + [51] = "TG0_T1_LEVEL", + [52] = "TG0_WDT_LEVEL", + [53] = "TG1_T0_LEVEL", + [54] = "TG1_T1_LEVEL", + [55] = "TG1_WDT_LEVEL", + [56] = "CACHE_IA", + [57] = "SYSTIMER_TARGET0", + [58] = "SYSTIMER_TARGET1", + [59] = "SYSTIMER_TARGET2", + [60] = "SPI_MEM_REJECT_CACHE", + [61] = "DCACHE_PRELOAD0", + [62] = "ICACHE_PRELOAD0", + [63] = "DCACHE_SYNC0", + [64] = "ICACHE_SYNC0", + [65] = "APB_ADC", + [66] = "DMA_IN_CH0", + [67] = "DMA_IN_CH1", + [68] = "DMA_IN_CH2", + [69] = "DMA_IN_CH3", + [70] = "DMA_IN_CH4", + [71] = "DMA_OUT_CH0", + [72] = "DMA_OUT_CH1", + [73] = "DMA_OUT_CH2", + [74] = "DMA_OUT_CH3", + [75] = "DMA_OUT_CH4", + [76] = "RSA", + [77] = "SHA", + [78] = "AES", + [79] = "FROM_CPU_INTR0", + [80] = "FROM_CPU_INTR1", + [81] = "FROM_CPU_INTR2", + [82] = "FROM_CPU_INTR3", + [83] = "ASSIST_DEBUG", + [84] = "DMA_APBPERI_PMS", + [85] = "CORE0_IRAM0_PMS", + [86] = "CORE0_DRAM0_PMS", + [87] = "CORE0_PIF_PMS", + [88] = "CORE0_PIF_PMS_SIZE", + [89] = "CORE1_IRAM0_PMS", + [90] = "CORE1_DRAM0_PMS", + [91] = "CORE1_PIF_PMS", + [92] = "CORE1_PIF_PMS_SIZE", + [93] = "BACKUP_PMS_VIOLATE", + [94] = "CACHE_CORE0_ACS", + [95] = "CACHE_CORE1_ACS", + [96] = "USB_SERIAL_JTAG", + [97] = "PERI_BACKUP", + [98] = "DMA_EXTMEM_REJECT", }; diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 5dbddc2771..2a4e8c7192 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1256,7 +1256,6 @@ components/soc/esp32s3/include/soc/usb_wrap_reg.h components/soc/esp32s3/include/soc/usb_wrap_struct.h components/soc/esp32s3/include/soc/usbh_struct.h components/soc/esp32s3/include/soc/wdev_reg.h -components/soc/esp32s3/interrupts.c components/soc/esp32s3/ledc_periph.c components/soc/esp32s3/rtc_io_periph.c components/soc/esp32s3/sdio_slave_periph.c