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Merge branch 's3_sysview_irq_names' into 'master'
Fix ESP32-S3 interrupt names used by SystemView See merge request espressif/esp-idf!19373
This commit is contained in:
Roland Dobai
commit
656936d32a
@ -1,16 +1,8 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/interrupts.h"
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@ -60,7 +52,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
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[42] = "PWM3",
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[43] = "LEDC",
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[44] = "EFUSE",
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[45] = "CAN",
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[45] = "TWAI",
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[46] = "RTC_CORE",
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[47] = "RMT",
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[48] = "PCNT",
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@ -1,16 +1,8 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/interrupts.h"
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@ -62,7 +54,7 @@ const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
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[44] = "PWM3",
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[45] = "LEDC",
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[46] = "EFUSE",
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[47] = "CAN",
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[47] = "TWAI",
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[48] = "USB",
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[49] = "RTC_CORE",
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[50] = "RMT",
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@ -151,7 +151,7 @@ typedef enum {
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ETS_CACHE_CORE0_ACS_INTR_SOURCE,
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ETS_CACHE_CORE1_ACS_INTR_SOURCE,
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ETS_USB_SERIAL_JTAG_INTR_SOURCE,
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ETS_PREI_BACKUP_INTR_SOURCE,
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ETS_PERI_BACKUP_INTR_SOURCE,
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ETS_DMA_EXTMEM_REJECT_SOURCE,
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ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
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} periph_interrput_t;
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@ -1,87 +1,105 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/interrupts.h"
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const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
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[0] = "WIFI_MAC",
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[1] = "WIFI_NMI",
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[2] = "WIFI_BB",
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[3] = "BT_MAC",
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[4] = "BT_BB",
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[5] = "BT_BB_NMI",
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[6] = "RWBT",
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[7] = "RWBLE",
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[8] = "RWBT_NMI",
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[9] = "RWBLE_NMI",
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[10] = "SLC0",
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[11] = "SLC1",
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[12] = "UHCI0",
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[13] = "UHCI1",
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[14] = "TG0_T0_LEVEL",
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[15] = "TG0_T1_LEVEL",
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[16] = "TG0_WDT_LEVEL",
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[17] = "TG0_LACT_LEVEL",
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[18] = "TG1_T0_LEVEL",
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[19] = "TG1_T1_LEVEL",
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[20] = "TG1_WDT_LEVEL",
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[21] = "TG1_LACT_LEVEL",
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[22] = "GPIO",
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[23] = "GPIO_NMI",
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[24] = "FROM_CPU0",
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[25] = "FROM_CPU1",
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[26] = "FROM_CPU2",
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[27] = "FROM_CPU3",
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[28] = "SPI0",
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[29] = "SPI1",
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[30] = "SPI2",
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[31] = "SPI3",
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[32] = "I2S0",
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[33] = "I2S1",
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[34] = "UART0",
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[35] = "UART1",
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[36] = "UART2",
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[37] = "SDIO_HOST",
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[38] = "ETH_MAC",
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[39] = "PWM0",
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[40] = "PWM1",
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[41] = "PWM2",
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[42] = "PWM3",
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[43] = "LEDC",
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[44] = "EFUSE",
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[45] = "TWAI",
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[46] = "RTC_CORE",
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[47] = "RMT",
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[48] = "PCNT",
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[49] = "I2C_EXT0",
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[50] = "I2C_EXT1",
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[51] = "RSA",
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[52] = "SPI1_DMA",
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[53] = "SPI2_DMA",
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[54] = "SPI3_DMA",
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[55] = "WDT",
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[56] = "TIMER1",
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[57] = "TIMER2",
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[58] = "TG0_T0_EDGE",
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[59] = "TG0_T1_EDGE",
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[60] = "TG0_WDT_EDGE",
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[61] = "TG0_LACT_EDGE",
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[62] = "TG1_T0_EDGE",
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[63] = "TG1_T1_EDGE",
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[64] = "TG1_WDT_EDGE",
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[65] = "TG1_LACT_EDGE",
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[66] = "MMU_IA",
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[67] = "MPU_IA",
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[68] = "CACHE_IA",
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[2] = "WIFI_PWR",
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[3] = "WIFI_BB",
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[4] = "BT_MAC",
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[5] = "BT_BB",
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[6] = "BT_BB_NMI",
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[7] = "RWBT",
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[8] = "RWBLE",
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[9] = "RWBT_NMI",
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[10] = "RWBLE_NMI",
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[11] = "I2C_MASTER",
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[12] = "SLC0",
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[13] = "SLC1",
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[14] = "UHCI0",
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[15] = "UHCI1",
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[16] = "GPIO",
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[17] = "GPIO_NMI",
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[18] = "GPIO_INTR_2",
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[19] = "GPIO_NMI_2",
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[20] = "SPI1",
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[21] = "SPI2",
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[22] = "SPI3",
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[24] = "LCD_CAM",
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[25] = "I2S0",
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[26] = "I2S1",
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[27] = "UART0",
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[28] = "UART1",
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[29] = "UART2",
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[30] = "SDIO_HOST",
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[31] = "PWM0",
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[32] = "PWM1",
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[35] = "LEDC",
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[36] = "EFUSE",
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[37] = "TWAI",
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[38] = "USB",
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[39] = "RTC_CORE",
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[40] = "RMT",
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[41] = "PCNT",
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[42] = "I2C_EXT0",
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[43] = "I2C_EXT1",
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[44] = "SPI2_DMA",
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[45] = "SPI3_DMA",
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[47] = "WDT",
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[48] = "TIMER1",
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[49] = "TIMER2",
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[50] = "TG0_T0_LEVEL",
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[51] = "TG0_T1_LEVEL",
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[52] = "TG0_WDT_LEVEL",
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[53] = "TG1_T0_LEVEL",
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[54] = "TG1_T1_LEVEL",
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[55] = "TG1_WDT_LEVEL",
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[56] = "CACHE_IA",
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[57] = "SYSTIMER_TARGET0",
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[58] = "SYSTIMER_TARGET1",
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[59] = "SYSTIMER_TARGET2",
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[60] = "SPI_MEM_REJECT_CACHE",
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[61] = "DCACHE_PRELOAD0",
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[62] = "ICACHE_PRELOAD0",
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[63] = "DCACHE_SYNC0",
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[64] = "ICACHE_SYNC0",
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[65] = "APB_ADC",
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[66] = "DMA_IN_CH0",
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[67] = "DMA_IN_CH1",
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[68] = "DMA_IN_CH2",
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[69] = "DMA_IN_CH3",
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[70] = "DMA_IN_CH4",
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[71] = "DMA_OUT_CH0",
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[72] = "DMA_OUT_CH1",
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[73] = "DMA_OUT_CH2",
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[74] = "DMA_OUT_CH3",
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[75] = "DMA_OUT_CH4",
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[76] = "RSA",
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[77] = "SHA",
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[78] = "AES",
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[79] = "FROM_CPU_INTR0",
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[80] = "FROM_CPU_INTR1",
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[81] = "FROM_CPU_INTR2",
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[82] = "FROM_CPU_INTR3",
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[83] = "ASSIST_DEBUG",
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[84] = "DMA_APBPERI_PMS",
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[85] = "CORE0_IRAM0_PMS",
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[86] = "CORE0_DRAM0_PMS",
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[87] = "CORE0_PIF_PMS",
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[88] = "CORE0_PIF_PMS_SIZE",
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[89] = "CORE1_IRAM0_PMS",
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[90] = "CORE1_DRAM0_PMS",
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[91] = "CORE1_PIF_PMS",
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[92] = "CORE1_PIF_PMS_SIZE",
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[93] = "BACKUP_PMS_VIOLATE",
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[94] = "CACHE_CORE0_ACS",
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[95] = "CACHE_CORE1_ACS",
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[96] = "USB_SERIAL_JTAG",
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[97] = "PERI_BACKUP",
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[98] = "DMA_EXTMEM_REJECT",
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};
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@ -1032,7 +1032,6 @@ components/soc/esp32/include/soc/uart_struct.h
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components/soc/esp32/include/soc/uhci_reg.h
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components/soc/esp32/include/soc/uhci_struct.h
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components/soc/esp32/include/soc/wdev_reg.h
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components/soc/esp32/interrupts.c
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components/soc/esp32/ledc_periph.c
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components/soc/esp32/sdio_slave_periph.c
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components/soc/esp32/sdmmc_periph.c
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@ -1174,7 +1173,6 @@ components/soc/esp32s2/include/soc/usb_wrap_reg.h
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components/soc/esp32s2/include/soc/usb_wrap_struct.h
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components/soc/esp32s2/include/soc/usbh_struct.h
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components/soc/esp32s2/include/soc/wdev_reg.h
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components/soc/esp32s2/interrupts.c
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components/soc/esp32s2/ledc_periph.c
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components/soc/esp32s2/spi_periph.c
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components/soc/esp32s2/uart_periph.c
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@ -1258,7 +1256,6 @@ components/soc/esp32s3/include/soc/usb_wrap_reg.h
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components/soc/esp32s3/include/soc/usb_wrap_struct.h
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components/soc/esp32s3/include/soc/usbh_struct.h
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components/soc/esp32s3/include/soc/wdev_reg.h
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components/soc/esp32s3/interrupts.c
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components/soc/esp32s3/ledc_periph.c
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components/soc/esp32s3/rtc_io_periph.c
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components/soc/esp32s3/sdio_slave_periph.c
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