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https://github.com/espressif/esp-idf.git
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fix(esp_hw_support): invalidate L1DCache before enter hardware sleep
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parent
157c5b52e3
commit
64c062047f
@ -117,28 +117,6 @@ rv_core_critical_regs_save:
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mv t3, t0
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mv t3, t0
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csrr t0, mscratch
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csrr t0, mscratch
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sw t0, RV_SLP_CTX_T0(t3)
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sw t0, RV_SLP_CTX_T0(t3)
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/* writeback dcache is required here!!! */
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la t0, CACHE_SYNC_MAP_REG
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li t1, 0x10 /* map l1 dcache */
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sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
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la t2, CACHE_SYNC_ADDR_REG
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sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */
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la t0, CACHE_SYNC_SIZE_REG
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sw zero, 0x0(t0) /* clear EXTMEM_CACHE_SYNC_SIZE_REG */
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la t1, CACHE_SYNC_CTRL_REG
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lw t2, 0x0(t1)
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ori t2, t2, 0x4
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sw t2, 0x0(t1)
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li t0, 0x10 /* SYNC_DONE bit */
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wait_sync_done:
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lw t2, 0x0(t1)
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and t2, t0, t2
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beqz t2, wait_sync_done
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lw t0, RV_SLP_CTX_T0(t3)
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lw t1, RV_SLP_CTX_T1(t3)
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lw t1, RV_SLP_CTX_T1(t3)
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lw t2, RV_SLP_CTX_T2(t3)
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lw t2, RV_SLP_CTX_T2(t3)
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lw t3, RV_SLP_CTX_T3(t3)
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lw t3, RV_SLP_CTX_T3(t3)
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@ -12,11 +12,13 @@
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#include "esp_err.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_attr.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "esp_private/regi2c_ctrl.h"
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#include "esp32p4/rom/cache.h"
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#include "soc/chip_revision.h"
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#include "soc/chip_revision.h"
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#include "soc/soc.h"
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#include "soc/soc.h"
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#include "soc/regi2c_syspll.h"
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#include "soc/regi2c_syspll.h"
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#include "soc/regi2c_cpll.h"
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#include "soc/regi2c_cpll.h"
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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#include "soc/cache_reg.h"
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#include "soc/pau_reg.h"
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#include "soc/pau_reg.h"
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#include "soc/pmu_reg.h"
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#include "soc/pmu_reg.h"
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#include "soc/pmu_struct.h"
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#include "soc/pmu_struct.h"
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@ -285,6 +287,11 @@ void pmu_sleep_shutdown_ldo(void) {
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CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
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CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_XPD);
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}
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}
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FORCE_INLINE_ATTR void sleep_writeback_l1_dcache(void) {
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Cache_WriteBack_All(CACHE_MAP_L1_DCACHE);
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while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE));
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}
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TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
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TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
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{
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{
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lp_aon_hal_inform_wakeup_type(dslp);
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lp_aon_hal_inform_wakeup_type(dslp);
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@ -297,6 +304,8 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
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pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
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pmu_ll_hp_clear_reject_intr_status(PMU_instance()->hal->dev);
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pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
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pmu_ll_hp_clear_reject_cause(PMU_instance()->hal->dev);
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sleep_writeback_l1_dcache();
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/* Start entry into sleep mode */
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/* Start entry into sleep mode */
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pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
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pmu_ll_hp_set_sleep_enable(PMU_instance()->hal->dev);
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