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fix(esp_hw_support): fix cpu_retention cache invalidate mask

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wuzhenghui 2024-07-11 22:01:49 +08:00
parent edf14a1de1
commit 64ace5b6d8
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GPG Key ID: 3EFEDECDEBA39BB9
2 changed files with 20 additions and 13 deletions
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3
components/esp_hw_support/lowpower/cpu_retention/port/esp32p4/sleep_cpu_asm.S
View File

@ -9,6 +9,7 @@
#include "freertos/FreeRTOSConfig.h"
#include "sdkconfig.h"
#include "esp32p4/rom/cache.h"
#include "soc/cache_reg.h"
#define MTVT (0x307)
@ -154,7 +155,7 @@ rv_core_critical_regs_restore:
/* Core 0 is wakeup core, Invalidate L1 Cache here */
/* Invalidate L1 cache is required here!!! */
la t0, CACHE_SYNC_MAP_REG
li t1, 0x7 /* map l1 i/dcache */
li t1, CACHE_MAP_L1_CACHE_MASK /* map l1 i/dcache */
sw t1, 0x0(t0) /* set EXTMEM_CACHE_SYNC_MAP_REG bit 4 */
la t2, CACHE_SYNC_ADDR_REG
sw zero, 0x0(t2) /* clear EXTMEM_CACHE_SYNC_ADDR_REG */

30
components/esp_rom/include/esp32p4/rom/cache.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,8 +7,10 @@
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
#include <stdint.h>
#include "esp_bit_defs.h"
#endif
#ifdef __cplusplus
extern "C" {
@ -86,6 +88,16 @@ extern "C" {
// should NOT =
#define SMMU_GID_TBIT_INDEX_HIGH (SMMU_GID_TBIT_INDEX_LOW + SMMU_GID_TBIT_NUM)
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
#define CACHE_MAP_L1_DCACHE BIT(4)
#define CACHE_MAP_L2_CACHE BIT(5)
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
#define CACHE_MAP_L1_CACHE_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE)
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
#if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
typedef enum {
CACHE_L1_ICACHE0 = 0,
CACHE_L1_ICACHE1 = 1,
@ -225,14 +237,6 @@ typedef enum {
CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
} cache_sync_t;
#define CACHE_MAP_L1_ICACHE_0 BIT(0)
#define CACHE_MAP_L1_ICACHE_1 BIT(1)
#define CACHE_MAP_L1_DCACHE BIT(4)
#define CACHE_MAP_L2_CACHE BIT(5)
#define CACHE_MAP_L1_ICACHE_MASK (CACHE_MAP_L1_ICACHE_0 | CACHE_MAP_L1_ICACHE_1)
#define CACHE_MAP_MASK (CACHE_MAP_L1_ICACHE_MASK | CACHE_MAP_L1_DCACHE | CACHE_MAP_L2_CACHE)
struct cache_internal_stub_table {
uint32_t (*l1_icache_line_size)(void);
uint32_t (*l1_dcache_line_size)(void);
@ -507,7 +511,7 @@ void ROM_Direct_Boot_Cache_Init(void);
*
* @param None
*
* @return 0 if mmu map is sucessfully, others if not.
* @return 0 if mmu map is successfully, others if not.
*/
int ROM_Direct_Boot_MMU_Init(void);
@ -1517,7 +1521,7 @@ void Cache_Freeze_L2_Cache_Disable(void);
void Cache_Travel_Tag_Memory(struct cache_mode *mode, uint32_t filter_addr, void (*process)(struct tag_group_info *, int res[]), int res[]);
/**
* @brief Travel tag memory to run a call back function using 2rd tag api.
* @brief Travel tag memory to run a call back function using 2nd tag api.
* ICache and DCache are suspend when doing this.
* The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
* Please do not call this function in your SDK application.
@ -1539,7 +1543,7 @@ void Cache_Travel_Tag_Memory2(struct cache_mode *mode, uint32_t filter_addr, voi
*
* @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
*
* @param uint32_t tag : the tag part fo a tag item, 12-14 bits.
* @param uint32_t tag : the tag part for a tag item, 12-14 bits.
*
* @param uint32_t addr_offset : the virtual address offset of the cache ways.
*
@ -1602,6 +1606,8 @@ int flash2spiram_rodata_offset(void);
uint32_t flash_instr_rodata_start_page(uint32_t bus);
uint32_t flash_instr_rodata_end_page(uint32_t bus);
#endif // #if (!defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__))
#ifdef __cplusplus
}
#endif