From 503b917ca5a8789482d0756e7bfc5089be268e65 Mon Sep 17 00:00:00 2001
From: Marius Vikhammer <marius.vikhammer@espressif.com>
Date: Thu, 7 Mar 2024 17:19:56 +0800
Subject: [PATCH] fix(bootloader): fixed P4 bootloader being able to boot with
 certain configs

Due to internal memory being behind a cache on P4 we need to make sure we do
cache write backs when manipulating IRAM over the dcache.
---
 .../bootloader_support/src/esp_image_format.c       | 13 ++++++++++++-
 examples/system/.build-test-rules.yml               |  6 ------
 examples/system/startup_time/pytest_startup_time.py |  1 -
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index 0a26247b56..c91089b23f 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -226,6 +226,8 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
             }
         }
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        /* We have manipulated data over dcache that will be read over icache and need
+           to writeback, else the data read might be invalid */
         cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
 #endif
     }
@@ -673,6 +675,13 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
 
     if (checksum == NULL && sha_handle == NULL) {
         memcpy((void *)load_addr, data, data_len);
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+        if (esp_ptr_in_iram((uint32_t *)load_addr)) {
+            /* If we have manipulated data over dcache that will be read over icache then we need
+               to writeback, else the data read might be invalid */
+            cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
+        }
+#endif
         bootloader_munmap(data);
         return ESP_OK;
     }
@@ -728,7 +737,9 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
         }
     }
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-    if (do_load && esp_ptr_in_diram_iram((uint32_t *)load_addr)) {
+    if (do_load && esp_ptr_in_iram((uint32_t *)load_addr)) {
+        /* If we have manipulated data over dcache that will be read over icache then we need
+           to writeback, else the data read might be invalid */
         cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
     }
 #endif
diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml
index 85ed27d783..a6f6727828 100644
--- a/examples/system/.build-test-rules.yml
+++ b/examples/system/.build-test-rules.yml
@@ -245,12 +245,6 @@ examples/system/select:
   depends_components:
     - vfs
 
-examples/system/startup_time:
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: test not pass, should be re-enable # TODO: IDF-8989
-
 examples/system/sysview_tracing:
   disable:
     - if: SOC_GPTIMER_SUPPORTED != 1
diff --git a/examples/system/startup_time/pytest_startup_time.py b/examples/system/startup_time/pytest_startup_time.py
index 4dbfe7b6fb..a2eff33822 100644
--- a/examples/system/startup_time/pytest_startup_time.py
+++ b/examples/system/startup_time/pytest_startup_time.py
@@ -6,7 +6,6 @@ import pytest
 from pytest_embedded import Dut
 
 
-@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='esp32p4 support TBD')  # TODO: IDF-8989
 @pytest.mark.supported_targets
 @pytest.mark.generic
 @pytest.mark.parametrize('config', [