alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-09-20 00:36:01 -04:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

Merge branch 'feature/default_clock_source_can_leave_empty' into 'master'

Browse Source 
feat(mcpwm): default clock source setting can leave empty

See merge request espressif/esp-idf!25478
This commit is contained in:
morris 2023-08-24 20:22:47 +08:00
commit 641fdabbf0
7 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
components/driver/deprecated/adc_legacy.c
View File

@ -670,7 +670,7 @@ static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuat
static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{
assert(adc_unit <= SOC_ADC_PERIPH_NUM);
assert(adc_unit < SOC_ADC_PERIPH_NUM);
uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
return adc_channel_io_map[adc_n][adc_channel];
}

2
components/driver/gptimer/Kconfig.gptimer
View File

@ -1,4 +1,5 @@
menu "GPTimer Configuration"
depends on SOC_GPTIMER_SUPPORTED
config GPTIMER_ISR_HANDLER_IN_IRAM
bool "Place GPTimer ISR handler into IRAM"
default y
@ -16,7 +17,6 @@ menu "GPTimer Configuration"
config GPTIMER_ISR_IRAM_SAFE
bool "GPTimer ISR IRAM-Safe"
select GPTIMER_ISR_HANDLER_IN_IRAM
select GPTIMER_ISR_NON_MASKABLE
default n
help
Ensure the GPTimer interrupt is IRAM-Safe by allowing the interrupt handler to be

5
components/driver/mcpwm/mcpwm_cap.c
View File

@ -96,13 +96,14 @@ esp_err_t mcpwm_new_capture_timer(const mcpwm_capture_timer_config_t *config, mc
mcpwm_group_t *group = cap_timer->group;
int group_id = group->group_id;
mcpwm_capture_clock_source_t clk_src = config->clk_src ? config->clk_src : MCPWM_CAPTURE_CLK_SRC_DEFAULT;
#if SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
// capture timer clock source is same as the MCPWM group
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)config->clk_src), err, TAG, "set group clock failed");
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)clk_src), err, TAG, "set group clock failed");
cap_timer->resolution_hz = group->resolution_hz;
#else
// capture timer has independent clock source selection
switch (config->clk_src) {
switch (clk_src) {
case MCPWM_CAPTURE_CLK_SRC_APB:
cap_timer->resolution_hz = esp_clk_apb_freq();
#if CONFIG_PM_ENABLE

3
components/driver/mcpwm/mcpwm_timer.c
View File

@ -110,7 +110,8 @@ esp_err_t mcpwm_new_timer(const mcpwm_timer_config_t *config, mcpwm_timer_handle
ESP_GOTO_ON_ERROR(mcpwm_check_intr_priority(group, config->intr_priority), err, TAG, "set group intrrupt priority failed");
// select the clock source
ESP_GOTO_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)config->clk_src), err, TAG, "set group clock failed");
mcpwm_timer_clock_source_t clk_src = config->clk_src ? config->clk_src : MCPWM_TIMER_CLK_SRC_DEFAULT;
ESP_RETURN_ON_ERROR(mcpwm_select_periph_clock(group, (soc_module_clk_t)clk_src), TAG, "set group clock failed");
// reset the timer to a determined state
mcpwm_hal_timer_reset(hal, timer_id);
// set timer resolution

2
components/esp_adc/adc_continuous.c
View File

@ -67,7 +67,7 @@ static void adc_dma_intr_handler(void *arg);
static int8_t adc_digi_get_io_num(adc_unit_t adc_unit, uint8_t adc_channel)
{
assert(adc_unit <= SOC_ADC_PERIPH_NUM);
assert(adc_unit < SOC_ADC_PERIPH_NUM);
uint8_t adc_n = (adc_unit == ADC_UNIT_1) ? 0 : 1;
return adc_channel_io_map[adc_n][adc_channel];
}

2
components/hal/README.md
View File

@ -61,7 +61,7 @@ The first argument of a HAL function is usually a pointer to the **context objec
`/include/hal` contains header files which provides a hardware-agnostic interface to the SoC. The interface consists of function declarations and abstracted types that other, higher level components can make use of in order to have code portable to all targets ESP-IDF supports.
It contains an abstraction layer for interacting with/driving the hardware found in the SoC such as the peripherals and 'core' hardware such as the CPU, MPU, caches, etc. It contains for the abstracted types.
The abstraction design is actually two levels -- often sometimes `xxx_hal.h` includes a lower-level header from a `xxx_ll.h`, which resides in the implementation. More on this abstraction design in the [`hal/include/hal`'s Readme](include/hal/readme.md)
The abstraction design is actually two levels -- often sometimes `xxx_hal.h` includes a lower-level header from a `xxx_ll.h`, which resides in the implementation.
### `target/include`

4
docs/en/api-reference/system/async_memcpy.rst
View File

@ -6,9 +6,9 @@ Overview
{IDF_TARGET_NAME} has a DMA engine which can help to offload internal memory copy operations from the CPU in an asynchronous way.
The async memcpy API wraps all DMA configurations and operations, the signature of :cpp:func:`esp_async_memcpy` is almost the same to the standard libc ``memcpy`` function.
The async memcpy API wraps all DMA configurations and operations, the signature of :cpp:func:`esp_async_memcpy` is almost the same as the standard libc ``memcpy`` function.
The DMA allows multiple memory copy requests to be queued up before the first one is completed, which allows overlap of computation and memory copy. By the way, it is still possible to know the exact time when a memory copy request is completed by registering an event callback.
The DMA allows multiple memory copy requests to be queued up before the first one is completed, which allows overlap of computation and memory copy. Moreover, it is still possible to know the exact time when a memory copy request is completed by registering an event callback.
.. only:: SOC_AHB_GDMA_SUPPORT_PSRAM