From 639e97437fbadb26dedb7f8c5e5faeb7ff3e92bd Mon Sep 17 00:00:00 2001
From: Angus Gratton <angus@espressif.com>
Date: Wed, 21 Oct 2020 15:09:22 +1100
Subject: [PATCH] esp32s2: Use regi2c registers to enable bootloader RNG

---
 .../src/bootloader_random_esp32s2.c           | 22 +++----
 components/hal/esp32s2/include/hal/adc_ll.h   | 60 -------------------
 .../esp32s2/private_include/regi2c_saradc.h   |  4 ++
 3 files changed, 15 insertions(+), 71 deletions(-)

diff --git a/components/bootloader_support/src/bootloader_random_esp32s2.c b/components/bootloader_support/src/bootloader_random_esp32s2.c
index c2b06b85ba..5ca8438039 100644
--- a/components/bootloader_support/src/bootloader_random_esp32s2.c
+++ b/components/bootloader_support/src/bootloader_random_esp32s2.c
@@ -51,14 +51,14 @@ void bootloader_random_enable(void)
     CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M);
     SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M);
     CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18));
-    SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16));
+    SET_PERI_REG_MASK(ANA_CONFIG2_REG, BIT(16));
 
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x4);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x4);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x4);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x4);
 
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 1);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
 
     REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0);
     WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffffff);    // set adc1 channel & bitwidth & atten
@@ -86,12 +86,12 @@ void bootloader_random_enable(void)
 void bootloader_random_disable(void)
 {
     /* Restore internal I2C bus state */
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x1);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 0x1);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 0x1);
 
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 0);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0);
-    REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
+    REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
 
     /* Restore SARADC to default mode */
     CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE);
diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h
index 530f67e6e0..cf4cd6e5eb 100644
--- a/components/hal/esp32s2/include/hal/adc_ll.h
+++ b/components/hal/esp32s2/include/hal/adc_ll.h
@@ -69,66 +69,6 @@ typedef enum {
     ADC2_CTRL_FORCE_DIG = 6,    /*!<For ADC2. Arbiter in shield mode. Force select digital controller work. */
 } adc_controller_t;
 
-/* ADC calibration defines. */
-#define ADC_LL_I2C_ADC            0X69
-#define ADC_LL_I2C_ADC_HOSTID     0
-
-#define ADC_LL_ANA_CONFIG2_REG  0x6000E048
-
-#define ADC_LL_SAR1_ENCAL_GND_ADDR 0x7
-#define ADC_LL_SAR1_ENCAL_GND_ADDR_MSB 5
-#define ADC_LL_SAR1_ENCAL_GND_ADDR_LSB 5
-
-#define ADC_LL_SAR2_ENCAL_GND_ADDR 0x7
-#define ADC_LL_SAR2_ENCAL_GND_ADDR_MSB 7
-#define ADC_LL_SAR2_ENCAL_GND_ADDR_LSB 7
-
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_LL_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR  0x0
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_LL_SAR1_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
-#define ADC_LL_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
-
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR  0x3
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_MSB  0x7
-#define ADC_LL_SAR2_INITIAL_CODE_LOW_ADDR_LSB  0x0
-
-#define ADC_LL_SAR1_DREF_ADDR  0x2
-#define ADC_LL_SAR1_DREF_ADDR_MSB  0x6
-#define ADC_LL_SAR1_DREF_ADDR_LSB  0x4
-
-#define ADC_LL_SAR2_DREF_ADDR  0x5
-#define ADC_LL_SAR2_DREF_ADDR_MSB  0x6
-#define ADC_LL_SAR2_DREF_ADDR_LSB  0x4
-
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR 0x2
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
-#define ADC_LL_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
-
-#define ADC_LL_SARADC_DTEST_RTC_ADDR 0x7
-#define ADC_LL_SARADC_DTEST_RTC_ADDR_MSB 1
-#define ADC_LL_SARADC_DTEST_RTC_ADDR_LSB 0
-
-#define ADC_LL_SARADC_ENT_TSENS_ADDR 0x7
-#define ADC_LL_SARADC_ENT_TSENS_ADDR_MSB 2
-#define ADC_LL_SARADC_ENT_TSENS_ADDR_LSB 2
-
-#define ADC_LL_SARADC_ENT_RTC_ADDR 0x7
-#define ADC_LL_SARADC_ENT_RTC_ADDR_MSB 3
-#define ADC_LL_SARADC_ENT_RTC_ADDR_LSB 3
-
-#define ADC_LL_SARADC_ENCAL_REF_ADDR 0x7
-#define ADC_LL_SARADC_ENCAL_REF_ADDR_MSB 4
-#define ADC_LL_SARADC_ENCAL_REF_ADDR_LSB 4
-
-/* ADC calibration defines end. */
-
 /*---------------------------------------------------------------
                     Digital controller setting
 ---------------------------------------------------------------*/
diff --git a/components/soc/soc/esp32s2/private_include/regi2c_saradc.h b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
index 0c223812bb..2345e0a5aa 100644
--- a/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
+++ b/components/soc/soc/esp32s2/private_include/regi2c_saradc.h
@@ -74,6 +74,10 @@
 #define ADC_SARADC_ENT_RTC_ADDR_MSB 3
 #define ADC_SARADC_ENT_RTC_ADDR_LSB 3
 
+#define ADC_SARADC_ENCAL_REF_ADDR 0x7
+#define ADC_SARADC_ENCAL_REF_ADDR_MSB 4
+#define ADC_SARADC_ENCAL_REF_ADDR_LSB 4
+
 #define I2C_SARADC_TSENS_DAC 0x6
 #define I2C_SARADC_TSENS_DAC_MSB 3
 #define I2C_SARADC_TSENS_DAC_LSB 0