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https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
deep sleep: modified to support dual-core mode
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@ -348,15 +348,6 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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// For deep sleep, wait for the contents of UART FIFO to be sent.
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bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
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bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
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#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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/* Currently only safe to use deep sleep wake stub & RTC memory as heap in single core mode.
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For ESP32-S3, either disable ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP in config or find a way to set the
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deep sleep wake stub to NULL.
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*/
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assert(!deep_sleep || esp_get_deep_sleep_wake_stub() == NULL);
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#endif
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if (deep_sleep) {
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if (deep_sleep) {
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flush_uarts();
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flush_uarts();
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} else {
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} else {
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@ -508,11 +499,17 @@ void IRAM_ATTR esp_deep_sleep_start(void)
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esp_brownout_disable();
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esp_brownout_disable();
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#endif //CONFIG_IDF_TARGET_ESP32S2
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#endif //CONFIG_IDF_TARGET_ESP32S2
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esp_sync_counters_rtc_and_frc();
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/* Disable interrupts and stall another core in case another task writes
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* to RTC memory while we calculate RTC memory CRC.
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*/
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portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
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esp_ipc_isr_stall_other_cpu();
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// record current RTC time
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// record current RTC time
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s_config.rtc_ticks_at_sleep_start = rtc_time_get();
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s_config.rtc_ticks_at_sleep_start = rtc_time_get();
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// record current RTC time
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esp_sync_counters_rtc_and_frc();
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// Configure wake stub
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// Configure wake stub
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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if (esp_get_deep_sleep_wake_stub() == NULL) {
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
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@ -544,6 +541,9 @@ void IRAM_ATTR esp_deep_sleep_start(void)
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while (1) {
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while (1) {
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;
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;
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}
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}
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// Never returns here
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esp_ipc_isr_release_other_cpu();
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portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
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}
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}
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/**
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/**
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