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fix(intr): fixed intr threshhold min level on C5
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parent
7ac98d33e3
commit
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@ -10,7 +10,7 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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#define NLBITS 3
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#define NLBITS 4
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define DUALCORE_CLIC_CTRL_OFF 0x10000
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#define DUALCORE_CLIC_CTRL_OFF 0x10000
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@ -10,7 +10,7 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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#define NLBITS 3
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#define NLBITS 4
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define CLIC_EXT_INTR_NUM_OFFSET 16
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#define DR_REG_CLIC_BASE (0x20800000)
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#define DR_REG_CLIC_BASE (0x20800000)
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@ -144,7 +144,7 @@ extern "C" {
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#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i)*4)
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#define BYTE_CLIC_INT_CTL_REG(i) (DR_REG_CLIC_CTRL_BASE + 3 + (i)*4)
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */
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/* BYTE_CLIC_INT_ATTR_MODE: R/W ; bitpos:[7:5] ;default: 3'd0 ; */
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/*description: interrupt pririty */
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/*description: interrupt priority */
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#define BYTE_CLIC_INT_CTL 0x00000007
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#define BYTE_CLIC_INT_CTL 0x00000007
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#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S))
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#define BYTE_CLIC_INT_CTL_M ((BYTE_CLIC_INT_CTL_V) << (BYTE_CLIC_INT_CTL_S))
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#define BYTE_CLIC_INT_CTL_V 0x7
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#define BYTE_CLIC_INT_CTL_V 0x7
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