From fefdee1349edd5edffd8d60601c0c46a04c5e4f4 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Thu, 12 Mar 2020 18:20:31 +0800 Subject: [PATCH 1/2] bootloader: fix the WRSR format for ISSI flash chips 1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability. This commit helps to clear WEL when flash configuration is done. **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA. 2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips. Status register bitmap of ISSI chip and GD chip: | SR | ISSI | GD25LQ32C | | -- | ---- | --------- | | 0 | WIP | WIP | | 1 | WEL | WEL | | 2 | BP0 | BP0 | | 3 | BP1 | BP1 | | 4 | BP2 | BP2 | | 5 | BP3 | BP3 | | 6 | QE | BP4 | | 7 | SRWD | SRP0 | | 8 | | SRP1 | | 9 | | QE | | 10 | | SUS2 | | 11 | | LB1 | | 12 | | LB2 | | 13 | | LB3 | | 14 | | CMP | | 15 | | SUS1 | QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command. However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips. Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected. This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6). 3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared. This commit skips the clearing of status register if there is no protection bits active. Also move the execute_flash_command to be a bootloader API; move implementation of spi_flash_wrap_set to the bootloader --- .../include_bootloader/bootloader_flash.h | 41 +++++ .../bootloader_support/src/bootloader_flash.c | 106 ++++++++++++- .../src/esp32/bootloader_esp32.c | 3 + .../src/esp32s2/bootloader_esp32s2.c | 3 + .../bootloader_support/src/flash_qio_mode.c | 145 +++--------------- .../esp_rom/include/esp32/rom/spi_flash.h | 1 + .../esp_rom/include/esp32s2/rom/opi_flash.h | 1 + .../esp_rom/include/esp32s2/rom/spi_flash.h | 1 + .../soc/soc/esp32s2/include/soc/soc_caps.h | 2 + .../soc/soc/esp32s3/include/soc/soc_caps.h | 1 + components/spi_flash/CMakeLists.txt | 3 +- components/spi_flash/Kconfig | 5 +- .../spi_flash/esp32/spi_flash_rom_patch.c | 42 +++-- .../spi_flash/esp32s2/flash_ops_esp32s2.c | 39 +---- components/spi_flash/flash_ops.c | 3 +- 15 files changed, 221 insertions(+), 175 deletions(-) diff --git a/components/bootloader_support/include_bootloader/bootloader_flash.h b/components/bootloader_support/include_bootloader/bootloader_flash.h index 6482dde99e..e2e0f3ed65 100644 --- a/components/bootloader_support/include_bootloader/bootloader_flash.h +++ b/components/bootloader_support/include_bootloader/bootloader_flash.h @@ -19,11 +19,26 @@ #include #include #include /* including in bootloader for error values */ +#include "sdkconfig.h" #define FLASH_SECTOR_SIZE 0x1000 #define FLASH_BLOCK_SIZE 0x10000 #define MMAP_ALIGNED_MASK 0x0000FFFF +/* SPI commands (actual on-wire commands not SPI controller bitmasks) + Suitable for use with the bootloader_execute_flash_command static function. +*/ +#define CMD_RDID 0x9F +#define CMD_WRSR 0x01 +#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ +#define CMD_WREN 0x06 +#define CMD_WRDI 0x04 +#define CMD_RDSR 0x05 +#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ +#define CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ +#define CMD_WRAP 0x77 /* Set burst with wrap command */ + + /* Provide a Flash API for bootloader_support code, that can be used from bootloader or app code. @@ -136,4 +151,30 @@ static inline uint32_t bootloader_cache_pages_to_map(uint32_t size, uint32_t vad return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE; } +/** + * @brief Execute a user command on the flash + * + * @param command The command value to execute. + * @param mosi_data MOSI data to send + * @param mosi_len Length of MOSI data, in bits + * @param miso_len Length of MISO data to receive, in bits + * @return Received MISO data + */ +uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len); + +/** + * @brief Enable the flash write protect (WEL bit). + */ +void bootloader_enable_wp(void); + +#if CONFIG_IDF_TARGET_ESP32S2 +/** + * @brief Set the burst mode setting command for specified wrap mode. + * + * @param mode The specified warp mode. + * @return always ESP_OK + */ +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + #endif diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index 9aadb8fc14..6716e3bc53 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -16,10 +16,26 @@ #include #include #include -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/spi_flash.h" +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if CONFIG_IDF_TARGET_ESP32 +# include "soc/spi_struct.h" +# include "soc/spi_reg.h" + /* SPI flash controller */ +# define SPIFLASH SPI1 +#else +# include "soc/spi_mem_struct.h" +# include "soc/spi_mem_reg.h" + /* SPI flash controller */ +# define SPIFLASH SPIMEM1 #endif +#if CONFIG_IDF_TARGET_ESP32S2 +#include "esp32s2/rom/spi_flash.h" //For SPI_Encrypt_Write +#endif + + #ifndef BOOTLOADER_BUILD /* Normal app version maps to esp_spi_flash.h operations... */ @@ -364,4 +380,90 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size) } return spi_to_esp_err(rc); } + #endif + +extern uint8_t g_rom_spiflash_dummy_len_plus[]; +uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len) +{ + uint32_t old_ctrl_reg = SPIFLASH.ctrl.val; +#if CONFIG_IDF_TARGET_ESP32 + SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode +#endif + SPIFLASH.user.usr_dummy = 0; + SPIFLASH.user.usr_addr = 0; + SPIFLASH.user.usr_command = 1; + SPIFLASH.user2.usr_command_bitlen = 7; + + SPIFLASH.user2.usr_command_value = command; + SPIFLASH.user.usr_miso = miso_len > 0; +#if CONFIG_IDF_TARGET_ESP32 + SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0; +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0; +#endif + SPIFLASH.user.usr_mosi = mosi_len > 0; +#if CONFIG_IDF_TARGET_ESP32 + SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0; +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 + SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0; +#endif + SPIFLASH.data_buf[0] = mosi_data; + + if (g_rom_spiflash_dummy_len_plus[1]) { + /* When flash pins are mapped via GPIO matrix, need a dummy cycle before reading via MISO */ + if (miso_len > 0) { + SPIFLASH.user.usr_dummy = 1; + SPIFLASH.user1.usr_dummy_cyclelen = g_rom_spiflash_dummy_len_plus[1] - 1; + } else { + SPIFLASH.user.usr_dummy = 0; + SPIFLASH.user1.usr_dummy_cyclelen = 0; + } + } + + SPIFLASH.cmd.usr = 1; + while (SPIFLASH.cmd.usr != 0) { + } + + SPIFLASH.ctrl.val = old_ctrl_reg; + return SPIFLASH.data_buf[0]; +} + +void bootloader_enable_wp(void) +{ + bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */ +} + +#if SOC_CACHE_SUPPORT_WRAP +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode) +{ + uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val; + uint32_t reg_bkp_usr = SPIFLASH.user.val; + SPIFLASH.user.fwrite_dio = 0; + SPIFLASH.user.fwrite_dual = 0; + SPIFLASH.user.fwrite_qio = 1; + SPIFLASH.user.fwrite_quad = 0; + SPIFLASH.ctrl.fcmd_dual = 0; + SPIFLASH.ctrl.fcmd_quad = 0; + SPIFLASH.user.usr_dummy = 0; + SPIFLASH.user.usr_addr = 1; + SPIFLASH.user.usr_command = 1; + SPIFLASH.user2.usr_command_bitlen = 7; + SPIFLASH.user2.usr_command_value = CMD_WRAP; + SPIFLASH.user1.usr_addr_bitlen = 23; + SPIFLASH.addr = 0; + SPIFLASH.user.usr_miso = 0; + SPIFLASH.user.usr_mosi = 1; + SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7; + SPIFLASH.data_buf[0] = (uint32_t) mode << 4;; + SPIFLASH.cmd.usr = 1; + while(SPIFLASH.cmd.usr != 0) + { } + + SPIFLASH.ctrl.val = reg_bkp_ctrl; + SPIFLASH.user.val = reg_bkp_usr; + return ESP_OK; +} +#endif //SOC_CACHE_SUPPORT_WRAP \ No newline at end of file diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index a324070c44..61501eed55 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -24,6 +24,7 @@ #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "bootloader_console.h" +#include "bootloader_flash.h" #include "soc/cpu.h" #include "soc/dport_reg.h" @@ -266,6 +267,8 @@ static esp_err_t bootloader_init_spi_flash(void) print_flash_info(&bootloader_image_hdr); update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); return ESP_OK; } diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 29f6d2f82b..882c656eec 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -27,6 +27,7 @@ #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "bootloader_console.h" +#include "bootloader_flash.h" #include "esp_rom_sys.h" #include "esp32s2/rom/cache.h" @@ -214,6 +215,8 @@ static esp_err_t bootloader_init_spi_flash(void) print_flash_info(&bootloader_image_hdr); update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); return ESP_OK; } diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c index 1fcf442f98..0dd3d41506 100644 --- a/components/bootloader_support/src/flash_qio_mode.c +++ b/components/bootloader_support/src/flash_qio_mode.c @@ -15,6 +15,7 @@ #include #include "bootloader_flash_config.h" #include "flash_qio_mode.h" +#include "bootloader_flash.h" #include "esp_log.h" #include "esp_err.h" #include "esp_rom_efuse.h" @@ -22,32 +23,13 @@ #include "esp32/rom/spi_flash.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/spi_flash.h" -#include "soc/spi_mem_struct.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/rom/spi_flash.h" #endif -#include "soc/spi_struct.h" -#include "soc/spi_reg.h" #include "soc/efuse_periph.h" #include "soc/io_mux_reg.h" #include "sdkconfig.h" -/* SPI flash controller */ -#if CONFIG_IDF_TARGET_ESP32 -#define SPIFLASH SPI1 -#elif CONFIG_IDF_TARGET_ESP32S2 -#define SPIFLASH SPIMEM1 -#endif - -/* SPI commands (actual on-wire commands not SPI controller bitmasks) - Suitable for use with the execute_flash_command static function. -*/ -#define CMD_RDID 0x9F -#define CMD_WRSR 0x01 -#define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ -#define CMD_WREN 0x06 -#define CMD_WRDI 0x04 -#define CMD_RDSR 0x05 -#define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ -#define CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ static const char *TAG = "qio_mode"; @@ -124,57 +106,15 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, The command passed here is always the on-the-wire command given to the SPI flash unit. */ -static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len); /* dummy_len_plus values defined in ROM for SPI flash configuration */ -extern uint8_t g_rom_spiflash_dummy_len_plus[]; uint32_t bootloader_read_flash_id(void) { - uint32_t id = execute_flash_command(CMD_RDID, 0, 0, 24); + uint32_t id = bootloader_execute_flash_command(CMD_RDID, 0, 0, 24); id = ((id & 0xff) << 16) | ((id >> 16) & 0xff) | (id & 0xff00); return id; } -#if CONFIG_IDF_TARGET_ESP32S2 -#define FLASH_WRAP_CMD 0x77 -typedef enum { - FLASH_WRAP_MODE_8B = 0, - FLASH_WRAP_MODE_16B = 2, - FLASH_WRAP_MODE_32B = 4, - FLASH_WRAP_MODE_64B = 6, - FLASH_WRAP_MODE_DISABLE = 1 -} spi_flash_wrap_mode_t; -static esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode) -{ - uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val; - uint32_t reg_bkp_usr = SPIFLASH.user.val; - SPIFLASH.user.fwrite_dio = 0; - SPIFLASH.user.fwrite_dual = 0; - SPIFLASH.user.fwrite_qio = 1; - SPIFLASH.user.fwrite_quad = 0; - SPIFLASH.ctrl.fcmd_dual = 0; - SPIFLASH.ctrl.fcmd_quad = 0; - SPIFLASH.user.usr_dummy = 0; - SPIFLASH.user.usr_addr = 1; - SPIFLASH.user.usr_command = 1; - SPIFLASH.user2.usr_command_bitlen = 7; - SPIFLASH.user2.usr_command_value = FLASH_WRAP_CMD; - SPIFLASH.user1.usr_addr_bitlen = 23; - SPIFLASH.addr = 0; - SPIFLASH.user.usr_miso = 0; - SPIFLASH.user.usr_mosi = 1; - SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7; - SPIFLASH.data_buf[0] = (uint32_t) mode << 4;; - SPIFLASH.cmd.usr = 1; - while (SPIFLASH.cmd.usr != 0) { - } - - SPIFLASH.ctrl.val = reg_bkp_ctrl; - SPIFLASH.user.val = reg_bkp_usr; - return ESP_OK; -} -#endif - void bootloader_enable_qio_mode(void) { uint32_t raw_flash_id; @@ -206,8 +146,8 @@ void bootloader_enable_qio_mode(void) enable_qio_mode(chip_data[i].read_status_fn, chip_data[i].write_status_fn, chip_data[i].status_qio_bit); -#if CONFIG_IDF_TARGET_ESP32S2 - spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); +#if SOC_CACHE_SUPPORT_WRAP + bootloader_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); #endif } @@ -224,7 +164,7 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, ESP_LOGD(TAG, "Initial flash chip status 0x%x", status); if ((status & (1 << status_qio_bit)) == 0) { - execute_flash_command(CMD_WREN, 0, 0, 0); + bootloader_execute_flash_command(CMD_WREN, 0, 0, 0); write_status_fn(status | (1 << status_qio_bit)); esp_rom_spiflash_wait_idle(&g_rom_flashchip); @@ -262,95 +202,48 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn, static unsigned read_status_8b_rdsr(void) { - return execute_flash_command(CMD_RDSR, 0, 0, 8); + return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8); } static unsigned read_status_8b_rdsr2(void) { - return execute_flash_command(CMD_RDSR2, 0, 0, 8); + return bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8); } static unsigned read_status_16b_rdsr_rdsr2(void) { - return execute_flash_command(CMD_RDSR, 0, 0, 8) | (execute_flash_command(CMD_RDSR2, 0, 0, 8) << 8); + return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8) | (bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8) << 8); } static void write_status_8b_wrsr(unsigned new_status) { - execute_flash_command(CMD_WRSR, new_status, 8, 0); + bootloader_execute_flash_command(CMD_WRSR, new_status, 8, 0); } static void write_status_8b_wrsr2(unsigned new_status) { - execute_flash_command(CMD_WRSR2, new_status, 8, 0); + bootloader_execute_flash_command(CMD_WRSR2, new_status, 8, 0); } static void write_status_16b_wrsr(unsigned new_status) { - execute_flash_command(CMD_WRSR, new_status, 16, 0); + bootloader_execute_flash_command(CMD_WRSR, new_status, 16, 0); } static unsigned read_status_8b_xmc25qu64a(void) { - execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ + bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ esp_rom_spiflash_wait_idle(&g_rom_flashchip); - uint32_t read_status = execute_flash_command(CMD_RDSR, 0, 0, 8); - execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */ + uint32_t read_status = bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8); + bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */ return read_status; } static void write_status_8b_xmc25qu64a(unsigned new_status) { - execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ + bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0); /* Enter OTP mode */ esp_rom_spiflash_wait_idle(&g_rom_flashchip); - execute_flash_command(CMD_WRSR, new_status, 8, 0); + bootloader_execute_flash_command(CMD_WRSR, new_status, 8, 0); esp_rom_spiflash_wait_idle(&g_rom_flashchip); - execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */ -} - -static uint32_t execute_flash_command(uint8_t command, uint32_t mosi_data, uint8_t mosi_len, uint8_t miso_len) -{ - uint32_t old_ctrl_reg = SPIFLASH.ctrl.val; -#if CONFIG_IDF_TARGET_ESP32 - SPIFLASH.ctrl.val = SPI_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode -#elif CONFIG_IDF_TARGET_ESP32S2 - SPIFLASH.ctrl.val = SPI_MEM_WP_REG_M; // keep WP high while idle, otherwise leave DIO mode -#endif - SPIFLASH.user.usr_dummy = 0; - SPIFLASH.user.usr_addr = 0; - SPIFLASH.user.usr_command = 1; - SPIFLASH.user2.usr_command_bitlen = 7; - - SPIFLASH.user2.usr_command_value = command; - SPIFLASH.user.usr_miso = miso_len > 0; -#if CONFIG_IDF_TARGET_ESP32 - SPIFLASH.miso_dlen.usr_miso_dbitlen = miso_len ? (miso_len - 1) : 0; -#elif CONFIG_IDF_TARGET_ESP32S2 - SPIFLASH.miso_dlen.usr_miso_bit_len = miso_len ? (miso_len - 1) : 0; -#endif - SPIFLASH.user.usr_mosi = mosi_len > 0; -#if CONFIG_IDF_TARGET_ESP32 - SPIFLASH.mosi_dlen.usr_mosi_dbitlen = mosi_len ? (mosi_len - 1) : 0; -#elif CONFIG_IDF_TARGET_ESP32S2 - SPIFLASH.mosi_dlen.usr_mosi_bit_len = mosi_len ? (mosi_len - 1) : 0; -#endif - SPIFLASH.data_buf[0] = mosi_data; - - if (g_rom_spiflash_dummy_len_plus[1]) { - /* When flash pins are mapped via GPIO matrix, need a dummy cycle before reading via MISO */ - if (miso_len > 0) { - SPIFLASH.user.usr_dummy = 1; - SPIFLASH.user1.usr_dummy_cyclelen = g_rom_spiflash_dummy_len_plus[1] - 1; - } else { - SPIFLASH.user.usr_dummy = 0; - SPIFLASH.user1.usr_dummy_cyclelen = 0; - } - } - - SPIFLASH.cmd.usr = 1; - while (SPIFLASH.cmd.usr != 0) { - } - - SPIFLASH.ctrl.val = old_ctrl_reg; - return SPIFLASH.data_buf[0]; + bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0); /* Exit OTP mode */ } diff --git a/components/esp_rom/include/esp32/rom/spi_flash.h b/components/esp_rom/include/esp32/rom/spi_flash.h index b78a6130aa..c71b810017 100644 --- a/components/esp_rom/include/esp32/rom/spi_flash.h +++ b/components/esp_rom/include/esp32/rom/spi_flash.h @@ -121,6 +121,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) //Extra dummy for flash read #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 diff --git a/components/esp_rom/include/esp32s2/rom/opi_flash.h b/components/esp_rom/include/esp32s2/rom/opi_flash.h index bb209f67f0..c985810b67 100644 --- a/components/esp_rom/include/esp32s2/rom/opi_flash.h +++ b/components/esp_rom/include/esp32s2/rom/opi_flash.h @@ -40,6 +40,7 @@ typedef struct { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_OP_MODE_RDCMD_DOUT 0x3B #define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 diff --git a/components/esp_rom/include/esp32s2/rom/spi_flash.h b/components/esp_rom/include/esp32s2/rom/spi_flash.h index 1eee20a5fa..2cf631666c 100644 --- a/components/esp_rom/include/esp32s2/rom/spi_flash.h +++ b/components/esp_rom/include/esp32s2/rom/spi_flash.h @@ -119,6 +119,7 @@ extern "C" { #define ESP_ROM_SPIFLASH_BP2 BIT4 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) #define ESP_ROM_SPIFLASH_QE BIT9 +#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) #define FLASH_ID_GD25LQ32C 0xC86016 diff --git a/components/soc/soc/esp32s2/include/soc/soc_caps.h b/components/soc/soc/esp32s2/include/soc/soc_caps.h index b0542b09b8..86e111db02 100644 --- a/components/soc/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/soc/esp32s2/include/soc/soc_caps.h @@ -11,3 +11,5 @@ #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_RISCV_COPROC_SUPPORTED 1 #define SOC_USB_SUPPORTED 1 + +#define SOC_CACHE_SUPPORT_WRAP 1 \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/soc_caps.h b/components/soc/soc/esp32s3/include/soc/soc_caps.h index 0c14285a18..de1b02ae73 100644 --- a/components/soc/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/soc/esp32s3/include/soc/soc_caps.h @@ -8,6 +8,7 @@ #define SOC_TWAI_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 #define SOC_CPU_CORES_NUM 2 +#define SOC_CACHE_SUPPORT_WRAP 1 // Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically // Remove them when GDMA driver API is ready diff --git a/components/spi_flash/CMakeLists.txt b/components/spi_flash/CMakeLists.txt index b123609940..406679bcef 100644 --- a/components/spi_flash/CMakeLists.txt +++ b/components/spi_flash/CMakeLists.txt @@ -1,5 +1,3 @@ -set(priv_requires bootloader_support soc) - if(BOOTLOADER_BUILD) if (CONFIG_IDF_TARGET_ESP32) # ESP32 Bootloader needs SPIUnlock from this file, but doesn't @@ -10,6 +8,7 @@ if(BOOTLOADER_BUILD) set(srcs) endif() set(cache_srcs "") + set(priv_requires bootloader_support soc) else() set(cache_srcs "cache_utils.c" diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index c1f6c93b3d..9f8b69d961 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -49,8 +49,9 @@ menu "SPI Flash driver" default y help Enable this flag to use patched versions of SPI flash ROM driver functions. - This option is needed to write to flash on ESP32-D2WD, and any configuration - where external SPI flash is connected to non-default pins. + This option should be enabled, if any one of the following is true: (1) need to write + to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main + SPI flash chip is manufactured by ISSI. choice SPI_FLASH_DANGEROUS_WRITE bool "Writing to dangerous flash regions" diff --git a/components/spi_flash/esp32/spi_flash_rom_patch.c b/components/spi_flash/esp32/spi_flash_rom_patch.c index 0c9be8db3c..d828452c84 100644 --- a/components/spi_flash/esp32/spi_flash_rom_patch.c +++ b/components/spi_flash/esp32/spi_flash_rom_patch.c @@ -19,8 +19,14 @@ #define SPI_IDX 1 #define OTH_IDX 0 + extern esp_rom_spiflash_chip_t g_rom_spiflash_chip; +static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip) +{ + return (((chip->device_id >> 16)&0xff) == 0x9D); +} + esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi) { uint32_t status; @@ -59,25 +65,43 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void) { uint32_t status; + uint32_t new_status; esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); - if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) { - return ESP_ROM_SPIFLASH_RESULT_ERR; - } + if (is_issi_chip(&g_rom_spiflash_chip)) { + // ISSI chips have different QE position - /* Clear all bits except QIE, if it is set. - (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.) - */ - status &= ESP_ROM_SPIFLASH_QE; + if (esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) { + return ESP_ROM_SPIFLASH_RESULT_ERR; + } + + /* Clear all bits in the mask. + (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.) + */ + new_status = status & (~ESP_ROM_SPIFLASH_BP_MASK_ISSI); + // Skip if nothing needs to be cleared. Otherwise will waste time waiting for the flash to clear nothing. + if (new_status == status) return ESP_ROM_SPIFLASH_RESULT_OK; + + CLEAR_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B); + } else { + if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) { + return ESP_ROM_SPIFLASH_RESULT_ERR; + } + + /* Clear all bits except QE, if it is set. + (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.) + */ + new_status = status & ESP_ROM_SPIFLASH_QE; + SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B); + } esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN); while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) { } esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip); - SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B); - if (esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status) != ESP_ROM_SPIFLASH_RESULT_OK) { + if (esp_rom_spiflash_write_status(&g_rom_spiflash_chip, new_status) != ESP_ROM_SPIFLASH_RESULT_OK) { return ESP_ROM_SPIFLASH_RESULT_ERR; } diff --git a/components/spi_flash/esp32s2/flash_ops_esp32s2.c b/components/spi_flash/esp32s2/flash_ops_esp32s2.c index 6cbe9b4fa0..c48e261d3f 100644 --- a/components/spi_flash/esp32s2/flash_ops_esp32s2.c +++ b/components/spi_flash/esp32s2/flash_ops_esp32s2.c @@ -20,6 +20,7 @@ #include "soc/soc_memory_layout.h" #include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/cache.h" +#include "bootloader_flash.h" #include "hal/spi_flash_hal.h" #include "esp_flash.h" #include "esp_log.h" @@ -76,48 +77,22 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a } } -#define FLASH_WRAP_CMD 0x77 esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode) { - uint32_t reg_bkp_ctrl = SPIFLASH.ctrl.val; - uint32_t reg_bkp_usr = SPIFLASH.user.val; - SPIFLASH.user.fwrite_dio = 0; - SPIFLASH.user.fwrite_dual = 0; - SPIFLASH.user.fwrite_qio = 1; - SPIFLASH.user.fwrite_quad = 0; - SPIFLASH.ctrl.fcmd_dual = 0; - SPIFLASH.ctrl.fcmd_quad = 0; - SPIFLASH.user.usr_dummy = 0; - SPIFLASH.user.usr_addr = 1; - SPIFLASH.user.usr_command = 1; - SPIFLASH.user2.usr_command_bitlen = 7; - SPIFLASH.user2.usr_command_value = FLASH_WRAP_CMD; - SPIFLASH.user1.usr_addr_bitlen = 23; - SPIFLASH.addr = 0; - SPIFLASH.user.usr_miso = 0; - SPIFLASH.user.usr_mosi = 1; - SPIFLASH.mosi_dlen.usr_mosi_bit_len = 7; - SPIFLASH.data_buf[0] = (uint32_t) mode << 4;; - SPIFLASH.cmd.usr = 1; - while(SPIFLASH.cmd.usr != 0) - { } - - SPIFLASH.ctrl.val = reg_bkp_ctrl; - SPIFLASH.user.val = reg_bkp_usr; - return ESP_OK; + return bootloader_flash_wrap_set(mode); } esp_err_t spi_flash_enable_wrap(uint32_t wrap_size) { switch(wrap_size) { case 8: - return spi_flash_wrap_set(FLASH_WRAP_MODE_8B); + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_8B); case 16: - return spi_flash_wrap_set(FLASH_WRAP_MODE_16B); + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_16B); case 32: - return spi_flash_wrap_set(FLASH_WRAP_MODE_32B); + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_32B); case 64: - return spi_flash_wrap_set(FLASH_WRAP_MODE_64B); + return bootloader_flash_wrap_set(FLASH_WRAP_MODE_64B); default: return ESP_FAIL; } @@ -125,7 +100,7 @@ esp_err_t spi_flash_enable_wrap(uint32_t wrap_size) void spi_flash_disable_wrap(void) { - spi_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); + bootloader_flash_wrap_set(FLASH_WRAP_MODE_DISABLE); } bool spi_flash_support_wrap_size(uint32_t wrap_size) diff --git a/components/spi_flash/flash_ops.c b/components/spi_flash/flash_ops.c index 4cabc92c0f..eb331b06bf 100644 --- a/components/spi_flash/flash_ops.c +++ b/components/spi_flash/flash_ops.c @@ -36,8 +36,6 @@ #include "esp32s2/rom/spi_flash.h" #include "esp32s2/rom/cache.h" #include "esp32s2/clk.h" -#include "soc/spi_mem_reg.h" -#include "soc/spi_mem_struct.h" #endif #include "esp_flash_partitions.h" #include "cache_utils.h" @@ -777,6 +775,7 @@ void spi_flash_dump_counters(void) #endif //CONFIG_SPI_FLASH_ENABLE_COUNTERS + #if defined(CONFIG_SPI_FLASH_USE_LEGACY_IMPL) && defined(CONFIG_IDF_TARGET_ESP32S2) // TODO esp32s2: Remove once ESP32S2 has new SPI Flash API support esp_flash_t *esp_flash_default_chip = NULL; From 3b2e8648eb0daa53b06c306bb9de169d26188c66 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Mon, 13 Jul 2020 03:23:12 +0800 Subject: [PATCH 2/2] bootloader: create public bootloader_flash.h header Move non-public functions into bootloader_flash_priv.h header --- components/app_update/test/test_switch_ota.c | 2 +- .../include/bootloader_flash.h | 30 +++++++++++++++++++ ...loader_flash.h => bootloader_flash_priv.h} | 11 +------ .../src/bootloader_common.c | 2 +- .../bootloader_support/src/bootloader_flash.c | 2 +- .../bootloader_support/src/bootloader_init.c | 2 +- .../src/bootloader_utility.c | 2 +- .../src/esp32/bootloader_esp32.c | 2 +- .../src/esp32/flash_encrypt.c | 2 +- .../src/esp32/secure_boot.c | 4 +-- .../src/esp32/secure_boot_signatures.c | 2 +- .../src/esp32s2/bootloader_esp32s2.c | 2 +- .../src/esp32s2/flash_encrypt.c | 6 ++-- .../src/esp32s2/secure_boot.c | 2 +- .../src/esp32s2/secure_boot_signatures.c | 2 +- .../bootloader_support/src/esp_image_format.c | 2 +- .../bootloader_support/src/flash_qio_mode.c | 2 +- .../src/idf/bootloader_sha.c | 2 +- .../src/idf/secure_boot_signatures.c | 4 +-- components/efuse/src/esp_efuse_fields.c | 2 +- 20 files changed, 53 insertions(+), 32 deletions(-) create mode 100644 components/bootloader_support/include/bootloader_flash.h rename components/bootloader_support/include_bootloader/{bootloader_flash.h => bootloader_flash_priv.h} (95%) diff --git a/components/app_update/test/test_switch_ota.c b/components/app_update/test/test_switch_ota.c index 5cbb8c0908..ec1847135a 100644 --- a/components/app_update/test/test_switch_ota.c +++ b/components/app_update/test/test_switch_ota.c @@ -23,7 +23,7 @@ #include "unity.h" #include "bootloader_common.h" -#include "../include_bootloader/bootloader_flash.h" +#include "../include_bootloader/bootloader_flash_priv.h" #include "esp_log.h" #include "esp_ota_ops.h" diff --git a/components/bootloader_support/include/bootloader_flash.h b/components/bootloader_support/include/bootloader_flash.h new file mode 100644 index 0000000000..5b74596544 --- /dev/null +++ b/components/bootloader_support/include/bootloader_flash.h @@ -0,0 +1,30 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include /* including in bootloader for error values */ +#include "sdkconfig.h" +#include "soc/soc_caps.h" + +#if SOC_CACHE_SUPPORT_WRAP +/** + * @brief Set the burst mode setting command for specified wrap mode. + * + * @param mode The specified warp mode. + * @return always ESP_OK + */ +esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); +#endif + diff --git a/components/bootloader_support/include_bootloader/bootloader_flash.h b/components/bootloader_support/include_bootloader/bootloader_flash_priv.h similarity index 95% rename from components/bootloader_support/include_bootloader/bootloader_flash.h rename to components/bootloader_support/include_bootloader/bootloader_flash_priv.h index e2e0f3ed65..45b7b06008 100644 --- a/components/bootloader_support/include_bootloader/bootloader_flash.h +++ b/components/bootloader_support/include_bootloader/bootloader_flash_priv.h @@ -20,6 +20,7 @@ #include #include /* including in bootloader for error values */ #include "sdkconfig.h" +#include "bootloader_flash.h" #define FLASH_SECTOR_SIZE 0x1000 #define FLASH_BLOCK_SIZE 0x10000 @@ -167,14 +168,4 @@ uint32_t bootloader_execute_flash_command(uint8_t command, uint32_t mosi_data, u */ void bootloader_enable_wp(void); -#if CONFIG_IDF_TARGET_ESP32S2 -/** - * @brief Set the burst mode setting command for specified wrap mode. - * - * @param mode The specified warp mode. - * @return always ESP_OK - */ -esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode); -#endif - #endif diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c index 09de9c246a..cc57d13273 100644 --- a/components/bootloader_support/src/bootloader_common.c +++ b/components/bootloader_support/src/bootloader_common.c @@ -26,7 +26,7 @@ #include "esp_rom_gpio.h" #include "esp_rom_sys.h" #include "esp_flash_partitions.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_common.h" #include "bootloader_utility.h" #include "soc/gpio_periph.h" diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index 6716e3bc53..d91c1cb4f3 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -13,7 +13,7 @@ // limitations under the License. #include -#include +#include #include #include #include "sdkconfig.h" diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index 8938dc7571..d662f2d32c 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -17,7 +17,7 @@ #include "esp_attr.h" #include "esp_log.h" #include "bootloader_init.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_flash_config.h" #include "bootloader_random.h" #include "bootloader_clock.h" diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 965fd0d12c..6c4662695e 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -51,7 +51,7 @@ #include "esp_secure_boot.h" #include "esp_flash_encrypt.h" #include "esp_flash_partitions.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_random.h" #include "bootloader_config.h" #include "bootloader_common.h" diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index 61501eed55..4bd3d04680 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -24,7 +24,7 @@ #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "bootloader_console.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "soc/cpu.h" #include "soc/dport_reg.h" diff --git a/components/bootloader_support/src/esp32/flash_encrypt.c b/components/bootloader_support/src/esp32/flash_encrypt.c index 6212228701..0a75ae6cf3 100644 --- a/components/bootloader_support/src/esp32/flash_encrypt.c +++ b/components/bootloader_support/src/esp32/flash_encrypt.c @@ -14,7 +14,7 @@ #include -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "esp_image_format.h" #include "esp_flash_encrypt.h" #include "esp_flash_partitions.h" diff --git a/components/bootloader_support/src/esp32/secure_boot.c b/components/bootloader_support/src/esp32/secure_boot.c index e54e65b6c0..99d7ebe024 100644 --- a/components/bootloader_support/src/esp32/secure_boot.c +++ b/components/bootloader_support/src/esp32/secure_boot.c @@ -28,7 +28,7 @@ #include "sdkconfig.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_random.h" #include "esp_image_format.h" #include "esp_secure_boot.h" @@ -322,7 +322,7 @@ esp_err_t esp_secure_boot_v2_permanently_enable(const esp_image_metadata_t *imag uint32_t dis_reg = REG_READ(EFUSE_BLK0_RDATA0_REG); bool efuse_key_read_protected = dis_reg & EFUSE_RD_DIS_BLK2; bool efuse_key_write_protected = dis_reg & EFUSE_WR_DIS_BLK2; - if (efuse_key_write_protected == false + if (efuse_key_write_protected == false && efuse_key_read_protected == false && REG_READ(EFUSE_BLK2_RDATA0_REG) == 0 && REG_READ(EFUSE_BLK2_RDATA1_REG) == 0 diff --git a/components/bootloader_support/src/esp32/secure_boot_signatures.c b/components/bootloader_support/src/esp32/secure_boot_signatures.c index 1ff4999b85..e38e98201b 100644 --- a/components/bootloader_support/src/esp32/secure_boot_signatures.c +++ b/components/bootloader_support/src/esp32/secure_boot_signatures.c @@ -13,7 +13,7 @@ // limitations under the License. #include "sdkconfig.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_sha.h" #include "bootloader_utility.h" #include "esp_log.h" diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 882c656eec..47c1a18020 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -27,7 +27,7 @@ #include "bootloader_flash_config.h" #include "bootloader_mem.h" #include "bootloader_console.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "esp_rom_sys.h" #include "esp32s2/rom/cache.h" diff --git a/components/bootloader_support/src/esp32s2/flash_encrypt.c b/components/bootloader_support/src/esp32s2/flash_encrypt.c index 9d9acf754f..017c42d8c0 100644 --- a/components/bootloader_support/src/esp32s2/flash_encrypt.c +++ b/components/bootloader_support/src/esp32s2/flash_encrypt.c @@ -14,7 +14,7 @@ #include -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_random.h" #include "bootloader_utility.h" #include "esp_image_format.h" @@ -299,8 +299,8 @@ static esp_err_t encrypt_bootloader(void) if (err != ESP_OK) { ESP_LOGE(TAG, "Failed to encrypt bootloader in place: 0x%x", err); return err; - } - + } + ESP_LOGI(TAG, "bootloader encrypted successfully"); return err; } diff --git a/components/bootloader_support/src/esp32s2/secure_boot.c b/components/bootloader_support/src/esp32s2/secure_boot.c index e5dd3b93b4..7a8ac94f6a 100644 --- a/components/bootloader_support/src/esp32s2/secure_boot.c +++ b/components/bootloader_support/src/esp32s2/secure_boot.c @@ -17,7 +17,7 @@ #include "esp_secure_boot.h" #include "soc/efuse_reg.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_sha.h" #include "bootloader_utility.h" diff --git a/components/bootloader_support/src/esp32s2/secure_boot_signatures.c b/components/bootloader_support/src/esp32s2/secure_boot_signatures.c index e60fcacaf1..3da88b262c 100644 --- a/components/bootloader_support/src/esp32s2/secure_boot_signatures.c +++ b/components/bootloader_support/src/esp32s2/secure_boot_signatures.c @@ -15,7 +15,7 @@ #include #include "esp_fault.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_sha.h" #include "bootloader_utility.h" #include "esp_log.h" diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index 2d02329019..eb03a2e581 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include "bootloader_util.h" diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c index 0dd3d41506..f142f7c284 100644 --- a/components/bootloader_support/src/flash_qio_mode.c +++ b/components/bootloader_support/src/flash_qio_mode.c @@ -15,7 +15,7 @@ #include #include "bootloader_flash_config.h" #include "flash_qio_mode.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "esp_log.h" #include "esp_err.h" #include "esp_rom_efuse.h" diff --git a/components/bootloader_support/src/idf/bootloader_sha.c b/components/bootloader_support/src/idf/bootloader_sha.c index 8d70406c72..40308b667f 100644 --- a/components/bootloader_support/src/idf/bootloader_sha.c +++ b/components/bootloader_support/src/idf/bootloader_sha.c @@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. #include "bootloader_sha.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include #include #include diff --git a/components/bootloader_support/src/idf/secure_boot_signatures.c b/components/bootloader_support/src/idf/secure_boot_signatures.c index 8f7acb9ea7..fd7017424a 100644 --- a/components/bootloader_support/src/idf/secure_boot_signatures.c +++ b/components/bootloader_support/src/idf/secure_boot_signatures.c @@ -13,7 +13,7 @@ // limitations under the License. #include "sdkconfig.h" -#include "bootloader_flash.h" +#include "bootloader_flash_priv.h" #include "bootloader_sha.h" #include "bootloader_utility.h" #include "esp_log.h" @@ -325,7 +325,7 @@ esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signa break; } } - + free(sig_be); free(buf); #if CONFIG_IDF_TARGET_ESP32 diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index 54d577a0ed..5cc8bc75fc 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -41,7 +41,7 @@ void esp_efuse_reset(void) #ifdef CONFIG_BOOTLOADER_EFUSE_SECURE_VERSION_EMULATE -#include "../include_bootloader/bootloader_flash.h" +#include "../include_bootloader/bootloader_flash_priv.h" #include "esp_flash_encrypt.h" static uint32_t esp_efuse_flash_offset = 0;