mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
fix(flash_mmap): fixed limited free I/D pages on ESP32S3, C2, C3
This commit is contained in:
Armando
parent
61ef154a60
commit
6183b555aa
@ -45,6 +45,10 @@ if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
|
||||
list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
|
||||
endif()
|
||||
|
||||
if(CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE)
|
||||
list(APPEND sources "patches/esp_rom_mmap.c")
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS ${sources}
|
||||
INCLUDE_DIRS ${include_dirs}
|
||||
PRIV_REQUIRES ${private_required_comp}
|
||||
|
||||
@ -42,3 +42,7 @@ config ESP_ROM_HAS_HEAP_TLSF
|
||||
config ESP_ROM_TLSF_CHECK_PATCH
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -16,3 +16,4 @@
|
||||
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
|
||||
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
|
||||
#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check()
|
||||
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
|
||||
|
||||
@ -46,3 +46,7 @@ config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
|
||||
config ESP_ROM_HAS_ETS_PRINTF_BUG
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -17,3 +17,4 @@
|
||||
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
|
||||
#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
|
||||
#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
|
||||
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
|
||||
|
||||
@ -42,3 +42,7 @@ config ESP_ROM_GET_CLK_FREQ
|
||||
config ESP_ROM_HAS_ETS_PRINTF_BUG
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -16,3 +16,4 @@
|
||||
#define ESP_ROM_HAS_ERASE_0_REGION_BUG (1) // ROM has esp_flash_erase_region(size=0) bug
|
||||
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
|
||||
#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
|
||||
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
|
||||
|
||||
@ -66,3 +66,7 @@ config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
|
||||
config ESP_ROM_HAS_CACHE_WRITEBACK_BUG
|
||||
bool
|
||||
default y
|
||||
|
||||
config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -22,3 +22,4 @@
|
||||
#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
|
||||
#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti
|
||||
#define ESP_ROM_HAS_CACHE_WRITEBACK_BUG (1) // ROM api Cache_WriteBack_Addr access cacheline being writen back may cause cache hit with wrong value.
|
||||
#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
|
||||
|
||||
@ -11,3 +11,5 @@ entries:
|
||||
esp_rom_tlsf (noflash)
|
||||
if SOC_SYSTIMER_SUPPORTED = y:
|
||||
esp_rom_systimer (noflash)
|
||||
if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE = y:
|
||||
esp_rom_mmap (noflash)
|
||||
|
||||
36
components/esp_rom/patches/esp_rom_mmap.c
Normal file
36
components/esp_rom/patches/esp_rom_mmap.c
Normal file
@ -0,0 +1,36 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/ext_mem_defs.h"
|
||||
|
||||
|
||||
uint32_t Cache_Get_IROM_MMU_End(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
return 0x800;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
return 0x200;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
return 0x100;
|
||||
#else
|
||||
assert(false);
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t Cache_Get_DROM_MMU_End(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32S3
|
||||
return 0x800;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
|
||||
return 0x200;
|
||||
#elif CONFIG_IDF_TARGET_ESP32C2
|
||||
return 0x100;
|
||||
#else
|
||||
assert(false);
|
||||
#endif
|
||||
}
|
||||
@ -51,7 +51,7 @@ extern "C" {
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_START 0
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
|
||||
@ -49,7 +49,7 @@ extern "C" {
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_START 0
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
|
||||
@ -49,7 +49,7 @@ extern "C" {
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_START 0
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
|
||||
@ -22,6 +22,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM)
|
||||
#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START)
|
||||
#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW
|
||||
|
||||
@ -48,7 +48,7 @@ extern "C" {
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_START 0
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
|
||||
@ -22,6 +22,7 @@ extern "C" {
|
||||
#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t))
|
||||
#define SOC_MMU_ADDR_MASK MMU_VALID_VAL_MASK
|
||||
#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH)
|
||||
#define SOC_MMU_PAGE_IN_PSRAM(page) ((page) | MMU_ACCESS_SPIRAM)
|
||||
#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW
|
||||
#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START
|
||||
#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
|
||||
|
||||
@ -198,6 +198,13 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
|
||||
for (pos = start; pos < start + page_count; ++pos, ++pageno) {
|
||||
int table_val = (int) mmu_ll_read_entry(MMU_TABLE_CORE0, pos);
|
||||
uint8_t refcnt = s_mmap_page_refcnt[pos];
|
||||
|
||||
#if !CONFIG_IDF_TARGET_ESP32 && SOC_SPIRAM_SUPPORTED
|
||||
if (table_val == SOC_MMU_PAGE_IN_PSRAM(pages[pageno])) {
|
||||
break;
|
||||
}
|
||||
#endif //#if !CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
if (refcnt != 0 && table_val != SOC_MMU_PAGE_IN_FLASH(pages[pageno])) {
|
||||
break;
|
||||
}
|
||||
@ -219,6 +226,12 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp
|
||||
#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
|
||||
uint32_t entry_app = mmu_ll_read_entry(MMU_TABLE_CORE1, i);
|
||||
#endif
|
||||
if (s_mmap_page_refcnt[i] == 0) {
|
||||
assert(mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE0, i));
|
||||
#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
|
||||
assert(mmu_ll_get_entry_is_invalid(MMU_TABLE_CORE1, i));
|
||||
#endif
|
||||
}
|
||||
assert(s_mmap_page_refcnt[i] == 0 ||
|
||||
(entry_pro == SOC_MMU_PAGE_IN_FLASH(pages[pageno])
|
||||
#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32
|
||||
|
||||
Loading…
Reference in New Issue
Block a user