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fix(ulp): write output mode to the correct register

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Fixes register mixup. According to the ESP32-S3 TRM (pages 515-516), the output pin's mode is set in the RTC_GPIO_PINn_REG, bit RTC_GPIO_PINn_PAD_DRIVER not the RTC_IO_TOUCH_PADn_REG field RTC_IO_TOUCH_PADn_DRV, which instead controls the drive output strength.
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LonerDan 2024-06-18 12:49:43 +02:00 committed by GitHub
parent 0479494e7a
commit 6169404f1f
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GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 1 deletions
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components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h
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@ -109,7 +109,7 @@ static inline uint8_t ulp_riscv_gpio_get_level(gpio_num_t gpio_num)
static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode)
{ {
REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_DRV, mode); REG_SET_FIELD(RTC_GPIO_PIN0_REG + gpio_num * 4, RTC_GPIO_PIN0_PAD_DRIVER, mode);
} }
static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num)