From 0e74ec67be0b7e6c08f65bb0dd838291a113a168 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Mon, 4 Sep 2017 19:00:47 +0800 Subject: [PATCH] Fix rebooting when PSRAM is active --- components/esp32/system_api.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index d88b1a1d03..82010595e3 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -24,6 +24,7 @@ #include "rom/cache.h" #include "rom/uart.h" #include "soc/dport_reg.h" +#include "soc/gpio_reg.h" #include "soc/efuse_reg.h" #include "soc/rtc_cntl_reg.h" #include "soc/timer_group_reg.h" @@ -298,6 +299,17 @@ void IRAM_ATTR esp_restart_noos() Cache_Read_Disable(0); Cache_Read_Disable(1); +#ifdef CONFIG_SPIRAM_SUPPORT + //External SPI RAM reconfigures some GPIO functions in a way that is not entirely undone in the boot rom. + //Undo them manually so we reboot correctly. + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); +#endif + // Flush any data left in UART FIFOs uart_tx_wait_idle(0); uart_tx_wait_idle(1);