From 5f550b2a134f7eec33271e7a8cacaf93e219e6ce Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 13 Sep 2022 15:54:05 +0800 Subject: [PATCH] rmt,gptimer: don't support rc_fast clock source for c6 and h2 The RC_FAST clock source on ESP32C6 and ESP32H2 can't be calibrated. Which makes it impossible to work stable for peripherals like timer, RMT --- components/driver/gptimer.c | 13 ------------- components/hal/esp32h2/include/hal/rmt_ll.h | 6 ------ .../soc/esp32c6/include/soc/Kconfig.soc_caps.in | 8 -------- components/soc/esp32c6/include/soc/clk_tree_defs.h | 3 +-- components/soc/esp32c6/include/soc/soc_caps.h | 2 -- .../soc/esp32h2/include/soc/Kconfig.soc_caps.in | 4 ---- components/soc/esp32h2/include/soc/clk_tree_defs.h | 3 +-- components/soc/esp32h2/include/soc/soc_caps.h | 1 - 8 files changed, 2 insertions(+), 38 deletions(-) diff --git a/components/driver/gptimer.c b/components/driver/gptimer.c index 358d2e7d9a..a278ee3888 100644 --- a/components/driver/gptimer.c +++ b/components/driver/gptimer.c @@ -214,12 +214,6 @@ esp_err_t gptimer_del_timer(gptimer_handle_t timer) int timer_id = timer->timer_id; ESP_LOGD(TAG, "del timer (%d,%d)", group_id, timer_id); timer_hal_deinit(&timer->hal); - // [refactor-todo]: replace the following code with clk_tree_acquire/release, and call them in gptimer_enable/disable -#if SOC_TIMER_GROUP_SUPPORT_RC_FAST - if (timer->clk_src == GPTIMER_CLK_SRC_RC_FAST) { - periph_rtc_dig_clk8m_disable(); - } -#endif // recycle memory resource ESP_RETURN_ON_ERROR(gptimer_destory(timer), TAG, "destory gptimer failed"); return ESP_OK; @@ -475,13 +469,6 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou counter_src_hz = esp_clk_xtal_freq(); break; #endif // SOC_TIMER_GROUP_SUPPORT_XTAL -#if SOC_TIMER_GROUP_SUPPORT_RC_FAST - case GPTIMER_CLK_SRC_RC_FAST: - // periph_rtc_dig_clk8m_enable must be called before periph_rtc_dig_clk8m_get_freq, to ensure a calibration is done - periph_rtc_dig_clk8m_enable(); - periph_src_clk_hz = periph_rtc_dig_clk8m_get_freq(); - break; -#endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST default: ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "clock source %d is not support", src_clk); break; diff --git a/components/hal/esp32h2/include/hal/rmt_ll.h b/components/hal/esp32h2/include/hal/rmt_ll.h index 5e9a3f38e0..5d18929689 100644 --- a/components/hal/esp32h2/include/hal/rmt_ll.h +++ b/components/hal/esp32h2/include/hal/rmt_ll.h @@ -98,9 +98,6 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, case RMT_CLK_SRC_AHB: dev->sys_conf.sclk_sel = 1; break; - case RMT_CLK_SRC_RC_FAST: - dev->sys_conf.sclk_sel = 2; - break; case RMT_CLK_SRC_XTAL: dev->sys_conf.sclk_sel = 3; break; @@ -742,9 +739,6 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint case 1: clk_src = RMT_CLK_SRC_AHB; break; - case 2: - clk_src = RMT_CLK_SRC_RC_FAST; - break; case 3: clk_src = RMT_CLK_SRC_XTAL; break; diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index c654e5472c..e0f924e5ba 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -419,10 +419,6 @@ config SOC_RMT_SUPPORT_APB bool default y -config SOC_RMT_SUPPORT_RC_FAST - bool - default y - config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH int default 128 @@ -603,10 +599,6 @@ config SOC_TIMER_GROUP_SUPPORT_APB bool default y -config SOC_TIMER_GROUP_SUPPORT_RC_FAST - bool - default y - config SOC_TIMER_GROUP_TOTAL_TIMERS int default 2 diff --git a/components/soc/esp32c6/include/soc/clk_tree_defs.h b/components/soc/esp32c6/include/soc/clk_tree_defs.h index 737c140943..07e8e9b0c5 100644 --- a/components/soc/esp32c6/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c6/include/soc/clk_tree_defs.h @@ -131,7 +131,7 @@ typedef enum { #if CONFIG_IDF_ENV_FPGA #define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL} #else -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL} #endif /** @@ -140,7 +140,6 @@ typedef enum { typedef enum { GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */ GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ #if CONFIG_IDF_ENV_FPGA GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */ #else diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 46836c604f..a68587ac8c 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -229,7 +229,6 @@ #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ #define SOC_RMT_SUPPORT_APB 1 /*!< Support set APB as the RMT clock source */ -#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */ // TODO: IDF-5348 (Copy from esp32c3, need check) /*-------------------------- RTC CAPS --------------------------------------*/ @@ -328,7 +327,6 @@ #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) #define SOC_TIMER_GROUP_SUPPORT_APB (1) -#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) #define SOC_TIMER_SUPPORT_ETM (1) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 00ba06cf98..f1c61bf610 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -451,10 +451,6 @@ config SOC_RMT_SUPPORT_AHB bool default y -config SOC_RMT_SUPPORT_RC_FAST - bool - default y - config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH int default 128 diff --git a/components/soc/esp32h2/include/soc/clk_tree_defs.h b/components/soc/esp32h2/include/soc/clk_tree_defs.h index 1b19e0c78f..9b8afbcb92 100644 --- a/components/soc/esp32h2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32h2/include/soc/clk_tree_defs.h @@ -158,14 +158,13 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of RMT */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL} /** * @brief Type of RMT clock source */ typedef enum { RMT_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB clock as the source clock */ - RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */ } soc_periph_rmt_clk_src_t; diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 41348c93f8..6980f32fcb 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -218,7 +218,6 @@ #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ #define SOC_RMT_SUPPORT_AHB 1 /*!< Support set AHB clock as the RMT clock source */ -#define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST clock as the RMT clock source */ /*-------------------------- RTC CAPS --------------------------------------*/ #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)