From 5f2fabb2b15264467ce77951d257727ad0b658b8 Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Fri, 19 Feb 2021 21:41:26 +0800 Subject: [PATCH] arch: move stdatomic --- components/newlib/CMakeLists.txt | 1 + components/newlib/newlib.lf | 1 + components/{xtensa => newlib}/stdatomic.c | 87 ++++++++++------------- components/riscv/CMakeLists.txt | 1 - components/riscv/linker.lf | 1 - components/xtensa/CMakeLists.txt | 3 - components/xtensa/linker.lf | 2 - 7 files changed, 38 insertions(+), 58 deletions(-) rename components/{xtensa => newlib}/stdatomic.c (64%) diff --git a/components/newlib/CMakeLists.txt b/components/newlib/CMakeLists.txt index 077db45299..ba4c124b9b 100644 --- a/components/newlib/CMakeLists.txt +++ b/components/newlib/CMakeLists.txt @@ -16,6 +16,7 @@ set(srcs "newlib_init.c" "syscalls.c" "termios.c" + "stdatomic.c" "time.c") set(include_dirs platform_include) diff --git a/components/newlib/newlib.lf b/components/newlib/newlib.lf index 5f1c382f8d..d92c04fb0f 100644 --- a/components/newlib/newlib.lf +++ b/components/newlib/newlib.lf @@ -4,3 +4,4 @@ entries: heap (noflash) abort (noflash) assert (noflash) + stdatomic (noflash) diff --git a/components/xtensa/stdatomic.c b/components/newlib/stdatomic.c similarity index 64% rename from components/xtensa/stdatomic.c rename to components/newlib/stdatomic.c index 4dc425c502..23e34c6951 100644 --- a/components/xtensa/stdatomic.c +++ b/components/newlib/stdatomic.c @@ -16,13 +16,13 @@ #include "sdkconfig.h" #include +#include + +#ifdef __XTENSA__ + #include "xtensa/config/core-isa.h" #include "xtensa/xtruntime.h" -//reserved to measure atomic operation time -#define atomic_benchmark_intr_disable() -#define atomic_benchmark_intr_restore(STATE) - // This allows nested interrupts disabling and restoring via local registers or stack. // They can be called from interrupts too. // WARNING: Only applies to current CPU. @@ -37,14 +37,37 @@ XTOS_RESTORE_JUST_INTLEVEL(state); \ } while (0) -#define ATOMIC_EXCHANGE(n, type) type __atomic_exchange_ ## n (type* mem, type val, int memorder) \ -{ \ - unsigned state = _ATOMIC_ENTER_CRITICAL(); \ - type ret = *mem; \ - *mem = val; \ - _ATOMIC_EXIT_CRITICAL(state); \ - return ret; \ -} +#ifndef XCHAL_HAVE_S32C1I +#error "XCHAL_HAVE_S32C1I not defined, include correct header!" +#endif + +#define NO_ATOMICS_SUPPORT (XCHAL_HAVE_S32C1I == 0) +#else // RISCV + +#include "freertos/portmacro.h" + +// This allows nested interrupts disabling and restoring via local registers or stack. +// They can be called from interrupts too. +// WARNING: Only applies to current CPU. +#define _ATOMIC_ENTER_CRITICAL(void) ({ \ + unsigned state = portENTER_CRITICAL_NESTED(); \ + atomic_benchmark_intr_disable(); \ + state; \ +}) + +#define _ATOMIC_EXIT_CRITICAL(state) do { \ + atomic_benchmark_intr_restore(state); \ + portEXIT_CRITICAL_NESTED(state); \ + } while (0) + +#define NO_ATOMICS_SUPPORT 1 // [todo] Get the equivalent XCHAL_HAVE_S32C1I check for RISCV + +#endif + + +//reserved to measure atomic operation time +#define atomic_benchmark_intr_disable() +#define atomic_benchmark_intr_restore(STATE) #define CMP_EXCHANGE(n, type) bool __atomic_compare_exchange_ ## n (type* mem, type* expect, type desired, int success, int failure) \ { \ @@ -105,47 +128,9 @@ return ret; \ } -#define SYNC_FETCH_OP(op, n, type) type __sync_fetch_and_ ## op ##_ ## n (type* ptr, type value, ...) \ -{ \ - return __atomic_fetch_ ## op ##_ ## n (ptr, value, __ATOMIC_SEQ_CST); \ -} - -#define SYNC_BOOL_CMP_EXCHANGE(n, type) bool __sync_bool_compare_and_swap_ ## n (type *ptr, type oldval, type newval, ...) \ -{ \ - bool ret = false; \ - unsigned state = _ATOMIC_ENTER_CRITICAL(); \ - if (*ptr == oldval) { \ - *ptr = newval; \ - ret = true; \ - } \ - _ATOMIC_EXIT_CRITICAL(state); \ - return ret; \ -} - -#define SYNC_VAL_CMP_EXCHANGE(n, type) type __sync_val_compare_and_swap_ ## n (type *ptr, type oldval, type newval, ...) \ -{ \ - unsigned state = _ATOMIC_ENTER_CRITICAL(); \ - type ret = *ptr; \ - if (*ptr == oldval) { \ - *ptr = newval; \ - } \ - _ATOMIC_EXIT_CRITICAL(state); \ - return ret; \ -} - -#ifndef XCHAL_HAVE_S32C1I -#error "XCHAL_HAVE_S32C1I not defined, include correct header!" -#endif - -//this piece of code should only be compiled if the cpu doesn't support atomic compare and swap (s32c1i) -#if XCHAL_HAVE_S32C1I == 0 - #pragma GCC diagnostic ignored "-Wbuiltin-declaration-mismatch" -ATOMIC_EXCHANGE(1, uint8_t) -ATOMIC_EXCHANGE(2, uint16_t) -ATOMIC_EXCHANGE(4, uint32_t) -ATOMIC_EXCHANGE(8, uint64_t) +#if NO_ATOMICS_SUPPORT CMP_EXCHANGE(1, uint8_t) CMP_EXCHANGE(2, uint16_t) diff --git a/components/riscv/CMakeLists.txt b/components/riscv/CMakeLists.txt index 0290ca9937..efc891b19e 100644 --- a/components/riscv/CMakeLists.txt +++ b/components/riscv/CMakeLists.txt @@ -11,7 +11,6 @@ else() "expression_with_stack_riscv_asm.S" "instruction_decode.c" "interrupt.c" - "stdatomic.c" "vectors.S") endif() diff --git a/components/riscv/linker.lf b/components/riscv/linker.lf index 2e5681238c..cfcb303cf0 100644 --- a/components/riscv/linker.lf +++ b/components/riscv/linker.lf @@ -3,4 +3,3 @@ archive: libriscv.a entries: interrupt (noflash_text) vectors (noflash_text) - stdatomic (noflash_text) diff --git a/components/xtensa/CMakeLists.txt b/components/xtensa/CMakeLists.txt index 3fa959a936..1511fb5d5a 100644 --- a/components/xtensa/CMakeLists.txt +++ b/components/xtensa/CMakeLists.txt @@ -18,9 +18,6 @@ else() "${target}/trax_init.c" ) - if(IDF_TARGET STREQUAL "esp32s2") - list(APPEND srcs "stdatomic.c") - endif() endif() idf_component_register(SRCS ${srcs} diff --git a/components/xtensa/linker.lf b/components/xtensa/linker.lf index 148116f1a1..5227ce02df 100644 --- a/components/xtensa/linker.lf +++ b/components/xtensa/linker.lf @@ -3,8 +3,6 @@ archive: libxtensa.a entries: eri (noflash_text) xtensa_intr_asm (noflash_text) - if IDF_TARGET_ESP32S2 = y: - stdatomic (noflash) [mapping:xt_hal] archive: libxt_hal.a