Merge branch 'fix/support_esp32c5_rom_flash_mmap' into 'master'

fix(esp_rom): support esp32c5 rom flash mmap

See merge request espressif/esp-idf!31736

components/esp_rom/esp32c5/Kconfig.soc_caps.in

@@ -79,6 +79,10 @@ config ESP_ROM_WDT_INIT_PATCH
     bool
     default y
 
+config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
+    bool
+    default y
+
 config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
     bool
     default y

components/esp_rom/esp32c5/esp_rom_caps.h

@@ -25,6 +25,7 @@
 #define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
 #define ESP_ROM_HAS_NEWLIB_NORMAL_FORMAT    (1) // ROM has the newlib normal/full version of formatting functions (as opposed to the nano versions)
 #define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
+#define ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE    (1) // ROM needs to set cache MMU size according to instruction and rodata for flash mmap
 #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
 #define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
 #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB  (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep.

components/soc/esp32c5/include/soc/mmu.h

@@ -0,0 +1,33 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/ext_mem_defs.h"
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined for flash mmap */
+#define SOC_MMU_REGIONS_COUNT                   1
+#define SOC_MMU_PAGES_PER_REGION                256
+#define SOC_MMU_IROM0_PAGES_START               (CACHE_IROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_IROM0_PAGES_END                 (CACHE_IROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
+#define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
+#define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
+#define SOC_MMU_ADDR_MASK                       (SOC_MMU_VALID - 1)
+#define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
+#define SOC_MMU_VADDR1_START_ADDR               SOC_IRAM0_CACHE_ADDRESS_LOW
+#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE     SOC_MMU_IROM0_PAGES_START
+#define SOC_MMU_VADDR0_START_ADDR               (SOC_IROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE))
+#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR        SOC_IROM_LOW
+
+#ifdef __cplusplus
+}
+#endif