diff --git a/components/esp_hw_support/sleep_console.c b/components/esp_hw_support/sleep_console.c
index 02a0f5bb27..c613540fff 100644
--- a/components/esp_hw_support/sleep_console.c
+++ b/components/esp_hw_support/sleep_console.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,7 +27,8 @@ void sleep_console_usj_pad_backup_and_disable(void)
         usb_serial_jtag_ll_enable_bus_clock(true);
         usb_serial_jtag_ll_reset_register();
     }
-    s_usj_state.usj_pad_enabled = usb_serial_jtag_ll_pad_backup_and_disable();
+    s_usj_state.usj_pad_enabled = usb_serial_jtag_ll_phy_is_pad_enabled();
+    usb_serial_jtag_ll_phy_enable_pad(false);
     // Disable USJ clock
     usb_serial_jtag_ll_enable_bus_clock(false);
 }
@@ -40,7 +41,7 @@ void sleep_console_usj_pad_restore(void)
     int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
 
     usb_serial_jtag_ll_enable_bus_clock(true);
-    usb_serial_jtag_ll_enable_pad(s_usj_state.usj_pad_enabled);
+    usb_serial_jtag_ll_phy_enable_pad(s_usj_state.usj_pad_enabled);
     if (!s_usj_state.usj_clock_enabled) {
         usb_serial_jtag_ll_enable_bus_clock(false);
     }
diff --git a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
index cdd78144bd..a706cee908 100644
--- a/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,8 @@ typedef enum {
     USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
 } usb_serial_jtag_ll_intr_t;
 
+/* ----------------------------- USJ Peripheral ----------------------------- */
+
 /**
  * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
  *
@@ -177,31 +179,112 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
     USB_SERIAL_JTAG.ep1_conf.wr_done=1;
 }
 
+/* ---------------------------- USB PHY Control  ---------------------------- */
+
 /**
- * @brief Disable usb serial jtag pad during light sleep to avoid current leakage
+ * @brief Sets whether the USJ's FSLS PHY interface routes to an internal or external PHY
  *
- * @return Initial configuration of usb serial jtag pad enable before light sleep
+ * @param enable Enables external PHY, internal otherwise
  */
-FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_external(bool enable)
 {
-    bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
-
-    // Disable USB pad function
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
-
-    return pad_enabled;
+    USB_SERIAL_JTAG.conf0.phy_sel = enable;
 }
 
 /**
- * @brief Enable the internal USJ PHY control to D+/D- pad
+ * @brief Enables/disables exchanging of the D+/D- pins USB PHY
  *
- * @param enable_pad Enable the USJ PHY control to D+/D- pad
+ * @param enable Enables pin exchange, disabled otherwise
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
 {
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
+    if (enable) {
+        USB_SERIAL_JTAG.conf0.exchg_pins = 1;
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
+    } else {
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
+        USB_SERIAL_JTAG.conf0.exchg_pins = 0;
+    }
 }
 
+/**
+ * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
+ *
+ * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
+ * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
+{
+    USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
+    USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
+    USB_SERIAL_JTAG.conf0.vref_override = 1;
+}
+
+/**
+ * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
+{
+    USB_SERIAL_JTAG.conf0.vref_override = 0;
+}
+
+/**
+ * @brief Enable override of USB FSLS PHY's pull up/down resistors
+ *
+ * @param dp_pu Enable D+ pullup
+ * @param dm_pu Enable D- pullup
+ * @param dp_pd Enable D+ pulldown
+ * @param dm_pd Enable D- pulldown
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
+{
+    USB_SERIAL_JTAG.conf0.dp_pullup = dp_pu;
+    USB_SERIAL_JTAG.conf0.dp_pulldown = dp_pd;
+    USB_SERIAL_JTAG.conf0.dm_pullup = dm_pu;
+    USB_SERIAL_JTAG.conf0.dm_pulldown = dm_pd;
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
+}
+
+/**
+ * @brief Disable override of USB FSLS PHY pull up/down resistors
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
+{
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
+}
+
+/**
+ * @brief Sets the strength of the pullup resistor
+ *
+ * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
+{
+    USB_SERIAL_JTAG.conf0.pullup_value = strong;
+}
+
+/**
+ * @brief Check if USB FSLS PHY pads are enabled
+ *
+ * @return True if enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
+{
+    return USB_SERIAL_JTAG.conf0.usb_pad_enable;
+}
+
+/**
+ * @brief Enable the USB FSLS PHY pads
+ *
+ * @param enable Whether to enable the USB FSLS PHY pads
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
+}
+
+/* ----------------------------- RCC Functions  ----------------------------- */
+
 /**
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module
diff --git a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h
index e0776eb923..d21821ad35 100644
--- a/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32c6/include/hal/usb_serial_jtag_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,8 @@ typedef enum {
     USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
 } usb_serial_jtag_ll_intr_t;
 
+/* ----------------------------- USJ Peripheral ----------------------------- */
+
 /**
  * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
  *
@@ -177,32 +179,125 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
     USB_SERIAL_JTAG.ep1_conf.wr_done=1;
 }
 
+/**
+ * @brief Enable USJ JTAG bridge
+ *
+ * If enabled, USJ is disconnected from internal JTAG interface. JTAG interface
+ * is routed through GPIO matrix instead.
+ *
+ * @param enable Enable USJ JTAG bridge
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable;
+}
+
+/* ---------------------------- USB PHY Control  ---------------------------- */
 
 /**
- * @brief Disable usb serial jtag pad during light sleep to avoid current leakage
+ * @brief Sets whether the USJ's FSLS PHY interface routes to an internal or external PHY
  *
- * @return Initial configuration of usb serial jtag pad enable before light sleep
+ * @param enable Enables external PHY, internal otherwise
  */
-FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_external(bool enable)
 {
-    bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
-
-    // Disable USB pad function
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
-
-    return pad_enabled;
+    USB_SERIAL_JTAG.conf0.phy_sel = enable;
 }
 
 /**
- * @brief Enable the internal USJ PHY control to D+/D- pad
+ * @brief Enables/disables exchanging of the D+/D- pins USB PHY
  *
- * @param enable_pad Enable the USJ PHY control to D+/D- pad
+ * @param enable Enables pin exchange, disabled otherwise
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
 {
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
+    if (enable) {
+        USB_SERIAL_JTAG.conf0.exchg_pins = 1;
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
+    } else {
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
+        USB_SERIAL_JTAG.conf0.exchg_pins = 0;
+    }
 }
 
+/**
+ * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
+ *
+ * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
+ * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
+{
+    USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
+    USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
+    USB_SERIAL_JTAG.conf0.vref_override = 1;
+}
+
+/**
+ * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
+{
+    USB_SERIAL_JTAG.conf0.vref_override = 0;
+}
+
+/**
+ * @brief Enable override of USB FSLS PHY's pull up/down resistors
+ *
+ * @param dp_pu Enable D+ pullup
+ * @param dm_pu Enable D- pullup
+ * @param dp_pd Enable D+ pulldown
+ * @param dm_pd Enable D- pulldown
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
+{
+    USB_SERIAL_JTAG.conf0.dp_pullup = dp_pu;
+    USB_SERIAL_JTAG.conf0.dp_pulldown = dp_pd;
+    USB_SERIAL_JTAG.conf0.dm_pullup = dm_pu;
+    USB_SERIAL_JTAG.conf0.dm_pulldown = dm_pd;
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
+}
+
+/**
+ * @brief Disable override of USB FSLS PHY pull up/down resistors
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
+{
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
+}
+
+/**
+ * @brief Sets the strength of the pullup resistor
+ *
+ * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
+{
+    USB_SERIAL_JTAG.conf0.pullup_value = strong;
+}
+
+/**
+ * @brief Check if USB FSLS PHY pads are enabled
+ *
+ * @return True if enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
+{
+    return USB_SERIAL_JTAG.conf0.usb_pad_enable;
+}
+
+/**
+ * @brief Enable the USB FSLS PHY pads
+ *
+ * @param enable Whether to enable the USB FSLS PHY pads
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
+}
+
+/* ----------------------------- RCC Functions  ----------------------------- */
+
 /**
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module
diff --git a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
index 3e3cf1cea2..ec8a32ea67 100644
--- a/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,8 @@ typedef enum {
     USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
 } usb_serial_jtag_ll_intr_t;
 
+/* ----------------------------- USJ Peripheral ----------------------------- */
+
 /**
  * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
  *
@@ -178,30 +180,124 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
 }
 
 /**
- * @brief Disable usb serial jtag pad during light sleep to avoid current leakage
+ * @brief Enable USJ JTAG bridge
  *
- * @return Initial configuration of usb serial jtag pad enable before light sleep
+ * If enabled, USJ is disconnected from internal JTAG interface. JTAG interface
+ * is routed through GPIO matrix instead.
+ *
+ * @param enable Enable USJ JTAG bridge
  */
-FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable)
 {
-    bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
+    USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable;
+}
 
-    // Disable USB pad function
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+/* ---------------------------- USB PHY Control  ---------------------------- */
 
-    return pad_enabled;
+/**
+ * @brief Sets whether the USJ's FSLS PHY interface routes to an internal or external PHY
+ *
+ * @param enable Enables external PHY, internal otherwise
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_external(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.phy_sel = enable;
 }
 
 /**
- * @brief Enable the internal USJ PHY control to D+/D- pad
+ * @brief Enables/disables exchanging of the D+/D- pins USB PHY
  *
- * @param enable_pad Enable the USJ PHY control to D+/D- pad
+ * @param enable Enables pin exchange, disabled otherwise
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
 {
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
+    if (enable) {
+        USB_SERIAL_JTAG.conf0.exchg_pins = 1;
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
+    } else {
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
+        USB_SERIAL_JTAG.conf0.exchg_pins = 0;
+    }
 }
 
+/**
+ * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
+ *
+ * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
+ * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
+{
+    USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
+    USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
+    USB_SERIAL_JTAG.conf0.vref_override = 1;
+}
+
+/**
+ * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
+{
+    USB_SERIAL_JTAG.conf0.vref_override = 0;
+}
+
+/**
+ * @brief Enable override of USB FSLS PHY's pull up/down resistors
+ *
+ * @param dp_pu Enable D+ pullup
+ * @param dm_pu Enable D- pullup
+ * @param dp_pd Enable D+ pulldown
+ * @param dm_pd Enable D- pulldown
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
+{
+    USB_SERIAL_JTAG.conf0.dp_pullup = dp_pu;
+    USB_SERIAL_JTAG.conf0.dp_pulldown = dp_pd;
+    USB_SERIAL_JTAG.conf0.dm_pullup = dm_pu;
+    USB_SERIAL_JTAG.conf0.dm_pulldown = dm_pd;
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
+}
+
+/**
+ * @brief Disable override of USB FSLS PHY pull up/down resistors
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
+{
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
+}
+
+/**
+ * @brief Sets the strength of the pullup resistor
+ *
+ * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
+{
+    USB_SERIAL_JTAG.conf0.pullup_value = strong;
+}
+
+/**
+ * @brief Check if USB FSLS PHY pads are enabled
+ *
+ * @return True if enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
+{
+    return USB_SERIAL_JTAG.conf0.usb_pad_enable;
+}
+
+/**
+ * @brief Enable the USB FSLS PHY pads
+ *
+ * @param enable Whether to enable the USB FSLS PHY pads
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
+}
+
+/* ----------------------------- RCC Functions  ----------------------------- */
+
 /**
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module
diff --git a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
index e00c402ba8..ad20f050ad 100644
--- a/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
+++ b/components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,7 @@
 #include <stdbool.h>
 #include "esp_attr.h"
 #include "soc/system_struct.h"
+#include "soc/rtc_cntl_struct.h"
 #include "soc/usb_serial_jtag_reg.h"
 #include "soc/usb_serial_jtag_struct.h"
 
@@ -34,6 +35,8 @@ typedef enum {
     USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD       = (1 << 10),
 } usb_serial_jtag_intr_t;
 
+/* ----------------------------- USJ Peripheral ----------------------------- */
+
 /**
  * @brief  Enable the USB_SERIAL_JTAG interrupt based on the given mask.
  *
@@ -178,30 +181,142 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
 }
 
 /**
- * @brief Disable usb serial jtag pad during light sleep to avoid current leakage
+ * @brief Enable USJ JTAG bridge
  *
- * @return Initial configuration of usb serial jtag pad enable before light sleep
+ * If enabled, USJ is disconnected from internal JTAG interface. JTAG interface
+ * is routed through GPIO matrix instead.
+ *
+ * @param enable Enable USJ JTAG bridge
  */
-FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable)
 {
-    bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
+    USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable;
+}
 
-    // Disable USB pad function
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
+/* ---------------------------- USB PHY Control  ---------------------------- */
 
-    return pad_enabled;
+/**
+ * @brief Sets whether the USJ's FSLS PHY interface routes to an internal or external PHY
+ *
+ * @param enable Enables external PHY, internal otherwise
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_external(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.phy_sel = enable;
+    // Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
+    RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
+    /*
+    For 'sw_usb_phy_sel':
+    0 - Internal USB FSLS PHY is mapped to the USJ. USB Wrap mapped to external PHY
+    1 - Internal USB FSLS PHY is mapped to the USB Wrap. USJ mapped to external PHY
+    */
+    RTCCNTL.usb_conf.sw_usb_phy_sel = enable;
 }
 
 /**
- * @brief Enable the internal USJ PHY control to D+/D- pad
+ * @brief Enables/disables exchanging of the D+/D- pins USB PHY
  *
- * @param enable_pad Enable the USJ PHY control to D+/D- pad
+ * @param enable Enables pin exchange, disabled otherwise
  */
-FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
 {
-    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
+    if (enable) {
+        USB_SERIAL_JTAG.conf0.exchg_pins = 1;
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
+    } else {
+        USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
+        USB_SERIAL_JTAG.conf0.exchg_pins = 0;
+    }
 }
 
+/**
+ * @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
+ *
+ * @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
+ * @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
+{
+    USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
+    USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
+    USB_SERIAL_JTAG.conf0.vref_override = 1;
+}
+
+/**
+ * @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
+{
+    USB_SERIAL_JTAG.conf0.vref_override = 0;
+}
+
+/**
+ * @brief Enable override of USB FSLS PHY's pull up/down resistors
+ *
+ * @param dp_pu Enable D+ pullup
+ * @param dm_pu Enable D- pullup
+ * @param dp_pd Enable D+ pulldown
+ * @param dm_pd Enable D- pulldown
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(bool dp_pu, bool dm_pu, bool dp_pd, bool dm_pd)
+{
+    USB_SERIAL_JTAG.conf0.dp_pullup = dp_pu;
+    USB_SERIAL_JTAG.conf0.dp_pulldown = dp_pd;
+    USB_SERIAL_JTAG.conf0.dm_pullup = dm_pu;
+    USB_SERIAL_JTAG.conf0.dm_pulldown = dm_pd;
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
+}
+
+/**
+ * @brief Disable override of USB FSLS PHY pull up/down resistors
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
+{
+    USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
+}
+
+/**
+ * @brief Sets the strength of the pullup resistor
+ *
+ * @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
+{
+    USB_SERIAL_JTAG.conf0.pullup_value = strong;
+}
+
+/**
+ * @brief Check if USB FSLS PHY pads are enabled
+ *
+ * @return True if enabled, false otherwise
+ */
+FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
+{
+    return USB_SERIAL_JTAG.conf0.usb_pad_enable;
+}
+
+/**
+ * @brief Enable the USB FSLS PHY pads
+ *
+ * @param enable Whether to enable the USB FSLS PHY pads
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
+{
+    USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
+}
+
+/**
+ * @brief Set USB FSLS PHY TX output clock edge
+ *
+ * @param clk_neg_edge True if TX output at negedge, posedge otherwise
+ */
+FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_tx_edge(bool clk_neg_edge)
+{
+    USB_SERIAL_JTAG.conf0.phy_tx_edge_sel = clk_neg_edge;
+}
+
+/* ----------------------------- RCC Functions  ----------------------------- */
+
 /**
  * @brief Enable the bus clock for  USB Serial_JTAG module
  * @param clk_en True if enable the clock of USB Serial_JTAG module