Merge branch 'feature/update_etm_source_on_p4' into 'master'

feat(etm): update etm source on p4

See merge request espressif/esp-idf!25021

components/soc/esp32p4/include/soc/soc_etm_source.h

@@ -59,238 +59,188 @@
 #define LEDC_EVT_TIMER1_CMP 50
 #define LEDC_EVT_TIMER2_CMP 51
 #define LEDC_EVT_TIMER3_CMP 52
-#define PCNT_EVT_CNT_EQ_THRESH 53
-#define PCNT_EVT_CNT_EQ_LMT 54
-#define PCNT_EVT_CNT_EQ_ZERO 55
-#define TG0_EVT_CNT_CMP_TIMER0 56
-#define TG0_EVT_CNT_CMP_TIMER1 57
-#define TG1_EVT_CNT_CMP_TIMER0 58
-#define TG1_EVT_CNT_CMP_TIMER1 59
-#define SYSTIMER_EVT_CNT_CMP0 60
-#define SYSTIMER_EVT_CNT_CMP1 61
-#define SYSTIMER_EVT_CNT_CMP2 62
-#define RMT_EVT_TX_END 63
-#define RMT_EVT_TX_LOOP 64
-#define RMT_EVT_RX_END 65
-#define RMT_EVT_TX_THRESH 66
-#define RMT_EVT_RX_THRESH 67
-#define MCPWM0_EVT_TIMER0_STOP 68
-#define MCPWM0_EVT_TIMER1_STOP 69
-#define MCPWM0_EVT_TIMER2_STOP 70
-#define MCPWM0_EVT_TIMER0_TEZ 71
-#define MCPWM0_EVT_TIMER1_TEZ 72
-#define MCPWM0_EVT_TIMER2_TEZ 73
-#define MCPWM0_EVT_TIMER0_TEP 74
-#define MCPWM0_EVT_TIMER1_TEP 75
-#define MCPWM0_EVT_TIMER2_TEP 76
-#define MCPWM0_EVT_OP0_TEA 77
-#define MCPWM0_EVT_OP1_TEA 78
-#define MCPWM0_EVT_OP2_TEA 79
-#define MCPWM0_EVT_OP0_TEB 80
-#define MCPWM0_EVT_OP1_TEB 81
-#define MCPWM0_EVT_OP2_TEB 82
-#define MCPWM0_EVT_F0 83
-#define MCPWM0_EVT_F1 84
-#define MCPWM0_EVT_F2 85
-#define MCPWM0_EVT_F0_CLR 86
-#define MCPWM0_EVT_F1_CLR 87
-#define MCPWM0_EVT_F2_CLR 88
-#define MCPWM0_EVT_TZ0_CBC 89
-#define MCPWM0_EVT_TZ1_CBC 90
-#define MCPWM0_EVT_TZ2_CBC 91
-#define MCPWM0_EVT_TZ0_OST 92
-#define MCPWM0_EVT_TZ1_OST 93
-#define MCPWM0_EVT_TZ2_OST 94
-#define MCPWM0_EVT_CAP0 95
-#define MCPWM0_EVT_CAP1 96
-#define MCPWM0_EVT_CAP2 97
-#define MCPWM0_EVT_OP0_TEE1 98
-#define MCPWM0_EVT_OP1_TEE1 99
-#define MCPWM0_EVT_OP2_TEE1 100
-#define MCPWM0_EVT_OP0_TEE2 101
-#define MCPWM0_EVT_OP1_TEE2 102
-#define MCPWM0_EVT_OP2_TEE2 103
-#define MCPWM1_EVT_TIMER0_STOP 104
-#define MCPWM1_EVT_TIMER1_STOP 105
-#define MCPWM1_EVT_TIMER2_STOP 106
-#define MCPWM1_EVT_TIMER0_TEZ 107
-#define MCPWM1_EVT_TIMER1_TEZ 108
-#define MCPWM1_EVT_TIMER2_TEZ 109
-#define MCPWM1_EVT_TIMER0_TEP 110
-#define MCPWM1_EVT_TIMER1_TEP 111
-#define MCPWM1_EVT_TIMER2_TEP 112
-#define MCPWM1_EVT_OP0_TEA 113
-#define MCPWM1_EVT_OP1_TEA 114
-#define MCPWM1_EVT_OP2_TEA 115
-#define MCPWM1_EVT_OP0_TEB 116
-#define MCPWM1_EVT_OP1_TEB 117
-#define MCPWM1_EVT_OP2_TEB 118
-#define MCPWM1_EVT_F0 119
-#define MCPWM1_EVT_F1 120
-#define MCPWM1_EVT_F2 121
-#define MCPWM1_EVT_F0_CLR 122
-#define MCPWM1_EVT_F1_CLR 123
-#define MCPWM1_EVT_F2_CLR 124
-#define MCPWM1_EVT_TZ0_CBC 125
-#define MCPWM1_EVT_TZ1_CBC 126
-#define MCPWM1_EVT_TZ2_CBC 127
-#define MCPWM1_EVT_TZ0_OST 128
-#define MCPWM1_EVT_TZ1_OST 129
-#define MCPWM1_EVT_TZ2_OST 130
-#define MCPWM1_EVT_CAP0 131
-#define MCPWM1_EVT_CAP1 132
-#define MCPWM1_EVT_CAP2 133
-#define MCPWM1_EVT_OP0_TEE1 134
-#define MCPWM1_EVT_OP1_TEE1 135
-#define MCPWM1_EVT_OP2_TEE1 136
-#define MCPWM1_EVT_OP0_TEE2 137
-#define MCPWM1_EVT_OP1_TEE2 138
-#define MCPWM1_EVT_OP2_TEE2 139
-#define ADC_EVT_CONV_CMPLT0 140
-#define ADC_EVT_EQ_ABOVE_THRESH0 141
-#define ADC_EVT_EQ_ABOVE_THRESH1 142
-#define ADC_EVT_EQ_BELOW_THRESH0 143
-#define ADC_EVT_EQ_BELOW_THRESH1 144
-#define ADC_EVT_RESULT_DONE0 145
-#define ADC_EVT_STOPPED0 146
-#define ADC_EVT_STARTED0 147
-#define REGDMA_EVT_DONE0 148
-#define REGDMA_EVT_DONE1 149
-#define REGDMA_EVT_DONE2 150
-#define REGDMA_EVT_DONE3 151
-#define REGDMA_EVT_ERR0 152
-#define REGDMA_EVT_ERR1 153
-#define REGDMA_EVT_ERR2 154
-#define REGDMA_EVT_ERR3 155
-#define PDMA_EVT_TX_DONE 156
-#define PDMA_EVT_OUT_EOF 157
-#define PDMA_EVT_IN_SUC_EOF 158
-#define PDMA_EVT_FULL_OR_EMPTY 159
-#define PDMA_EVT_ALL_DONE 160
-#define PDMA_EVT_RX_DONE 161
-#define TMPSNSR_EVT_OVER_LIMIT 162
-#define UART_EVT_REC_DATA_OVF0 163
-#define UART_EVT_REC_DATA_OVF1 164
-#define UART_EVT_TX_DONE0 165
-#define UART_EVT_TX_DONE1 166
-#define UART_EVT_TIMEOUT0 167
-#define UART_EVT_TIMEOUT1 168
-#define UART_EVT_ERR0 169
-#define UART_EVT_ERR1 170
-#define UART_EVT_CTS0 171
-#define UART_EVT_CTS1 172
-#define UART_EVT_TX_EMPTY0 173
-#define UART_EVT_TX_EMPTY1 174
-#define UART_EVT_AT_PATTERNS0 175
-#define UART_EVT_AT_PATTERNS1 176
-#define SPI_EVT_STOPPED 177
-#define I2S0_EVT_RX_DONE 178
-#define I2S0_EVT_TX_DONE 179
-#define I2S0_EVT_X_WORDS_RECEIVED 180
-#define I2S0_EVT_X_WORDS_SENT 181
-#define I2S1_EVT_RX_DONE 182
-#define I2S1_EVT_TX_DONE 183
-#define I2S1_EVT_X_WORDS_RECEIVED 184
-#define I2S1_EVT_X_WORDS_SENT 185
-#define I2S2_EVT_RX_DONE 186
-#define I2S2_EVT_TX_DONE 187
-#define I2S2_EVT_X_WORDS_RECEIVED 188
-#define I2S2_EVT_X_WORDS_SENT 189
-#define I2C_EVT_TRANS_DONE 190
-#define LCDCAM_EVT_TRANS_DONE 191
-#define CAN_EVT_TRANS_DONE 192
-#define ULP_EVT_ERR_INTR 193
-#define ULP_EVT_HALT 194
-#define ULP_EVT_START_INTR 195
-#define RTC_EVT_TICK 196
-#define RTC_EVT_OVF 197
-#define RTC_EVT_CMP 198
-#define GDMA_AHB_EVT_IN_DONE_CH0 199
-#define GDMA_AHB_EVT_IN_DONE_CH1 200
-#define GDMA_AHB_EVT_IN_DONE_CH2 201
-#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 202
-#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 203
-#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 204
-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 205
-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 206
-#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 207
-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 208
-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 209
-#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 210
-#define GDMA_AHB_EVT_OUT_DONE_CH0 211
-#define GDMA_AHB_EVT_OUT_DONE_CH1 212
-#define GDMA_AHB_EVT_OUT_DONE_CH2 213
-#define GDMA_AHB_EVT_OUT_EOF_CH0 214
-#define GDMA_AHB_EVT_OUT_EOF_CH1 215
-#define GDMA_AHB_EVT_OUT_EOF_CH2 216
-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 217
-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 218
-#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 219
-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 220
-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 221
-#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 222
-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 223
-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 224
-#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 225
-#define GDMA_AXI_EVT_IN_DONE_CH0 226
-#define GDMA_AXI_EVT_IN_DONE_CH1 227
-#define GDMA_AXI_EVT_IN_DONE_CH2 228
-#define GDMA_AXI_EVT_IN_DONE_CH3 229
-#define GDMA_AXI_EVT_IN_DONE_CH4 230
-#define GDMA_AXI_EVT_IN_SUC_EOF_CH0 231
-#define GDMA_AXI_EVT_IN_SUC_EOF_CH1 232
-#define GDMA_AXI_EVT_IN_SUC_EOF_CH2 233
-#define GDMA_AXI_EVT_IN_SUC_EOF_CH3 234
-#define GDMA_AXI_EVT_IN_SUC_EOF_CH4 235
-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH0 236
-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH1 237
-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH2 238
-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH3 239
-#define GDMA_AXI_EVT_IN_FIFO_EMPTY_CH4 240
-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH0 241
-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH1 242
-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH2 243
-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH3 244
-#define GDMA_AXI_EVT_IN_FIFO_FULL_CH4 245
-#define GDMA_AXI_EVT_OUT_DONE_CH0 246
-#define GDMA_AXI_EVT_OUT_DONE_CH1 247
-#define GDMA_AXI_EVT_OUT_DONE_CH2 248
-#define GDMA_AXI_EVT_OUT_DONE_CH3 249
-#define GDMA_AXI_EVT_OUT_DONE_CH4 250
-#define GDMA_AXI_EVT_OUT_EOF_CH0 251
-#define GDMA_AXI_EVT_OUT_EOF_CH1 252
-#define GDMA_AXI_EVT_OUT_EOF_CH2 253
-#define GDMA_AXI_EVT_OUT_EOF_CH3 254
-#define GDMA_AXI_EVT_OUT_EOF_CH4 255
-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH0 256
-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH1 257
-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH2 258
-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH3 259
-#define GDMA_AXI_EVT_OUT_TOTAL_EOF_CH4 260
-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0 261
-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1 262
-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2 263
-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH3 264
-#define GDMA_AXI_EVT_OUT_FIFO_EMPTY_CH4 265
-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH0 266
-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH1 267
-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH2 268
-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH3 269
-#define GDMA_AXI_EVT_OUT_FIFO_FULL_CH4 270
-#define PMU_EVT_SLEEP_WEEKUP 271
-#define DMA2D_EVT_IN_DONE_CH0 272
-#define DMA2D_EVT_IN_DONE_CH1 273
-#define DMA2D_EVT_IN_SUC_EOF_CH0 274
-#define DMA2D_EVT_IN_SUC_EOF_CH1 275
-#define DMA2D_EVT_OUT_DONE_CH0 276
-#define DMA2D_EVT_OUT_DONE_CH1 277
-#define DMA2D_EVT_OUT_DONE_CH2 278
-#define DMA2D_EVT_OUT_EOF_CH0 279
-#define DMA2D_EVT_OUT_EOF_CH1 280
-#define DMA2D_EVT_OUT_EOF_CH2 281
-#define DMA2D_EVT_OUT_TOTAL_EOF_CH0 282
-#define DMA2D_EVT_OUT_TOTAL_EOF_CH1 283
-#define DMA2D_EVT_OUT_TOTAL_EOF_CH2 284
+#define TG0_EVT_CNT_CMP_TIMER0 53
+#define TG0_EVT_CNT_CMP_TIMER1 54
+#define TG1_EVT_CNT_CMP_TIMER0 55
+#define TG1_EVT_CNT_CMP_TIMER1 56
+#define SYSTIMER_EVT_CNT_CMP0 57
+#define SYSTIMER_EVT_CNT_CMP1 58
+#define SYSTIMER_EVT_CNT_CMP2 59
+#define MCPWM0_EVT_TIMER0_STOP 60
+#define MCPWM0_EVT_TIMER1_STOP 61
+#define MCPWM0_EVT_TIMER2_STOP 62
+#define MCPWM0_EVT_TIMER0_TEZ 63
+#define MCPWM0_EVT_TIMER1_TEZ 64
+#define MCPWM0_EVT_TIMER2_TEZ 65
+#define MCPWM0_EVT_TIMER0_TEP 66
+#define MCPWM0_EVT_TIMER1_TEP 67
+#define MCPWM0_EVT_TIMER2_TEP 68
+#define MCPWM0_EVT_OP0_TEA 69
+#define MCPWM0_EVT_OP1_TEA 70
+#define MCPWM0_EVT_OP2_TEA 71
+#define MCPWM0_EVT_OP0_TEB 72
+#define MCPWM0_EVT_OP1_TEB 73
+#define MCPWM0_EVT_OP2_TEB 74
+#define MCPWM0_EVT_F0 75
+#define MCPWM0_EVT_F1 76
+#define MCPWM0_EVT_F2 77
+#define MCPWM0_EVT_F0_CLR 78
+#define MCPWM0_EVT_F1_CLR 79
+#define MCPWM0_EVT_F2_CLR 80
+#define MCPWM0_EVT_TZ0_CBC 81
+#define MCPWM0_EVT_TZ1_CBC 82
+#define MCPWM0_EVT_TZ2_CBC 83
+#define MCPWM0_EVT_TZ0_OST 84
+#define MCPWM0_EVT_TZ1_OST 85
+#define MCPWM0_EVT_TZ2_OST 86
+#define MCPWM0_EVT_CAP0 87
+#define MCPWM0_EVT_CAP1 88
+#define MCPWM0_EVT_CAP2 89
+#define MCPWM0_EVT_OP0_TEE1 90
+#define MCPWM0_EVT_OP1_TEE1 91
+#define MCPWM0_EVT_OP2_TEE1 92
+#define MCPWM0_EVT_OP0_TEE2 93
+#define MCPWM0_EVT_OP1_TEE2 94
+#define MCPWM0_EVT_OP2_TEE2 95
+#define MCPWM1_EVT_TIMER0_STOP 96
+#define MCPWM1_EVT_TIMER1_STOP 97
+#define MCPWM1_EVT_TIMER2_STOP 98
+#define MCPWM1_EVT_TIMER0_TEZ 99
+#define MCPWM1_EVT_TIMER1_TEZ 100
+#define MCPWM1_EVT_TIMER2_TEZ 101
+#define MCPWM1_EVT_TIMER0_TEP 102
+#define MCPWM1_EVT_TIMER1_TEP 103
+#define MCPWM1_EVT_TIMER2_TEP 104
+#define MCPWM1_EVT_OP0_TEA 105
+#define MCPWM1_EVT_OP1_TEA 106
+#define MCPWM1_EVT_OP2_TEA 107
+#define MCPWM1_EVT_OP0_TEB 108
+#define MCPWM1_EVT_OP1_TEB 109
+#define MCPWM1_EVT_OP2_TEB 110
+#define MCPWM1_EVT_F0 111
+#define MCPWM1_EVT_F1 112
+#define MCPWM1_EVT_F2 113
+#define MCPWM1_EVT_F0_CLR 114
+#define MCPWM1_EVT_F1_CLR 115
+#define MCPWM1_EVT_F2_CLR 116
+#define MCPWM1_EVT_TZ0_CBC 117
+#define MCPWM1_EVT_TZ1_CBC 118
+#define MCPWM1_EVT_TZ2_CBC 119
+#define MCPWM1_EVT_TZ0_OST 120
+#define MCPWM1_EVT_TZ1_OST 121
+#define MCPWM1_EVT_TZ2_OST 122
+#define MCPWM1_EVT_CAP0 123
+#define MCPWM1_EVT_CAP1 124
+#define MCPWM1_EVT_CAP2 125
+#define MCPWM1_EVT_OP0_TEE1 126
+#define MCPWM1_EVT_OP1_TEE1 127
+#define MCPWM1_EVT_OP2_TEE1 128
+#define MCPWM1_EVT_OP0_TEE2 129
+#define MCPWM1_EVT_OP1_TEE2 130
+#define MCPWM1_EVT_OP2_TEE2 131
+#define ADC_EVT_CONV_CMPLT0 132
+#define ADC_EVT_EQ_ABOVE_THRESH0 133
+#define ADC_EVT_EQ_ABOVE_THRESH1 134
+#define ADC_EVT_EQ_BELOW_THRESH0 135
+#define ADC_EVT_EQ_BELOW_THRESH1 136
+#define ADC_EVT_RESULT_DONE0 137
+#define ADC_EVT_STOPPED0 138
+#define ADC_EVT_STARTED0 139
+#define REGDMA_EVT_DONE0 140
+#define REGDMA_EVT_DONE1 141
+#define REGDMA_EVT_DONE2 142
+#define REGDMA_EVT_DONE3 143
+#define REGDMA_EVT_ERR0 144
+#define REGDMA_EVT_ERR1 145
+#define REGDMA_EVT_ERR2 146
+#define REGDMA_EVT_ERR3 147
+#define TMPSNSR_EVT_OVER_LIMIT 148
+#define I2S0_EVT_RX_DONE 149
+#define I2S0_EVT_TX_DONE 150
+#define I2S0_EVT_X_WORDS_RECEIVED 151
+#define I2S0_EVT_X_WORDS_SENT 152
+#define I2S1_EVT_RX_DONE 153
+#define I2S1_EVT_TX_DONE 154
+#define I2S1_EVT_X_WORDS_RECEIVED 155
+#define I2S1_EVT_X_WORDS_SENT 156
+#define I2S2_EVT_RX_DONE 157
+#define I2S2_EVT_TX_DONE 158
+#define I2S2_EVT_X_WORDS_RECEIVED 159
+#define I2S2_EVT_X_WORDS_SENT 160
+#define ULP_EVT_ERR_INTR 161
+#define ULP_EVT_HALT 162
+#define ULP_EVT_START_INTR 163
+#define RTC_EVT_TICK 164
+#define RTC_EVT_OVF 165
+#define RTC_EVT_CMP 166
+#define PDMA_AHB_EVT_IN_DONE_CH0 167
+#define PDMA_AHB_EVT_IN_DONE_CH1 168
+#define PDMA_AHB_EVT_IN_DONE_CH2 169
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH0 170
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH1 171
+#define PDMA_AHB_EVT_IN_SUC_EOF_CH2 172
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 173
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 174
+#define PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 175
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH0 176
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH1 177
+#define PDMA_AHB_EVT_IN_FIFO_FULL_CH2 178
+#define PDMA_AHB_EVT_OUT_DONE_CH0 179
+#define PDMA_AHB_EVT_OUT_DONE_CH1 180
+#define PDMA_AHB_EVT_OUT_DONE_CH2 181
+#define PDMA_AHB_EVT_OUT_EOF_CH0 182
+#define PDMA_AHB_EVT_OUT_EOF_CH1 183
+#define PDMA_AHB_EVT_OUT_EOF_CH2 184
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 185
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 186
+#define PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 187
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 188
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 189
+#define PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 190
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH0 191
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH1 192
+#define PDMA_AHB_EVT_OUT_FIFO_FULL_CH2 193
+#define PDMA_AXI_EVT_IN_DONE_CH0 194
+#define PDMA_AXI_EVT_IN_DONE_CH1 195
+#define PDMA_AXI_EVT_IN_DONE_CH2 196
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH0 197
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH1 198
+#define PDMA_AXI_EVT_IN_SUC_EOF_CH2 199
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0 200
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1 201
+#define PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2 202
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH0 203
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH1 204
+#define PDMA_AXI_EVT_IN_FIFO_FULL_CH2 205
+#define PDMA_AXI_EVT_OUT_DONE_CH0 206
+#define PDMA_AXI_EVT_OUT_DONE_CH1 207
+#define PDMA_AXI_EVT_OUT_DONE_CH2 208
+#define PDMA_AXI_EVT_OUT_EOF_CH0 209
+#define PDMA_AXI_EVT_OUT_EOF_CH1 210
+#define PDMA_AXI_EVT_OUT_EOF_CH2 211
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0 212
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1 213
+#define PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2 214
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0 215
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1 216
+#define PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2 217
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH0 218
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH1 219
+#define PDMA_AXI_EVT_OUT_FIFO_FULL_CH2 220
+#define PMU_EVT_SLEEP_WEEKUP 221
+#define DMA2D_EVT_IN_DONE_CH0 222
+#define DMA2D_EVT_IN_DONE_CH1 223
+#define DMA2D_EVT_IN_SUC_EOF_CH0 224
+#define DMA2D_EVT_IN_SUC_EOF_CH1 225
+#define DMA2D_EVT_OUT_DONE_CH0 226
+#define DMA2D_EVT_OUT_DONE_CH1 227
+#define DMA2D_EVT_OUT_DONE_CH2 228
+#define DMA2D_EVT_OUT_EOF_CH0 229
+#define DMA2D_EVT_OUT_EOF_CH1 230
+#define DMA2D_EVT_OUT_EOF_CH2 231
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH0 232
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH1 233
+#define DMA2D_EVT_OUT_TOTAL_EOF_CH2 234
 
 #define GPIO_TASK_CH0_SET 1
 #define GPIO_TASK_CH1_SET 2
@@ -320,213 +270,182 @@
 #define LEDC_TASK_TIMER1_RES_UPDATE 26
 #define LEDC_TASK_TIMER2_RES_UPDATE 27
 #define LEDC_TASK_TIMER3_RES_UPDATE 28
-#define LEDC_TASK_RSV0 29
-#define LEDC_TASK_RSV1 30
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 31
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 32
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 33
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 34
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 35
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 36
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 37
-#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 38
-#define LEDC_TASK_TIMER0_CAP 39
-#define LEDC_TASK_TIMER1_CAP 40
-#define LEDC_TASK_TIMER2_CAP 41
-#define LEDC_TASK_TIMER3_CAP 42
-#define LEDC_TASK_SIG_OUT_DIS_CH0 43
-#define LEDC_TASK_SIG_OUT_DIS_CH1 44
-#define LEDC_TASK_SIG_OUT_DIS_CH2 45
-#define LEDC_TASK_SIG_OUT_DIS_CH3 46
-#define LEDC_TASK_SIG_OUT_DIS_CH4 47
-#define LEDC_TASK_SIG_OUT_DIS_CH5 48
-#define LEDC_TASK_SIG_OUT_DIS_CH6 49
-#define LEDC_TASK_SIG_OUT_DIS_CH7 50
-#define LEDC_TASK_OVF_CNT_RST_CH0 51
-#define LEDC_TASK_OVF_CNT_RST_CH1 52
-#define LEDC_TASK_OVF_CNT_RST_CH2 53
-#define LEDC_TASK_OVF_CNT_RST_CH3 54
-#define LEDC_TASK_OVF_CNT_RST_CH4 55
-#define LEDC_TASK_OVF_CNT_RST_CH5 56
-#define LEDC_TASK_OVF_CNT_RST_CH6 57
-#define LEDC_TASK_OVF_CNT_RST_CH7 58
-#define LEDC_TASK_TIMER0_RST 59
-#define LEDC_TASK_TIMER1_RST 60
-#define LEDC_TASK_TIMER2_RST 61
-#define LEDC_TASK_TIMER3_RST 62
-#define LEDC_TASK_TIMER0_RESUME 63
-#define LEDC_TASK_TIMER1_RESUME 64
-#define LEDC_TASK_TIMER2_RESUME 65
-#define LEDC_TASK_TIMER3_RESUME 66
-#define LEDC_TASK_TIMER0_PAUSE 67
-#define LEDC_TASK_TIMER1_PAUSE 68
-#define LEDC_TASK_TIMER2_PAUSE 69
-#define LEDC_TASK_TIMER3_PAUSE 70
-#define LEDC_TASK_GAMMA_RESTART_CH0 71
-#define LEDC_TASK_GAMMA_RESTART_CH1 72
-#define LEDC_TASK_GAMMA_RESTART_CH2 73
-#define LEDC_TASK_GAMMA_RESTART_CH3 74
-#define LEDC_TASK_GAMMA_RESTART_CH4 75
-#define LEDC_TASK_GAMMA_RESTART_CH5 76
-#define LEDC_TASK_GAMMA_RESTART_CH6 77
-#define LEDC_TASK_GAMMA_RESTART_CH7 78
-#define LEDC_TASK_GAMMA_PAUSE_CH0 79
-#define LEDC_TASK_GAMMA_PAUSE_CH1 80
-#define LEDC_TASK_GAMMA_PAUSE_CH2 81
-#define LEDC_TASK_GAMMA_PAUSE_CH3 82
-#define LEDC_TASK_GAMMA_PAUSE_CH4 83
-#define LEDC_TASK_GAMMA_PAUSE_CH5 84
-#define LEDC_TASK_GAMMA_PAUSE_CH6 85
-#define LEDC_TASK_GAMMA_PAUSE_CH7 86
-#define LEDC_TASK_GAMMA_RESUME_CH0 87
-#define LEDC_TASK_GAMMA_RESUME_CH1 88
-#define LEDC_TASK_GAMMA_RESUME_CH2 89
-#define LEDC_TASK_GAMMA_RESUME_CH3 90
-#define LEDC_TASK_GAMMA_RESUME_CH4 91
-#define LEDC_TASK_GAMMA_RESUME_CH5 92
-#define LEDC_TASK_GAMMA_RESUME_CH6 93
-#define LEDC_TASK_GAMMA_RESUME_CH7 94
-#define PCNT_TASK_START 95
-#define PCNT_TASK_STOP 96
-#define PCNT_TASK_CNT_INC 97
-#define PCNT_TASK_CNT_DEC 98
-#define PCNT_TASK_CNT_RST 99
-#define TG0_TASK_CNT_START_TIMER0 100
-#define TG0_TASK_ALARM_START_TIMER0 101
-#define TG0_TASK_CNT_STOP_TIMER0 102
-#define TG0_TASK_CNT_RELOAD_TIMER0 103
-#define TG0_TASK_CNT_CAP_TIMER0 104
-#define TG0_TASK_CNT_START_TIMER1 105
-#define TG0_TASK_ALARM_START_TIMER1 106
-#define TG0_TASK_CNT_STOP_TIMER1 107
-#define TG0_TASK_CNT_RELOAD_TIMER1 108
-#define TG0_TASK_CNT_CAP_TIMER1 109
-#define TG1_TASK_CNT_START_TIMER0 110
-#define TG1_TASK_ALARM_START_TIMER0 111
-#define TG1_TASK_CNT_STOP_TIMER0 112
-#define TG1_TASK_CNT_RELOAD_TIMER0 113
-#define TG1_TASK_CNT_CAP_TIMER0 114
-#define TG1_TASK_CNT_START_TIMER1 115
-#define TG1_TASK_ALARM_START_TIMER1 116
-#define TG1_TASK_CNT_STOP_TIMER1 117
-#define TG1_TASK_CNT_RELOAD_TIMER1 118
-#define TG1_TASK_CNT_CAP_TIMER1 119
-#define RMT_TASK_TX_START 120
-#define RMT_TASK_TX_STOP 121
-#define RMT_TASK_RX_DONE 122
-#define RMT_TASK_RX_START 123
-#define MCPWM0_TASK_CMPR0_A_UP 124
-#define MCPWM0_TASK_CMPR1_A_UP 125
-#define MCPWM0_TASK_CMPR2_A_UP 126
-#define MCPWM0_TASK_CMPR0_B_UP 127
-#define MCPWM0_TASK_CMPR1_B_UP 128
-#define MCPWM0_TASK_CMPR2_B_UP 129
-#define MCPWM0_TASK_GEN_STOP 130
-#define MCPWM0_TASK_TIMER0_SYN 131
-#define MCPWM0_TASK_TIMER1_SYN 132
-#define MCPWM0_TASK_TIMER2_SYN 133
-#define MCPWM0_TASK_TIMER0_PERIOD_UP 134
-#define MCPWM0_TASK_TIMER1_PERIOD_UP 135
-#define MCPWM0_TASK_TIMER2_PERIOD_UP 136
-#define MCPWM0_TASK_TZ0_OST 137
-#define MCPWM0_TASK_TZ1_OST 138
-#define MCPWM0_TASK_TZ2_OST 139
-#define MCPWM0_TASK_CLR0_OST 140
-#define MCPWM0_TASK_CLR1_OST 141
-#define MCPWM0_TASK_CLR2_OST 142
-#define MCPWM0_TASK_CAP0 143
-#define MCPWM0_TASK_CAP1 144
-#define MCPWM0_TASK_CAP2 145
-#define MCPWM1_TASK_CMPR0_A_UP 146
-#define MCPWM1_TASK_CMPR1_A_UP 147
-#define MCPWM1_TASK_CMPR2_A_UP 148
-#define MCPWM1_TASK_CMPR0_B_UP 149
-#define MCPWM1_TASK_CMPR1_B_UP 150
-#define MCPWM1_TASK_CMPR2_B_UP 151
-#define MCPWM1_TASK_GEN_STOP 152
-#define MCPWM1_TASK_TIMER0_SYN 153
-#define MCPWM1_TASK_TIMER1_SYN 154
-#define MCPWM1_TASK_TIMER2_SYN 155
-#define MCPWM1_TASK_TIMER0_PERIOD_UP 156
-#define MCPWM1_TASK_TIMER1_PERIOD_UP 157
-#define MCPWM1_TASK_TIMER2_PERIOD_UP 158
-#define MCPWM1_TASK_TZ0_OST 159
-#define MCPWM1_TASK_TZ1_OST 160
-#define MCPWM1_TASK_TZ2_OST 161
-#define MCPWM1_TASK_CLR0_OST 162
-#define MCPWM1_TASK_CLR1_OST 163
-#define MCPWM1_TASK_CLR2_OST 164
-#define MCPWM1_TASK_CAP0 165
-#define MCPWM1_TASK_CAP1 166
-#define MCPWM1_TASK_CAP2 167
-#define ADC_TASK_SAMPLE0 168
-#define ADC_TASK_SAMPLE1 169
-#define ADC_TASK_START0 170
-#define ADC_TASK_STOP0 171
-#define REGDMA_TASK_START0 172
-#define REGDMA_TASK_START1 173
-#define REGDMA_TASK_START2 174
-#define REGDMA_TASK_START3 175
-#define PDMA_TASK_START_TX 176
-#define PDMA_TASK_START_RX 177
-#define PDMA_TASK_STOP 178
-#define TMPSNSR_TASK_START_SAMPLE 179
-#define TMPSNSR_TASK_STOP_SAMPLE 180
-#define UART_TASK_TX_START0 181
-#define UART_TASK_TX_START1 182
-#define UART_TASK_TX_STOP0 183
-#define UART_TASK_TX_STOP1 184
-#define UART_TASK_RX_START0 185
-#define UART_TASK_RX_START1 186
-#define UART_TASK_RX_STOP0 187
-#define UART_TASK_RX_STOP1 188
-#define SPI_TASK_TX_START 189
-#define SPI_TASK_SLAVE_HD 190
-#define SPI_TASK_STOP 191
-#define I2S0_TASK_START_RX 192
-#define I2S0_TASK_START_TX 193
-#define I2S0_TASK_STOP_RX 194
-#define I2S0_TASK_STOP_TX 195
-#define I2S1_TASK_START_RX 196
-#define I2S1_TASK_START_TX 197
-#define I2S1_TASK_STOP_RX 198
-#define I2S1_TASK_STOP_TX 199
-#define I2S2_TASK_START_RX 200
-#define I2S2_TASK_START_TX 201
-#define I2S2_TASK_STOP_RX 202
-#define I2S2_TASK_STOP_TX 203
-#define I2C_TASK_START_TRANS 204
-#define CAN_TASK_TRANS_START 205
-#define ULP_TASK_WAKEUP_CPU 206
-#define ULP_TASK_INT_CPU 207
-#define RTC_TASK_START 208
-#define RTC_TASK_STOP 209
-#define RTC_TASK_CLR 210
-#define RTC_TASK_TRIGGERFLW 211
-#define GDMA_AHB_TASK_IN_START_CH0 212
-#define GDMA_AHB_TASK_IN_START_CH1 213
-#define GDMA_AHB_TASK_IN_START_CH2 214
-#define GDMA_AHB_TASK_OUT_START_CH0 215
-#define GDMA_AHB_TASK_OUT_START_CH1 216
-#define GDMA_AHB_TASK_OUT_START_CH2 217
-#define GDMA_AXI_TASK_IN_START_CH0 218
-#define GDMA_AXI_TASK_IN_START_CH1 219
-#define GDMA_AXI_TASK_IN_START_CH2 220
-#define GDMA_AXI_TASK_IN_START_CH3 221
-#define GDMA_AXI_TASK_IN_START_CH4 222
-#define GDMA_AXI_TASK_OUT_START_CH0 223
-#define GDMA_AXI_TASK_OUT_START_CH1 224
-#define GDMA_AXI_TASK_OUT_START_CH2 225
-#define GDMA_AXI_TASK_OUT_START_CH3 226
-#define GDMA_AXI_TASK_OUT_START_CH4 227
-#define PMU_TASK_SLEEP_REQ 228
-#define DMA2D_TASK_IN_START_CH0 229
-#define DMA2D_TASK_IN_START_CH1 230
-#define DMA2D_TASK_IN_DSCR_READY_CH0 231
-#define DMA2D_TASK_IN_DSCR_READY_CH1 232
-#define DMA2D_TASK_OUT_START_CH0 233
-#define DMA2D_TASK_OUT_START_CH1 234
-#define DMA2D_TASK_OUT_START_CH2 235
-#define DMA2D_TASK_OUT_DSCR_READY_CH0 236
-#define DMA2D_TASK_OUT_DSCR_READY_CH1 237
-#define DMA2D_TASK_OUT_DSCR_READY_CH2 238
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 35
+#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 36
+#define LEDC_TASK_TIMER0_CAP 37
+#define LEDC_TASK_TIMER1_CAP 38
+#define LEDC_TASK_TIMER2_CAP 39
+#define LEDC_TASK_TIMER3_CAP 40
+#define LEDC_TASK_SIG_OUT_DIS_CH0 41
+#define LEDC_TASK_SIG_OUT_DIS_CH1 42
+#define LEDC_TASK_SIG_OUT_DIS_CH2 43
+#define LEDC_TASK_SIG_OUT_DIS_CH3 44
+#define LEDC_TASK_SIG_OUT_DIS_CH4 45
+#define LEDC_TASK_SIG_OUT_DIS_CH5 46
+#define LEDC_TASK_SIG_OUT_DIS_CH6 47
+#define LEDC_TASK_SIG_OUT_DIS_CH7 48
+#define LEDC_TASK_OVF_CNT_RST_CH0 49
+#define LEDC_TASK_OVF_CNT_RST_CH1 50
+#define LEDC_TASK_OVF_CNT_RST_CH2 51
+#define LEDC_TASK_OVF_CNT_RST_CH3 52
+#define LEDC_TASK_OVF_CNT_RST_CH4 53
+#define LEDC_TASK_OVF_CNT_RST_CH5 54
+#define LEDC_TASK_OVF_CNT_RST_CH6 55
+#define LEDC_TASK_OVF_CNT_RST_CH7 56
+#define LEDC_TASK_TIMER0_RST 57
+#define LEDC_TASK_TIMER1_RST 58
+#define LEDC_TASK_TIMER2_RST 59
+#define LEDC_TASK_TIMER3_RST 60
+#define LEDC_TASK_TIMER0_RESUME 61
+#define LEDC_TASK_TIMER1_RESUME 62
+#define LEDC_TASK_TIMER2_RESUME 63
+#define LEDC_TASK_TIMER3_RESUME 64
+#define LEDC_TASK_TIMER0_PAUSE 65
+#define LEDC_TASK_TIMER1_PAUSE 66
+#define LEDC_TASK_TIMER2_PAUSE 67
+#define LEDC_TASK_TIMER3_PAUSE 68
+#define LEDC_TASK_GAMMA_RESTART_CH0 69
+#define LEDC_TASK_GAMMA_RESTART_CH1 70
+#define LEDC_TASK_GAMMA_RESTART_CH2 71
+#define LEDC_TASK_GAMMA_RESTART_CH3 72
+#define LEDC_TASK_GAMMA_RESTART_CH4 73
+#define LEDC_TASK_GAMMA_RESTART_CH5 74
+#define LEDC_TASK_GAMMA_RESTART_CH6 75
+#define LEDC_TASK_GAMMA_RESTART_CH7 76
+#define LEDC_TASK_GAMMA_PAUSE_CH0 77
+#define LEDC_TASK_GAMMA_PAUSE_CH1 78
+#define LEDC_TASK_GAMMA_PAUSE_CH2 79
+#define LEDC_TASK_GAMMA_PAUSE_CH3 80
+#define LEDC_TASK_GAMMA_PAUSE_CH4 81
+#define LEDC_TASK_GAMMA_PAUSE_CH5 82
+#define LEDC_TASK_GAMMA_PAUSE_CH6 83
+#define LEDC_TASK_GAMMA_PAUSE_CH7 84
+#define LEDC_TASK_GAMMA_RESUME_CH0 85
+#define LEDC_TASK_GAMMA_RESUME_CH1 86
+#define LEDC_TASK_GAMMA_RESUME_CH2 87
+#define LEDC_TASK_GAMMA_RESUME_CH3 88
+#define LEDC_TASK_GAMMA_RESUME_CH4 89
+#define LEDC_TASK_GAMMA_RESUME_CH5 90
+#define LEDC_TASK_GAMMA_RESUME_CH6 91
+#define LEDC_TASK_GAMMA_RESUME_CH7 92
+#define TG0_TASK_CNT_START_TIMER0 93
+#define TG0_TASK_ALARM_START_TIMER0 94
+#define TG0_TASK_CNT_STOP_TIMER0 95
+#define TG0_TASK_CNT_RELOAD_TIMER0 96
+#define TG0_TASK_CNT_CAP_TIMER0 97
+#define TG0_TASK_CNT_START_TIMER1 98
+#define TG0_TASK_ALARM_START_TIMER1 99
+#define TG0_TASK_CNT_STOP_TIMER1 100
+#define TG0_TASK_CNT_RELOAD_TIMER1 101
+#define TG0_TASK_CNT_CAP_TIMER1 102
+#define TG1_TASK_CNT_START_TIMER0 103
+#define TG1_TASK_ALARM_START_TIMER0 104
+#define TG1_TASK_CNT_STOP_TIMER0 105
+#define TG1_TASK_CNT_RELOAD_TIMER0 106
+#define TG1_TASK_CNT_CAP_TIMER0 107
+#define TG1_TASK_CNT_START_TIMER1 108
+#define TG1_TASK_ALARM_START_TIMER1 109
+#define TG1_TASK_CNT_STOP_TIMER1 110
+#define TG1_TASK_CNT_RELOAD_TIMER1 111
+#define TG1_TASK_CNT_CAP_TIMER1 112
+#define MCPWM0_TASK_CMPR0_A_UP 113
+#define MCPWM0_TASK_CMPR1_A_UP 114
+#define MCPWM0_TASK_CMPR2_A_UP 115
+#define MCPWM0_TASK_CMPR0_B_UP 116
+#define MCPWM0_TASK_CMPR1_B_UP 117
+#define MCPWM0_TASK_CMPR2_B_UP 118
+#define MCPWM0_TASK_GEN_STOP 119
+#define MCPWM0_TASK_TIMER0_SYN 120
+#define MCPWM0_TASK_TIMER1_SYN 121
+#define MCPWM0_TASK_TIMER2_SYN 122
+#define MCPWM0_TASK_TIMER0_PERIOD_UP 123
+#define MCPWM0_TASK_TIMER1_PERIOD_UP 124
+#define MCPWM0_TASK_TIMER2_PERIOD_UP 125
+#define MCPWM0_TASK_TZ0_OST 126
+#define MCPWM0_TASK_TZ1_OST 127
+#define MCPWM0_TASK_TZ2_OST 128
+#define MCPWM0_TASK_CLR0_OST 129
+#define MCPWM0_TASK_CLR1_OST 130
+#define MCPWM0_TASK_CLR2_OST 131
+#define MCPWM0_TASK_CAP0 132
+#define MCPWM0_TASK_CAP1 133
+#define MCPWM0_TASK_CAP2 134
+#define MCPWM1_TASK_CMPR0_A_UP 135
+#define MCPWM1_TASK_CMPR1_A_UP 136
+#define MCPWM1_TASK_CMPR2_A_UP 137
+#define MCPWM1_TASK_CMPR0_B_UP 138
+#define MCPWM1_TASK_CMPR1_B_UP 139
+#define MCPWM1_TASK_CMPR2_B_UP 140
+#define MCPWM1_TASK_GEN_STOP 141
+#define MCPWM1_TASK_TIMER0_SYN 142
+#define MCPWM1_TASK_TIMER1_SYN 143
+#define MCPWM1_TASK_TIMER2_SYN 144
+#define MCPWM1_TASK_TIMER0_PERIOD_UP 145
+#define MCPWM1_TASK_TIMER1_PERIOD_UP 146
+#define MCPWM1_TASK_TIMER2_PERIOD_UP 147
+#define MCPWM1_TASK_TZ0_OST 148
+#define MCPWM1_TASK_TZ1_OST 149
+#define MCPWM1_TASK_TZ2_OST 150
+#define MCPWM1_TASK_CLR0_OST 151
+#define MCPWM1_TASK_CLR1_OST 152
+#define MCPWM1_TASK_CLR2_OST 153
+#define MCPWM1_TASK_CAP0 154
+#define MCPWM1_TASK_CAP1 155
+#define MCPWM1_TASK_CAP2 156
+#define ADC_TASK_SAMPLE0 157
+#define ADC_TASK_SAMPLE1 158
+#define ADC_TASK_START0 159
+#define ADC_TASK_STOP0 160
+#define REGDMA_TASK_START0 161
+#define REGDMA_TASK_START1 162
+#define REGDMA_TASK_START2 163
+#define REGDMA_TASK_START3 164
+#define TMPSNSR_TASK_START_SAMPLE 165
+#define TMPSNSR_TASK_STOP_SAMPLE 166
+#define I2S0_TASK_START_RX 167
+#define I2S0_TASK_START_TX 168
+#define I2S0_TASK_STOP_RX 169
+#define I2S0_TASK_STOP_TX 170
+#define I2S1_TASK_START_RX 171
+#define I2S1_TASK_START_TX 172
+#define I2S1_TASK_STOP_RX 173
+#define I2S1_TASK_STOP_TX 174
+#define I2S2_TASK_START_RX 175
+#define I2S2_TASK_START_TX 176
+#define I2S2_TASK_STOP_RX 177
+#define I2S2_TASK_STOP_TX 178
+#define ULP_TASK_WAKEUP_CPU 179
+#define ULP_TASK_INT_CPU 180
+#define RTC_TASK_START 181
+#define RTC_TASK_STOP 182
+#define RTC_TASK_CLR 183
+#define RTC_TASK_TRIGGERFLW 184
+#define PDMA_AHB_TASK_IN_START_CH0 185
+#define PDMA_AHB_TASK_IN_START_CH1 186
+#define PDMA_AHB_TASK_IN_START_CH2 187
+#define PDMA_AHB_TASK_OUT_START_CH0 188
+#define PDMA_AHB_TASK_OUT_START_CH1 189
+#define PDMA_AHB_TASK_OUT_START_CH2 190
+#define PDMA_AXI_TASK_IN_START_CH0 191
+#define PDMA_AXI_TASK_IN_START_CH1 192
+#define PDMA_AXI_TASK_IN_START_CH2 193
+#define PDMA_AXI_TASK_OUT_START_CH0 194
+#define PDMA_AXI_TASK_OUT_START_CH1 195
+#define PDMA_AXI_TASK_OUT_START_CH2 196
+#define PMU_TASK_SLEEP_REQ 197
+#define DMA2D_TASK_IN_START_CH0 198
+#define DMA2D_TASK_IN_START_CH1 199
+#define DMA2D_TASK_IN_DSCR_READY_CH0 200
+#define DMA2D_TASK_IN_DSCR_READY_CH1 201
+#define DMA2D_TASK_OUT_START_CH0 202
+#define DMA2D_TASK_OUT_START_CH1 203
+#define DMA2D_TASK_OUT_START_CH2 204
+#define DMA2D_TASK_OUT_DSCR_READY_CH0 205
+#define DMA2D_TASK_OUT_DSCR_READY_CH1 206
+#define DMA2D_TASK_OUT_DSCR_READY_CH2 207