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Merge branch 'feat/esp32s3_support_gpio_deepsleep_wakeup' into 'master'
example/deep_sleep: add example of EXT0 and using internal pullups Closes IDF-4657 and IDFGH-6711 See merge request espressif/esp-idf!17099
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5a2f672d5a
@ -23,30 +23,6 @@ config SOC_CPU_HAS_FPU
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bool
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default y
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config SOC_GPIO_PORT
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int
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default 1
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config SOC_GPIO_PIN_COUNT
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int
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default 49
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config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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bool
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default y
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config SOC_GPIO_SUPPORT_FORCE_HOLD
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bool
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default y
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config SOC_GPIO_VALID_GPIO_MASK
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hex
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default 0x1FFFFFFFFFFFF
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config SOC_GPIO_SUPPORT_SLP_SWITCH
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bool
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default y
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config SOC_LEDC_SUPPORT_XTAL_CLOCK
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bool
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default y
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@ -83,22 +59,6 @@ config SOC_MPU_REGION_WO_SUPPORTED
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bool
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default n
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config SOC_RTCIO_PIN_COUNT
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int
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default 22
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config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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bool
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default y
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config SOC_RTCIO_HOLD_SUPPORTED
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bool
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default y
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config SOC_RTCIO_WAKE_SUPPORTED
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bool
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default y
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config SOC_ADC_SUPPORTED
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bool
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default y
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@ -339,6 +299,30 @@ config SOC_GDMA_PSRAM_MIN_ALIGN
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int
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default 16
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config SOC_GPIO_PORT
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int
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default 1
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config SOC_GPIO_PIN_COUNT
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int
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default 49
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config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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bool
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default y
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config SOC_GPIO_SUPPORT_FORCE_HOLD
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bool
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default y
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config SOC_GPIO_VALID_GPIO_MASK
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hex
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default 0x1FFFFFFFFFFFF
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config SOC_GPIO_SUPPORT_SLP_SWITCH
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bool
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default y
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config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
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int
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default 8
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@ -559,6 +543,22 @@ config SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH
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int
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default 128
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config SOC_RTCIO_PIN_COUNT
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int
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default 22
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config SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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bool
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default y
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config SOC_RTCIO_HOLD_SUPPORTED
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bool
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default y
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config SOC_RTCIO_WAKE_SUPPORTED
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bool
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default y
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config SOC_SIGMADELTA_NUM
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bool
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default y
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@ -1,32 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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// ESP32-S3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1U)
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#define SOC_GPIO_PIN_COUNT (49)
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// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-S3
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// 0~48 except from 22~25 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
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// No GPIO is input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
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// Support to configure slept status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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#ifdef __cplusplus
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}
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#endif
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@ -1,12 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#define SOC_RTCIO_PIN_COUNT 22
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#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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@ -119,7 +119,23 @@
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#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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#include "gpio_caps.h"
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// ESP32-S3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1U)
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#define SOC_GPIO_PIN_COUNT (49)
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// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-S3
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// 0~48 except from 22~25 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
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// No GPIO is input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
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// Support to configure slept status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
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#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
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@ -213,7 +229,10 @@
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#define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3)
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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#include "rtc_io_caps.h"
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#define SOC_RTCIO_PIN_COUNT 22
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#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
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#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
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@ -19,8 +19,17 @@ menu "Example Configuration"
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the window defined by the initial temperature and a threshold
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around it.
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config EXAMPLE_EXT0_WAKEUP
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bool "Enable wakeup from GPIO (ext0)"
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default y
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depends on !SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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help
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This option enables wake up from deep sleep from GPIO3. They should be connected to LOW to avoid
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floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
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pins may trigger a wake up.
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config EXAMPLE_EXT1_WAKEUP
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bool "Enable wakeup from GPIO"
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bool "Enable wakeup from GPIO (ext1)"
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default y
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depends on !SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
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help
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@ -28,6 +37,21 @@ menu "Example Configuration"
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floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
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pins may trigger a wake up.
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config EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
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bool "Use internal pull-up/downs for EXT1 wakeup source"
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default n
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depends on EXAMPLE_EXT1_WAKEUP
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help
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When using EXT1 wakeup source without external pull-up/downs, you may want to make use of the internal
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ones.
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However, the RTC IO reside in the RTC Periph power domain. Enable this option to force that power domain
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ON during deep sleep. Note that this will increase some power comsumption, so it's still suggested to use
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external ones instead.
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EXT0 wakeup source resides in the same power domain as RTCIO (RTC Periph), so internal pull-up/downs are
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always available. There's no need to explicitly force it on for EXT0.
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config EXAMPLE_GPIO_WAKEUP
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bool "Enable wakeup from GPIO"
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default y
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@ -103,6 +103,12 @@ void app_main(void)
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int sleep_time_ms = (now.tv_sec - sleep_enter_time.tv_sec) * 1000 + (now.tv_usec - sleep_enter_time.tv_usec) / 1000;
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switch (esp_sleep_get_wakeup_cause()) {
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#if CONFIG_EXAMPLE_EXT0_WAKEUP
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case ESP_SLEEP_WAKEUP_EXT0: {
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printf("Wake up from ext0\n");
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break;
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}
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#endif // CONFIG_EXAMPLE_EXT0_WAKEUP
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#ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
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case ESP_SLEEP_WAKEUP_EXT1: {
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uint64_t wakeup_pin_mask = esp_sleep_get_ext1_wakeup_status();
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@ -174,6 +180,18 @@ void app_main(void)
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printf("Enabling timer wakeup, %ds\n", wakeup_time_sec);
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esp_sleep_enable_timer_wakeup(wakeup_time_sec * 1000000);
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#if CONFIG_EXAMPLE_EXT0_WAKEUP
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const int ext_wakeup_pin_0 = 3;
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printf("Enabling EXT0 wakeup on pin GPIO%d\n", ext_wakeup_pin_0);
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esp_sleep_enable_ext0_wakeup(ext_wakeup_pin_0, 1);
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// Configure pullup/downs via RTCIO to tie wakeup pins to inactive level during deepsleep.
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// EXT0 resides in the same power domain (RTC_PERIPH) as the RTC IO pullup/downs.
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// No need to keep that power domain explicitly, unlike EXT1.
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rtc_gpio_pullup_dis(ext_wakeup_pin_0);
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rtc_gpio_pulldown_en(ext_wakeup_pin_0);
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#endif // CONFIG_EXAMPLE_EXT0_WAKEUP
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#ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
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const int ext_wakeup_pin_1 = 2;
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const uint64_t ext_wakeup_pin_1_mask = 1ULL << ext_wakeup_pin_1;
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@ -182,6 +200,17 @@ void app_main(void)
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printf("Enabling EXT1 wakeup on pins GPIO%d, GPIO%d\n", ext_wakeup_pin_1, ext_wakeup_pin_2);
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esp_sleep_enable_ext1_wakeup(ext_wakeup_pin_1_mask | ext_wakeup_pin_2_mask, ESP_EXT1_WAKEUP_ANY_HIGH);
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/* If there are no external pull-up/downs, tie wakeup pins to inactive level with internal pull-up/downs via RTC IO
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* during deepsleep. However, RTC IO relies on the RTC_PERIPH power domain. Keeping this power domain on will
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* increase some power comsumption. */
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# if CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
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esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
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rtc_gpio_pullup_dis(ext_wakeup_pin_1);
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rtc_gpio_pulldown_en(ext_wakeup_pin_1);
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rtc_gpio_pullup_dis(ext_wakeup_pin_2);
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rtc_gpio_pulldown_en(ext_wakeup_pin_2);
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# endif //CONFIG_EXAMPLE_EXT1_USE_INTERNAL_PULLUPS
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#endif // CONFIG_EXAMPLE_EXT1_WAKEUP
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#ifdef CONFIG_EXAMPLE_GPIO_WAKEUP
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