From 5911eb3f3ece157d0d1fc0ecfbb1b13d3d5b09eb Mon Sep 17 00:00:00 2001 From: Alexey Gerenkov Date: Fri, 22 Oct 2021 23:19:12 +0300 Subject: [PATCH] apptrace: Adds ESP32-S3 support --- .../app_trace/app_trace_membufs_proto.c | 9 ++- components/app_trace/port/xtensa/port.c | 66 +++++++++++++++---- .../Config/SEGGER_SYSVIEW_Config_FreeRTOS.c | 4 ++ components/heap/port/esp32s3/memory_layout.c | 2 +- tools/ci/check_copyright_ignore.txt | 2 - 5 files changed, 66 insertions(+), 17 deletions(-) diff --git a/components/app_trace/app_trace_membufs_proto.c b/components/app_trace/app_trace_membufs_proto.c index daa2d8cc41..f163daddc6 100644 --- a/components/app_trace/app_trace_membufs_proto.c +++ b/components/app_trace/app_trace_membufs_proto.c @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + #include #include #include "sdkconfig.h" @@ -93,7 +99,8 @@ static esp_err_t esp_apptrace_membufs_swap(esp_apptrace_membufs_proto_data_t *pr if (proto->hw->host_data_pending() && hdr->block_sz > 0) { // TODO: add support for multiple blocks from host, currently there is no need for that uint8_t *p = proto->blocks[new_block_num].start + proto->blocks[new_block_num].sz; - ESP_APPTRACE_LOGD("Recvd %d bytes from host [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]", hdr->block_sz, + ESP_APPTRACE_LOGD("Recvd %d bytes from host (@ 0x%x) [%x %x %x %x %x %x %x %x .. %x %x %x %x %x %x %x %x]", + hdr->block_sz, proto->blocks[new_block_num].start, *(proto->blocks[new_block_num].start+0), *(proto->blocks[new_block_num].start+1), *(proto->blocks[new_block_num].start+2), *(proto->blocks[new_block_num].start+3), *(proto->blocks[new_block_num].start+4), *(proto->blocks[new_block_num].start+5), diff --git a/components/app_trace/port/xtensa/port.c b/components/app_trace/port/xtensa/port.c index b0dcaa1b21..3c6701b004 100644 --- a/components/app_trace/port/xtensa/port.c +++ b/components/app_trace/port/xtensa/port.c @@ -1,3 +1,9 @@ +/* + * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + // // How It Works // ************ @@ -145,7 +151,7 @@ #include "soc/dport_access.h" #if CONFIG_IDF_TARGET_ESP32 #include "soc/dport_reg.h" -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #include "soc/sensitive_reg.h" #endif #include "eri.h" @@ -160,10 +166,42 @@ #define TRACEMEM_MUX_BLK0_ONLY 1 #define TRACEMEM_MUX_BLK1_ONLY 2 #define TRACEMEM_MUX_PROBLK1_APPBLK0 3 +#define TRACEMEM_BLK0_ADDR 0x3FFFC000UL +#define TRACEMEM_BLK1_ADDR 0x3FFF8000UL #elif CONFIG_IDF_TARGET_ESP32S2 #define TRACEMEM_MUX_BLK0_NUM 19 #define TRACEMEM_MUX_BLK1_NUM 20 #define TRACEMEM_BLK_NUM2ADDR(_n_) (0x3FFB8000UL + 0x4000UL*((_n_)-4)) +#define TRACEMEM_BLK0_ADDR TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK0_NUM) +#define TRACEMEM_BLK1_ADDR TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK1_NUM) +#elif CONFIG_IDF_TARGET_ESP32S3 +#define TRACEMEM_MUX_BLK0_NUM 22 +#define TRACEMEM_MUX_BLK0_ALLOC 0x0 +#define TRACEMEM_MUX_BLK1_NUM 23 +#define TRACEMEM_MUX_BLK1_ALLOC 0x1 + +#define TRACEMEM_CORE0_MUX_BLK_BIT(_n_, _a_) (BIT(((_n_)-2UL)/4UL) | ((_a_) << 14)) +#define TRACEMEM_CORE1_MUX_BLK_BIT(_n_, _a_) (BIT(7UL+(((_n_)-2UL)/4UL)) | ((_a_) << 16)) + +#if TRACEMEM_MUX_BLK0_NUM < 2 +#error Invalid block num! +#elif TRACEMEM_MUX_BLK0_NUM < 6 +#define TRACEMEM_BLK0_ADDR (0x3FC88000UL + 0x2000UL*(TRACEMEM_MUX_BLK0_NUM-2)) +#elif TRACEMEM_MUX_BLK0_NUM < 30 +#define TRACEMEM_BLK0_ADDR (0x3FC90000UL + 0x4000UL*(TRACEMEM_MUX_BLK0_NUM-6)) +#else +#error Invalid block num! +#endif + +#if TRACEMEM_MUX_BLK1_NUM < 2 +#error Invalid block num! +#elif TRACEMEM_MUX_BLK1_NUM < 6 +#define TRACEMEM_BLK1_ADDR (0x3FC88000UL + 0x2000UL*(TRACEMEM_MUX_BLK1_NUM-2)) +#elif TRACEMEM_MUX_BLK1_NUM < 30 +#define TRACEMEM_BLK1_ADDR (0x3FC90000UL + 0x4000UL*(TRACEMEM_MUX_BLK1_NUM-6)) +#else +#error Invalid block num! +#endif #endif // TRAX is disabled, so we use its registers for our own purposes @@ -182,18 +220,6 @@ #define ESP_APPTRACE_TRAX_INITED(_hw_) ((_hw_)->inited & (1 << cpu_hal_get_core_id())) -#if CONFIG_IDF_TARGET_ESP32 -static uint8_t * const s_trax_blocks[] = { - (uint8_t *) 0x3FFFC000, - (uint8_t *) 0x3FFF8000 -}; -#elif CONFIG_IDF_TARGET_ESP32S2 -static uint8_t * const s_trax_blocks[] = { - (uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK0_NUM), - (uint8_t *)TRACEMEM_BLK_NUM2ADDR(TRACEMEM_MUX_BLK1_NUM) -}; -#endif - #define ESP_APPTRACE_TRAX_BLOCK_SIZE (0x4000UL) /** TRAX HW transport data */ @@ -223,6 +249,12 @@ static bool esp_apptrace_trax_host_data_pending(void); const static char *TAG = "esp_apptrace"; +static uint8_t * const s_trax_blocks[] = { + (uint8_t *)TRACEMEM_BLK0_ADDR, + (uint8_t *)TRACEMEM_BLK1_ADDR +}; + + esp_apptrace_hw_t *esp_apptrace_uart_hw_get(int num, void **data) { return NULL; @@ -300,6 +332,14 @@ static inline void esp_apptrace_trax_select_memory_block(int block_num) DPORT_WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, block_num ? TRACEMEM_MUX_BLK0_ONLY : TRACEMEM_MUX_BLK1_ONLY); #elif CONFIG_IDF_TARGET_ESP32S2 WRITE_PERI_REG(DPORT_PMS_OCCUPY_3_REG, block_num ? BIT(TRACEMEM_MUX_BLK0_NUM-4) : BIT(TRACEMEM_MUX_BLK1_NUM-4)); +#elif CONFIG_IDF_TARGET_ESP32S3 + // select memory block to be exposed to the TRAX module (accessed by host) + uint32_t block_bits = block_num ? TRACEMEM_CORE0_MUX_BLK_BIT(TRACEMEM_MUX_BLK0_NUM, TRACEMEM_MUX_BLK0_ALLOC) + : TRACEMEM_CORE0_MUX_BLK_BIT(TRACEMEM_MUX_BLK1_NUM, TRACEMEM_MUX_BLK1_ALLOC); + block_bits |= block_num ? TRACEMEM_CORE1_MUX_BLK_BIT(TRACEMEM_MUX_BLK0_NUM, TRACEMEM_MUX_BLK0_ALLOC) + : TRACEMEM_CORE1_MUX_BLK_BIT(TRACEMEM_MUX_BLK1_NUM, TRACEMEM_MUX_BLK1_ALLOC); + ESP_EARLY_LOGV(TAG, "Select block %d @ %p (bits 0x%x)", block_num, s_trax_blocks[block_num], block_bits); + DPORT_WRITE_PERI_REG(SENSITIVE_INTERNAL_SRAM_USAGE_2_REG, block_bits); #endif } diff --git a/components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c b/components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c index 268b389921..6398ae039d 100644 --- a/components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c +++ b/components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c @@ -73,6 +73,8 @@ Revision: $Rev: 3734 $ #include "esp32/clk.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/clk.h" +#elif CONFIG_IDF_TARGET_ESP32S3 +#include "esp32s3/clk.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/clk.h" #endif @@ -142,6 +144,8 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI; #define SYSVIEW_TIMESTAMP_FREQ (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000) #elif CONFIG_IDF_TARGET_ESP32S2 #define SYSVIEW_TIMESTAMP_FREQ (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000) +#elif CONFIG_IDF_TARGET_ESP32S3 +#define SYSVIEW_TIMESTAMP_FREQ (CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ * 1000000) #endif #endif // TS_USE_CCOUNT diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 30aca7c139..37a8efc51d 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -107,7 +107,7 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_dat #endif #if CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM > 0 -SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem); +SOC_RESERVE_MEMORY_REGION(0x3FCD0000, 0x3FCD0000 + CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, trace_mem); #endif // RTC Fast RAM region diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index fbfb4fe756..782a7f8059 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -1,8 +1,6 @@ .gitlab/ci/dependencies/generate_rules.py -components/app_trace/app_trace_membufs_proto.c components/app_trace/port/include/esp_app_trace_port.h components/app_trace/port/riscv/port.c -components/app_trace/port/xtensa/port.c components/app_trace/private_include/esp_app_trace_membufs_proto.h components/app_trace/sys_view/Config/Global.h components/app_trace/sys_view/Config/SEGGER_RTT_Conf.h