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Merge branch 'feat/i2c_c5mp' into 'master'

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feat(i2c): Add i2c support on esp32c5 mp

Closes IDF-8694 and IDF-8696

See merge request espressif/esp-idf!31554
This commit is contained in:
morris 2024-06-18 15:51:33 +08:00
commit 580810d2d5
19 changed files with 161 additions and 225 deletions
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4
components/esp_driver_i2c/test_apps/i2c_test_apps/README.md
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@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |

4
components/esp_lcd/test_apps/i2c_lcd/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
This test app is used to test LCDs with I2C interface.

4
components/esp_lcd/test_apps/i2c_lcd_legacy/README.md
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@ -1,4 +1,4 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
This test app is used to test LCDs with I2C interface.

32
components/hal/esp32c5/include/hal/i2c_ll.h
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@ -611,7 +611,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@ -646,7 +646,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@ -718,7 +718,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief Reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@ -746,7 +746,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
@ -853,6 +853,20 @@ static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
}
/**
* @brief Check if i2c command is done.
*
* @param hw Beginning address of the peripheral registers
* @param cmd_idx The index of the command register, must be less than 8
*
* @return True if the `cmd_idx` command is done. Otherwise false.
*/
__attribute__((always_inline))
static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
{
return hw->command[cmd_idx].command_done;
}
/**
* @brief Calculate SCL timeout us to reg value
*
@ -902,7 +916,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, height_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@ -1090,16 +1104,16 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param height_period The I2C SCL height period (in core clock cycle, height_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.
*/
static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period)
static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int height_period, int low_period)
{
hw->scl_low_period.scl_low_period = low_period - 1;
hw->scl_high_period.scl_high_period = hight_period - 10;
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
hw->scl_high_period.scl_high_period = height_period - 10;
hw->scl_high_period.scl_wait_high_period = height_period - hw->scl_high_period.scl_high_period;
}
/**

4
components/hal/test_apps/hal_i2c/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# HAL I2C test

6
components/hal/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c
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@ -92,7 +92,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
// 2. Set both SCL and SDA open-drain
// 3. Set both SCL and SDA pullup enable and pulldown disable. (If you use external pullup, this can be ignored)
// 4. io mux function select
// 5. We connect out/in signal. As I2C master, out/in signal is necessary fpr both SCL and SDA according to esp hardware.
// 5. We connect out/in signal. As I2C master, out/in signal is necessary for both SCL and SDA according to esp hardware.
// SDA pin configurations
if (sda_io != -1) {
@ -101,7 +101,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
gpio_ll_od_enable(&GPIO, sda_io);
gpio_ll_pullup_en(&GPIO, sda_io);
gpio_ll_pulldown_dis(&GPIO, sda_io);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[sda_io], PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, sda_io, PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(sda_io, i2c_periph_signal[cfg->i2c_port].sda_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(sda_io, i2c_periph_signal[cfg->i2c_port].sda_in_sig, 0);
}
@ -112,7 +112,7 @@ esp_err_t hal_i2c_init(hal_i2c_config *cfg)
gpio_ll_od_enable(&GPIO, scl_io);
gpio_ll_pullup_en(&GPIO, scl_io);
gpio_ll_pulldown_dis(&GPIO, scl_io);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[scl_io], PIN_FUNC_GPIO);
gpio_ll_func_sel(&GPIO, scl_io, PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(scl_io, i2c_periph_signal[cfg->i2c_port].scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(scl_io, i2c_periph_signal[cfg->i2c_port].scl_out_sig, 0);
}

22
components/soc/esp32c5/i2c_periph.c Normal file
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@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
};

48
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -67,6 +67,10 @@ config SOC_LEDC_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@ -287,6 +291,50 @@ config SOC_HP_I2C_NUM
int
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_RTC
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
bool
default y
config SOC_I2S_NUM
int
default 1

201
components/soc/esp32c5/include/soc/i2c_struct.h
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@ -992,180 +992,37 @@ typedef union {
uint32_t val;
} i2c_int_status_reg_t;
/** Group: Command registers */
/** Type of comd0 register
* I2C command register 0
/** Type of comd register
* I2C command register n
*/
typedef union {
struct {
/** command0 : R/W; bitpos: [13:0]; default: 0;
* Configures command 0. \\
* It consists of three parts:\\
* op_code is the command\\
* 1: WRITE\\
* 2: STOP\\
* 3: READ\\
* 4: END\\
* 6: RSTART\\
* Byte_num represents the number of bytes that need to be sent or received.\\
* Configures command 0. It consists of three parts:
* op_code is the command,
* 0: RSTART,
* 1: WRITE,
* 2: READ,
* 3: STOP,
* 4: END.
*
* Byte_num represents the number of bytes that need to be sent or received.
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
* structure <a href=fig:i2c-cmd-structure">link</a> for more information.
* \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}"
* structure for more information.
*/
uint32_t command0:14;
uint32_t command:14;
uint32_t reserved_14:17;
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
/** command_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 0 is done in I2C Master mode.
* 0: Not done
*
* 1: Done
*/
uint32_t command0_done:1;
uint32_t command_done:1;
};
uint32_t val;
} i2c_comd0_reg_t;
/** Type of comd1 register
* I2C command register 1
*/
typedef union {
struct {
/** command1 : R/W; bitpos: [13:0]; default: 0;
* Configures command 1.\\
* See details in I2C_CMD0_REG[13:0].
*/
uint32_t command1:14;
uint32_t reserved_14:17;
/** command1_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 1 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command1_done:1;
};
uint32_t val;
} i2c_comd1_reg_t;
/** Type of comd2 register
* I2C command register 2
*/
typedef union {
struct {
/** command2 : R/W; bitpos: [13:0]; default: 0;
* Configures command 2. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command2:14;
uint32_t reserved_14:17;
/** command2_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 2 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command2_done:1;
};
uint32_t val;
} i2c_comd2_reg_t;
/** Type of comd3 register
* I2C command register 3
*/
typedef union {
struct {
/** command3 : R/W; bitpos: [13:0]; default: 0;
* Configures command 3. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command3:14;
uint32_t reserved_14:17;
/** command3_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 3 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command3_done:1;
};
uint32_t val;
} i2c_comd3_reg_t;
/** Type of comd4 register
* I2C command register 4
*/
typedef union {
struct {
/** command4 : R/W; bitpos: [13:0]; default: 0;
* Configures command 4. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command4:14;
uint32_t reserved_14:17;
/** command4_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 4 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command4_done:1;
};
uint32_t val;
} i2c_comd4_reg_t;
/** Type of comd5 register
* I2C command register 5
*/
typedef union {
struct {
/** command5 : R/W; bitpos: [13:0]; default: 0;
* Configures command 5. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command5:14;
uint32_t reserved_14:17;
/** command5_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 5 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command5_done:1;
};
uint32_t val;
} i2c_comd5_reg_t;
/** Type of comd6 register
* I2C command register 6
*/
typedef union {
struct {
/** command6 : R/W; bitpos: [13:0]; default: 0;
* Configures command 6. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command6:14;
uint32_t reserved_14:17;
/** command6_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 6 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command6_done:1;
};
uint32_t val;
} i2c_comd6_reg_t;
/** Type of comd7 register
* I2C command register 7
*/
typedef union {
struct {
/** command7 : R/W; bitpos: [13:0]; default: 0;
* Configures command 7. See details in I2C_CMD0_REG[13:0].
*/
uint32_t command7:14;
uint32_t reserved_14:17;
/** command7_done : R/W/SS; bitpos: [31]; default: 0;
* Represents whether command 7 is done in I2C Master mode.\\
* 0: Not done \\
* 1: Done \\
*/
uint32_t command7_done:1;
};
uint32_t val;
} i2c_comd7_reg_t;
} i2c_comd_reg_t;
/** Group: Version register */
/** Type of date register
@ -1233,14 +1090,7 @@ typedef struct {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
volatile i2c_clk_conf_reg_t clk_conf;
volatile i2c_comd0_reg_t comd0;
volatile i2c_comd1_reg_t comd1;
volatile i2c_comd2_reg_t comd2;
volatile i2c_comd3_reg_t comd3;
volatile i2c_comd4_reg_t comd4;
volatile i2c_comd5_reg_t comd5;
volatile i2c_comd6_reg_t comd6;
volatile i2c_comd7_reg_t comd7;
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@ -1248,15 +1098,14 @@ typedef struct {
uint32_t reserved_088[28];
volatile i2c_date_reg_t date;
uint32_t reserved_0fc;
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
uint32_t reserved_104[31];
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
volatile uint32_t txfifo_mem[32];
volatile uint32_t rxfifo_mem[32];
} i2c_dev_t;
extern i2c_dev_t I2C;
extern i2c_dev_t I2C0;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
#endif
#ifdef __cplusplus

10
components/soc/esp32c5/include/soc/pcr_struct.h
View File

@ -2329,6 +2329,13 @@ typedef union {
uint32_t val;
} pcr_date_reg_t;
/**
* @brief The struct of I2C configuration registers
*/
typedef struct {
pcr_i2c_conf_reg_t i2c_conf;
pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
} pcr_i2c_reg_t;
typedef struct {
volatile pcr_uart0_conf_reg_t uart0_conf;
@ -2339,8 +2346,7 @@ typedef struct {
volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
volatile pcr_mspi_conf_reg_t mspi_conf;
volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
volatile pcr_i2c_conf_reg_t i2c_conf;
volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
volatile pcr_i2c_reg_t i2c[1];
volatile pcr_twai0_conf_reg_t twai0_conf;
volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
volatile pcr_twai1_conf_reg_t twai1_conf;

2
components/soc/esp32c5/include/soc/periph_defs.h
View File

@ -20,7 +20,7 @@ typedef enum {
PERIPH_UART0_MODULE,
PERIPH_UART1_MODULE,
PERIPH_USB_DEVICE_MODULE, // USB Serial Jtag
PERIPH_I2C_MODULE,
PERIPH_I2C0_MODULE,
PERIPH_I2S_MODULE,
PERIPH_TIMG0_MODULE,
PERIPH_TIMG1_MODULE,

26
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -43,7 +43,7 @@
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
#define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
#define SOC_AES_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
@ -235,20 +235,18 @@
#define SOC_I2C_NUM (1U)
#define SOC_HP_I2C_NUM (1U)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693

2
components/soc/esp32c5/ld/esp32c5.peripherals.ld
View File

@ -8,7 +8,7 @@ PROVIDE ( UART0 = 0x60000000 );
PROVIDE ( UART1 = 0x60001000 );
PROVIDE ( SPIMEM0 = 0x60002000 );
PROVIDE ( SPIMEM1 = 0x60003000 );
PROVIDE ( I2C = 0x60004000 );
PROVIDE ( I2C0 = 0x60004000 );
PROVIDE ( UHCI = 0x60005000 );
PROVIDE ( RMT = 0x60006000 );
PROVIDE ( RMTMEM = 0x60006400 );

1
docs/docs_not_updated/esp32c5.txt
View File

@ -108,7 +108,6 @@ api-reference/peripherals/touch_pad.rst
api-reference/peripherals/adc_calibration.rst
api-reference/peripherals/spi_slave_hd.rst
api-reference/peripherals/parlio.rst
api-reference/peripherals/i2c.rst
api-reference/peripherals/dedic_gpio.rst
api-reference/peripherals/sd_pullup_requirements.rst
api-reference/peripherals/spi_master.rst

4
examples/peripherals/i2c/i2c_eeprom/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# I2C EEPROM example

4
examples/peripherals/i2c/i2c_tools/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# I2C Tools Example

4
examples/peripherals/i2s/i2s_codec/i2s_es7210_tdm/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
# I2S TDM Example -- ES7210 4-Ch ADC Codec

4
examples/peripherals/i2s/i2s_codec/i2s_es8311/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# I2S ES8311 Example

4
examples/peripherals/lcd/i2c_oled/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
# I2C OLED example