diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c
index ae67528183..e847676f87 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c
@@ -42,6 +42,8 @@ static const char *TAG = "rtc_clk";
 // Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
 static uint32_t s_cur_pll_freq;
 
+static uint32_t s_apb_freq;
+
 static void rtc_clk_cpu_freq_to_8m(void);
 
 void rtc_clk_32k_enable_internal(x32k_config_t cfg)
@@ -510,16 +512,12 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
 
 void rtc_clk_apb_freq_update(uint32_t apb_freq)
 {
-    WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
+    s_apb_freq = apb_freq;
 }
 
 uint32_t rtc_clk_apb_freq_get(void)
 {
-    uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
-    // round to the nearest MHz
-    freq_hz += MHZ / 2;
-    uint32_t remainder = freq_hz % MHZ;
-    return freq_hz - remainder;
+    return s_apb_freq;
 }
 
 void rtc_clk_divider_set(uint32_t div)
diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk_common.h b/components/esp_hw_support/port/esp32s3/rtc_clk_common.h
index 7c0f76dafd..93e328874c 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_clk_common.h
+++ b/components/esp_hw_support/port/esp32s3/rtc_clk_common.h
@@ -35,9 +35,8 @@ extern "C" {
 
 void rtc_clk_cpu_freq_to_xtal(int freq, int div);
 
-/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
- * lower and upper 16-bit halves. These are the routines to work with such a
- * representation.
+/* Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
+ * halves. These are the routines to work with that representation.
  */
 static inline bool clk_val_is_valid(uint32_t val)
 {
diff --git a/components/esp_rom/include/esp32s3/rom/rtc.h b/components/esp_rom/include/esp32s3/rom/rtc.h
index b23b22d4b9..c1a31a3893 100644
--- a/components/esp_rom/include/esp32s3/rom/rtc.h
+++ b/components/esp_rom/include/esp32s3/rom/rtc.h
@@ -51,7 +51,7 @@ extern "C" {
   *     RTC_CNTL_STORE2_REG     Boot time, low word
   *     RTC_CNTL_STORE3_REG     Boot time, high word
   *     RTC_CNTL_STORE4_REG     External XTAL frequency
-  *     RTC_CNTL_STORE5_REG     APB bus frequency
+  *     RTC_CNTL_STORE5_REG     FAST_RTC_MEMORY_LENGTH
   *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
   *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
   *************************************************************************************
@@ -61,7 +61,6 @@ extern "C" {
 #define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
 #define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
 #define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
-#define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c
index b309bef623..5f222e7aef 100644
--- a/components/esp_system/fpga_overrides.c
+++ b/components/esp_system/fpga_overrides.c
@@ -22,6 +22,13 @@
 
 static const char *TAG = "fpga";
 
+#ifdef CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/rtc.h"
+#endif
+#ifdef CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/rtc.h"
+#endif
+
 extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
 
 static void s_warn(void)
@@ -41,7 +48,9 @@ void bootloader_clock_configure(void)
     uint32_t apb_freq_hz = 40000000;
 #endif // CONFIG_IDF_TARGET_ESP32S2
     ets_update_cpu_frequency(apb_freq_hz / 1000000);
-    REG_WRITE(RTC_CNTL_STORE5_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
+#ifdef RTC_APB_FREQ_REG
+    REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
+#endif
     REG_WRITE(RTC_CNTL_STORE4_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
 }
 
diff --git a/components/esp_system/port/soc/esp32s3/reset_reason.c b/components/esp_system/port/soc/esp32s3/reset_reason.c
index e14159e161..94b6da72f5 100644
--- a/components/esp_system/port/soc/esp32s3/reset_reason.c
+++ b/components/esp_system/port/soc/esp32s3/reset_reason.c
@@ -84,10 +84,8 @@ esp_reset_reason_t esp_reset_reason(void)
  * is only used for deep sleep reset, and in this case the reason provided by
  * rtc_get_reset_reason is unambiguous.
  *
- * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
- * the value is replicated in low and high half-words. In addition to that,
- * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
- * deep sleep wake stub address.
+ * In addition to that, MSB is set to 1, which doesn't happen when
+ * RTC_CNTL_STORE6_REG contains deep sleep wake stub address.
  */
 
 #define RST_REASON_BIT  0x80000000
diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h
index a52afe3ee0..8d64b24d1a 100644
--- a/components/soc/esp32s3/include/soc/rtc.h
+++ b/components/soc/esp32s3/include/soc/rtc.h
@@ -480,14 +480,13 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
 void rtc_clk_cpu_freq_set_xtal(void);
 
 /**
- * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ * @brief Store new APB frequency value in RAM
  *
  * This function doesn't change any hardware clocks.
  *
  * Functions which perform frequency switching and change APB frequency call
- * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
- * (one of RTC general purpose retention registers). This should not normally
- * be called from application code.
+ * this function to update the value of APB frequency stored in RAM.
+ * (This should not normally be called from application code.)
  *
  * @param apb_freq  new APB frequency, in Hz
  */