diff --git a/components/driver/ledc/ledc.c b/components/driver/ledc/ledc.c index c5e9b5b190..99c6a4cdf9 100644 --- a/components/driver/ledc/ledc.c +++ b/components/driver/ledc/ledc.c @@ -44,6 +44,18 @@ static __attribute__((unused)) const char *LEDC_TAG = "ledc"; #define LEDC_CLK_SRC_FREQ_PRECISION ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX #endif +#if !SOC_RCC_IS_INDEPENDENT +#define LEDC_BUS_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define LEDC_BUS_CLOCK_ATOMIC() +#endif + +#if SOC_PERIPH_CLK_CTRL_SHARED +#define LEDC_FUNC_CLOCK_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define LEDC_FUNC_CLOCK_ATOMIC() +#endif + typedef enum { LEDC_FSM_IDLE, LEDC_FSM_HW_FADE, @@ -297,8 +309,10 @@ static bool ledc_speed_mode_ctx_create(ledc_mode_t speed_mode) memset(ledc_new_mode_obj->timer_specific_clk, LEDC_TIMER_SPECIFIC_CLK_UNINIT, sizeof(ledc_clk_src_t) * LEDC_TIMER_MAX); #endif p_ledc_obj[speed_mode] = ledc_new_mode_obj; - // Enable APB access to LEDC registers - periph_module_enable(PERIPH_LEDC_MODULE); + LEDC_BUS_CLOCK_ATOMIC() { + ledc_ll_enable_bus_clock(true); + ledc_ll_enable_reset_reg(false); + } } } _lock_release(&s_ledc_mutex[speed_mode]); @@ -439,7 +453,6 @@ static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint3 return ret; } -extern void esp_sleep_periph_use_8m(bool use_or_not); /** * @brief Function setting the LEDC timer divisor with the given source clock, @@ -549,14 +562,20 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n if (p_ledc_obj[speed_mode]->glb_clk != glb_clk) { // TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree] p_ledc_obj[speed_mode]->glb_clk = glb_clk; - ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk); + LEDC_FUNC_CLOCK_ATOMIC() { + ledc_ll_enable_clock(p_ledc_obj[speed_mode]->ledc_hal.dev, true); + ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk); + } } portEXIT_CRITICAL(&ledc_spinlock); ESP_LOGD(LEDC_TAG, "In slow speed mode, global clk set: %d", glb_clk); +#if !CONFIG_IDF_TARGET_ESP32P4 //depend on sleep support IDF-7528 and IDF-7529 /* keep ESP_PD_DOMAIN_RC_FAST on during light sleep */ + extern void esp_sleep_periph_use_8m(bool use_or_not); esp_sleep_periph_use_8m(glb_clk == LEDC_SLOW_CLK_RC_FAST); +#endif } /* The divisor is correct, we can write in the hardware. */ @@ -564,7 +583,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n return ESP_OK; error: - ESP_LOGE(LEDC_TAG, "requested frequency and duty resolution can not be achieved, try reducing freq_hz or duty_resolution. div_param=%"PRIu32, div_param); + ESP_LOGE(LEDC_TAG, "requested frequency %d and duty resolution %d can not be achieved, try reducing freq_hz or duty_resolution. div_param=%"PRIu32, freq_hz, duty_resolution, div_param); return ESP_FAIL; } @@ -655,7 +674,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) if (!new_speed_mode_ctx_created && !p_ledc_obj[speed_mode]) { return ESP_ERR_NO_MEM; } -#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2) +#if !(CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4) // On such targets, the default ledc core(global) clock does not connect to any clock source // Set channel configurations and update bits before core clock is on could lead to error // Therefore, we should connect the core clock to a real clock source to make it on before any ledc register operation diff --git a/components/driver/test_apps/ledc/README.md b/components/driver/test_apps/ledc/README.md index a8b7833fa3..bf47d80ec6 100644 --- a/components/driver/test_apps/ledc/README.md +++ b/components/driver/test_apps/ledc/README.md @@ -1,2 +1,2 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | diff --git a/components/driver/test_apps/ledc/main/test_app_main.c b/components/driver/test_apps/ledc/main/test_app_main.c index df3999b7f2..3818d8c7de 100644 --- a/components/driver/test_apps/ledc/main/test_app_main.c +++ b/components/driver/test_apps/ledc/main/test_app_main.c @@ -1,36 +1,41 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "unity.h" #include "unity_test_utils.h" -#include "unity_test_runner.h" #include "esp_heap_caps.h" // Some resources are lazy allocated in LEDC driver, the threshold is left for that case #define TEST_MEMORY_LEAK_THRESHOLD (230) -static size_t before_free_8bit; -static size_t before_free_32bit; - void setUp(void) { - before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); + unity_utils_record_free_mem(); } void tearDown(void) { - size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT); - size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT); - printf("\n"); - unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD); - unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD); + esp_reent_cleanup(); //clean up some of the newlib's lazy allocations + unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD); } void app_main(void) { + + // _____ _ _ _____ ____ ____ + // |_ _|__ ___| |_ | | | ____| _ \ / ___| + // | |/ _ \/ __| __| | | | _| | | | | | + // | | __/\__ \ |_ | |___| |___| |_| | |___ + // |_|\___||___/\__| |_____|_____|____/ \____| + + printf("\n"); + printf(" _____ _ _ _____ ____ ____ \n"); + printf(" |_ _|__ ___| |_ | | | ____| _ \\ / ___|\n"); + printf(" | |/ _ \\/ __| __| | | | _| | | | | | \n"); + printf(" | | __/\\__ \\ |_ | |___| |___| |_| | |___ \n"); + printf(" |_|\\___||___/\\__| |_____|_____|____/ \\____|\n"); unity_run_menu(); } diff --git a/components/driver/test_apps/ledc/main/test_ledc.c b/components/driver/test_apps/ledc/main/test_ledc.c index e0249ee33a..fd7fda1880 100644 --- a/components/driver/test_apps/ledc/main/test_ledc.c +++ b/components/driver/test_apps/ledc/main/test_ledc.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,7 +37,11 @@ #if SOC_LEDC_SUPPORT_APB_CLOCK #define TEST_DEFAULT_CLK_CFG LEDC_USE_APB_CLK #elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK +#if SOC_CLK_TREE_SUPPORTED #define TEST_DEFAULT_CLK_CFG LEDC_USE_PLL_DIV_CLK +#else +#define TEST_DEFAULT_CLK_CFG LEDC_USE_XTAL_CLK +#endif #endif static ledc_channel_config_t initialize_channel_config(void) @@ -541,12 +545,13 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_ .speed_mode = speed_mode, .duty_resolution = timer_bit, .timer_num = timer, - .freq_hz = 5000, + .freq_hz = TEST_PWM_FREQ, .clk_cfg = TEST_DEFAULT_CLK_CFG, }; TEST_ESP_OK(ledc_channel_config(&ledc_ch_config)); TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); frequency_set_get(speed_mode, timer, 100, 100, 20); +#if SOC_CLK_TREE_SUPPORTED frequency_set_get(speed_mode, timer, 5000, 5000, 50); // Try a frequency that couldn't be exactly achieved, requires rounding uint32_t theoretical_freq = 9000; @@ -558,6 +563,7 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_ theoretical_freq = 9009; } frequency_set_get(speed_mode, timer, 9000, theoretical_freq, 50); +#endif // Pause and de-configure the timer so that it won't affect the following test cases TEST_ESP_OK(ledc_timer_pause(speed_mode, timer)); @@ -581,6 +587,7 @@ TEST_CASE("LEDC set and get frequency", "[ledc][timeout=60]") tear_testbench(); } +#if SOC_CLK_TREE_SUPPORTED static void timer_set_clk_src_and_freq_test(ledc_mode_t speed_mode, ledc_clk_cfg_t clk_src, uint32_t duty_res, uint32_t freq_hz) { @@ -648,6 +655,7 @@ TEST_CASE("LEDC timer select specific clock source", "[ledc]") tear_testbench(); } +#endif //SOC_CLK_TREE_SUPPORTED TEST_CASE("LEDC timer pause and resume", "[ledc]") { @@ -669,14 +677,14 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]") .speed_mode = test_speed_mode, .duty_resolution = LEDC_TIMER_13_BIT, .timer_num = LEDC_TIMER_0, - .freq_hz = 5000, + .freq_hz = TEST_PWM_FREQ, .clk_cfg = TEST_DEFAULT_CLK_CFG, }; TEST_ESP_OK(ledc_timer_config(&ledc_time_config)); vTaskDelay(10 / portTICK_PERIOD_MS); count = wave_count(1000); - TEST_ASSERT_INT16_WITHIN(5, 5000, count); + TEST_ASSERT_INT16_WITHIN(5, TEST_PWM_FREQ, count); //pause ledc timer, when pause it, will get no waveform count printf("Pause ledc timer\n"); @@ -690,14 +698,14 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]") TEST_ESP_OK(ledc_timer_resume(test_speed_mode, LEDC_TIMER_0)); vTaskDelay(10 / portTICK_PERIOD_MS); count = wave_count(1000); - TEST_ASSERT_UINT32_WITHIN(5, 5000, count); + TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ, count); //reset ledc timer printf("reset ledc timer\n"); TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0)); vTaskDelay(100 / portTICK_PERIOD_MS); count = wave_count(1000); - TEST_ASSERT_UINT32_WITHIN(5, 5000, count); + TEST_ASSERT_UINT32_WITHIN(5, TEST_PWM_FREQ, count); tear_testbench(); } diff --git a/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c b/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c index 3e45685b8d..40d5ac5989 100644 --- a/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c +++ b/components/driver/test_apps/legacy_pcnt_driver/main/test_legacy_pcnt.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,11 +13,13 @@ #include "driver/pcnt.h" #if SOC_LEDC_SUPPORTED #include "driver/ledc.h" +#include "soc/ledc_periph.h" #endif #include "esp_attr.h" #include "esp_log.h" #include "soc/gpio_periph.h" #include "soc/pcnt_struct.h" +#include "soc/pcnt_periph.h" #include "unity.h" #include "esp_rom_gpio.h" @@ -32,21 +34,6 @@ #define PCNT_CTRL_HIGH_LEVEL 1 #define PCNT_CTRL_LOW_LEVEL 0 -// The following items only used in the cases that involve LEDC -#if SOC_LEDC_SUPPORTED - -static QueueHandle_t pcnt_evt_queue = NULL; - -typedef struct { - int zero_times; - int h_limit; - int l_limit; - int h_threshold; - int l_threshold; - int filter_time; -} event_times; -#endif // SOC_LEDC_SUPPORTED - // test PCNT basic configuration TEST_CASE("PCNT_test_config", "[pcnt]") { @@ -108,14 +95,25 @@ TEST_CASE("PCNT_test_config", "[pcnt]") // The following test cases rely on the support of LEDC #if SOC_LEDC_SUPPORTED +// The following items only used in the cases that involve LEDC +static QueueHandle_t pcnt_evt_queue = NULL; + +typedef struct { + int zero_times; + int h_limit; + int l_limit; + int h_threshold; + int l_threshold; + int filter_time; +} event_times; static void pcnt_test_io_config(int ctrl_level) { // Connect internal signals using IO matrix. gpio_set_direction(PULSE_IO, GPIO_MODE_INPUT_OUTPUT); - esp_rom_gpio_connect_out_signal(PULSE_IO, LEDC_LS_SIG_OUT1_IDX, 0, 0); // LEDC_TIMER_1, LEDC_LOW_SPEED_MODE - esp_rom_gpio_connect_in_signal(PULSE_IO, PCNT_SIG_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0 - esp_rom_gpio_connect_in_signal(ctrl_level ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT, PCNT_CTRL_CH0_IN0_IDX, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0 + esp_rom_gpio_connect_out_signal(PULSE_IO, ledc_periph_signal[LEDC_LOW_SPEED_MODE].sig_out0_idx + 1, 0, 0); // LEDC_CHANNEL_1, LEDC_LOW_SPEED_MODE + esp_rom_gpio_connect_in_signal(PULSE_IO, pcnt_periph_signals.groups[0].units[0].channels[0].pulse_sig, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0 + esp_rom_gpio_connect_in_signal(ctrl_level ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT, pcnt_periph_signals.groups[0].units[0].channels[0].control_sig, 0); // PCNT_UNIT_0, PCNT_CHANNEL_0 } /* use LEDC to produce pulse for PCNT diff --git a/components/hal/esp32/include/hal/ledc_ll.h b/components/hal/esp32/include/hal/ledc_ll.h index 83e83b155c..e460ebe98b 100644 --- a/components/hal/esp32/include/hal/ledc_ll.h +++ b/components/hal/esp32/include/hal/ledc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" #include "soc/ledc_struct.h" +#include "soc/dport_reg.h" #ifdef __cplusplus extern "C" { @@ -40,6 +41,49 @@ extern "C" { ((SPEED) == LEDC_HIGH_SPEED_MODE && (CLK) == LEDC_USE_APB_CLK) \ ) +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + //resolve for compatibility +} /** * @brief Set LEDC low speed timer clock diff --git a/components/hal/esp32c2/include/hal/ledc_ll.h b/components/hal/esp32c2/include/hal/ledc_ll.h index 625ecdd7c9..e70282c9b7 100644 --- a/components/hal/esp32c2/include/hal/ledc_ll.h +++ b/components/hal/esp32c2/include/hal/ledc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,6 +11,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -34,6 +35,41 @@ extern "C" { #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + SYSTEM.perip_clk_en0.ledc_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + SYSTEM.perip_rst_en0.ledc_rst = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + //resolve for compatibility +} /** * @brief Set LEDC low speed timer clock diff --git a/components/hal/esp32c3/include/hal/ledc_ll.h b/components/hal/esp32c3/include/hal/ledc_ll.h index af623d7e18..373a3c679e 100644 --- a/components/hal/esp32c3/include/hal/ledc_ll.h +++ b/components/hal/esp32c3/include/hal/ledc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" #include "soc/ledc_struct.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,42 @@ extern "C" { #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + SYSTEM.perip_clk_en0.reg_ledc_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + SYSTEM.perip_rst_en0.reg_ledc_rst = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + //resolve for compatibility +} + /** * @brief Set LEDC low speed timer clock * diff --git a/components/hal/esp32c6/include/hal/ledc_ll.h b/components/hal/esp32c6/include/hal/ledc_ll.h index 74e3a63834..cc858d4dee 100644 --- a/components/hal/esp32c6/include/hal/ledc_ll.h +++ b/components/hal/esp32c6/include/hal/ledc_ll.h @@ -13,7 +13,9 @@ #include "soc/ledc_struct.h" #include "soc/ledc_reg.h" #include "soc/pcr_struct.h" +#include "soc/clk_tree_defs.h" #include "hal/assert.h" +#include "esp_rom_sys.h" //for sync issue workaround #ifdef __cplusplus extern "C" { @@ -27,15 +29,25 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) - -#define LEDC_LL_GLOBAL_CLOCKS { \ - LEDC_SLOW_CLK_PLL_DIV, \ - LEDC_SLOW_CLK_XTAL, \ - LEDC_SLOW_CLK_RC_FAST, \ - } +#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + PCR.ledc_conf.ledc_clk_en = enable; +} + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + PCR.ledc_conf.ledc_rst_en = enable; +} /** * @brief Enable LEDC function clock @@ -414,6 +426,35 @@ static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t sp hw->channel_gamma_group[speed_mode].channel[channel_num].wr_addr.gamma_wr_addr = duty_range; } +/** + * @brief Function to set fade parameters all-in-one for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + // To workaround sync issue + // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + + ledc_ll_set_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + + // To workaround sync issue + // This is to ensure the fade param in gamma_wr register can be written to the correct wr_addr + esp_rom_delay_us(5); +} + /** * @brief Set the total number of ranges in one fading * @@ -481,6 +522,29 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode *step = (val & LEDC_CH0_GAMMA_DUTY_NUM_M) >> LEDC_CH0_GAMMA_DUTY_NUM_S; } +/** + * @brief Get fade configurations for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir Pointer to accept fade direction value + * @param cycle Pointer to accept fade cycle value + * @param scale Pointer to accept fade scale value + * @param step Pointer to accept fade step value + * + * @return None + */ +static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) +{ + // On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue + // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization + ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); +} + /** * @brief Set the output enable * diff --git a/components/hal/esp32h2/include/hal/ledc_ll.h b/components/hal/esp32h2/include/hal/ledc_ll.h index d773079e66..81e8177b7b 100644 --- a/components/hal/esp32h2/include/hal/ledc_ll.h +++ b/components/hal/esp32h2/include/hal/ledc_ll.h @@ -13,7 +13,9 @@ #include "soc/ledc_struct.h" #include "soc/ledc_reg.h" #include "soc/pcr_struct.h" +#include "soc/clk_tree_defs.h" #include "hal/assert.h" +#include "esp_rom_sys.h" //for sync issue workaround #ifdef __cplusplus extern "C" { @@ -27,13 +29,23 @@ extern "C" { #define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) #define LEDC_LL_FRACTIONAL_BITS (8) #define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS -#define LEDC_LL_GLOBAL_CLOCKS { \ - LEDC_SLOW_CLK_PLL_DIV, \ - LEDC_SLOW_CLK_XTAL, \ - LEDC_SLOW_CLK_RC_FAST, \ - } +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + PCR.ledc_conf.ledc_clk_en = enable; +} +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + PCR.ledc_conf.ledc_rst_en = enable; +} /** * @brief Enable LEDC function clock @@ -412,6 +424,35 @@ static inline void ledc_ll_set_duty_range_wr_addr(ledc_dev_t *hw, ledc_mode_t sp hw->channel_gamma_group[speed_mode].channel[channel_num].wr_addr.gamma_wr_addr = duty_range; } +/** + * @brief Function to set fade parameters all-in-one for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + // To workaround sync issue + // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + + ledc_ll_set_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); + ledc_ll_set_duty_range_wr_addr(hw, speed_mode, channel_num, range); + + // To workaround sync issue + // This is to ensure the fade param in gamma_wr register can be written to the correct wr_addr + esp_rom_delay_us(5); +} + /** * @brief Set the total number of ranges in one fading * @@ -479,6 +520,29 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode *step = (val & LEDC_CH0_GAMMA_DUTY_NUM_M) >> LEDC_CH0_GAMMA_DUTY_NUM_S; } +/** + * @brief Get fade configurations for one range + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir Pointer to accept fade direction value + * @param cycle Pointer to accept fade cycle value + * @param scale Pointer to accept fade scale value + * @param step Pointer to accept fade step value + * + * @return None + */ +static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) +{ + // On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue + // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization + ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range); + esp_rom_delay_us(5); + ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step); +} + /** * @brief Set the output enable * diff --git a/components/hal/esp32p4/include/hal/clk_gate_ll.h b/components/hal/esp32p4/include/hal/clk_gate_ll.h index c5230a5b98..7cf2ea3be4 100644 --- a/components/hal/esp32p4/include/hal/clk_gate_ll.h +++ b/components/hal/esp32p4/include/hal/clk_gate_ll.h @@ -50,8 +50,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return HP_SYS_CLKRST_REG_CAM_CLK_EN; case PERIPH_SYSTIMER_MODULE: return HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN; - case PERIPH_LEDC_MODULE: - return HP_SYS_CLKRST_REG_LEDC_CLK_EN; case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_REG_ADC_CLK_EN; case PERIPH_PVT_MODULE: @@ -117,8 +115,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en return HP_SYS_CLKRST_REG_RST_EN_CAN1; case PERIPH_TWAI2_MODULE: return HP_SYS_CLKRST_REG_RST_EN_CAN2; - case PERIPH_LEDC_MODULE: - return HP_SYS_CLKRST_REG_RST_EN_LEDC; case PERIPH_LCD_MODULE: return HP_SYS_CLKRST_REG_RST_EN_LCDCAM; case PERIPH_SARADC_MODULE: @@ -188,8 +184,6 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) case PERIPH_CAM_MODULE: return HP_SYS_CLKRST_PERI_CLK_CTRL119_REG; case PERIPH_SYSTIMER_MODULE: - case PERIPH_LEDC_MODULE: - return HP_SYS_CLKRST_PERI_CLK_CTRL21_REG; case PERIPH_SARADC_MODULE: return HP_SYS_CLKRST_PERI_CLK_CTRL22_REG; case PERIPH_PVT_MODULE: @@ -232,7 +226,6 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) case PERIPH_TWAI0_MODULE: case PERIPH_TWAI1_MODULE: case PERIPH_TWAI2_MODULE: - case PERIPH_LEDC_MODULE: case PERIPH_CAM_MODULE: case PERIPH_SARADC_MODULE: case PERIPH_AES_MODULE: diff --git a/components/hal/esp32p4/include/hal/ledc_ll.h b/components/hal/esp32p4/include/hal/ledc_ll.h new file mode 100644 index 0000000000..ca655dabb5 --- /dev/null +++ b/components/hal/esp32p4/include/hal/ledc_ll.h @@ -0,0 +1,568 @@ +/* + * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for LEDC register operations. +// Note that most of the register operations in this layer are non-atomic operations. + +#pragma once + +#include "hal/assert.h" +#include "hal/ledc_types.h" +#include "soc/ledc_struct.h" +#include "soc/ledc_reg.h" +#include "soc/clk_tree_defs.h" +#include "soc/hp_sys_clkrst_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define LEDC_LL_GET_HW() &LEDC + +#define LEDC_LL_DUTY_NUM_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V) +#define LEDC_LL_DUTY_CYCLE_MAX (LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V) +#define LEDC_LL_DUTY_SCALE_MAX (LEDC_CH0_GAMMA_RANGE0_SCALE_V) +#define LEDC_LL_HPOINT_VAL_MAX (LEDC_HPOINT_CH0_V) +#define LEDC_LL_FRACTIONAL_BITS (8) +#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1) +#define LEDC_LL_GLOBAL_CLOCKS SOC_LEDC_CLKS + +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + HP_SYS_CLKRST.soc_clk_ctrl3.reg_ledc_apb_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_ledc = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + (void)hw; + HP_SYS_CLKRST.peri_clk_ctrl22.reg_ledc_clk_en = en; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_clock(__VA_ARGS__) + +/** + * @brief Set LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_set_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t slow_clk_sel) +{ + (void) hw; + uint32_t clk_sel_val = 3; + switch (slow_clk_sel) + { + case LEDC_SLOW_CLK_XTAL: + clk_sel_val = 0; + break; + case LEDC_SLOW_CLK_RC_FAST: + clk_sel_val = 1; + break; + case LEDC_SLOW_CLK_PLL_DIV: + clk_sel_val = 2; + break; + default: + abort(); + } + + HP_SYS_CLKRST.peri_clk_ctrl22.reg_ledc_clk_src_sel = clk_sel_val; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_set_slow_clk_sel(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_set_slow_clk_sel(__VA_ARGS__) + +/** + * @brief Get LEDC low speed timer clock + * + * @param hw Beginning address of the peripheral registers + * @param slow_clk_sel LEDC low speed timer clock source + * + * @return None + */ +static inline void ledc_ll_get_slow_clk_sel(ledc_dev_t *hw, ledc_slow_clk_sel_t *slow_clk_sel) +{ + (void) hw; + switch (HP_SYS_CLKRST.peri_clk_ctrl22.reg_ledc_clk_src_sel) + { + case 0: + *slow_clk_sel = LEDC_SLOW_CLK_XTAL; + break; + case 1: + *slow_clk_sel = LEDC_SLOW_CLK_RC_FAST; + break; + case 2: + *slow_clk_sel = LEDC_SLOW_CLK_PLL_DIV; + break; + default: + abort(); + } +} + +/** + * @brief Update LEDC low speed timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_ls_timer_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.para_up = 1; + // Here, we don't wait for the bit gets cleared since it can take quite long depends on the pwm frequency +} + +/** + * @brief Reset LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_rst(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 1; + hw->timer_group[speed_mode].timer[timer_sel].conf.rst = 0; +} + +/** + * @brief Pause LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_pause(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 1; +} + +/** + * @brief Resume LEDC timer + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_timer_resume(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.pause = 0; +} + +/** + * @brief Set LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_set_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t clock_divider) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div = clock_divider; +} + +/** + * @brief Get LEDC timer clock divider + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clock_divider Timer clock divide value, the timer clock is divided from the selected clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *clock_divider) +{ + *clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clk_div; +} + +/** + * @brief Get LEDC timer clock source + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param clk_src Pointer to accept the timer clock source + * + * @return None + */ +static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src) +{ + // The target has no timer-specific clock source option + HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0); + *clk_src = LEDC_SCLK; +} + +/** + * @brief Set LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Resolution of duty setting in number of bits. The range of duty values is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t duty_resolution) +{ + hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res = duty_resolution; +} + +/** + * @brief Get LEDC duty resolution + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param duty_resolution Pointer to accept the resolution of duty setting in number of bits. + * + * @return None + */ +static inline void ledc_ll_get_duty_resolution(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *duty_resolution) +{ + *duty_resolution = hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res; +} + +/** + * @brief Get LEDC max duty + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * @param max_duty Pointer to accept the max duty + * + * @return None + */ +static inline void ledc_ll_get_max_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t *max_duty) +{ + *max_duty = (1 << (hw->timer_group[speed_mode].timer[timer_sel].conf.duty_res)); +} + +/** + * @brief Update channel configure when select low speed mode + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_ls_channel_update(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.para_up = 1; +} + +/** + * @brief Set LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param hpoint_val LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_set_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t hpoint_val) +{ + hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint = hpoint_val; +} + +/** + * @brief Get LEDC hpoint value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param hpoint_val Pointer to accept the LEDC hpoint value(max: 0xfffff) + * + * @return None + */ +static inline void ledc_ll_get_hpoint(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *hpoint_val) +{ + *hpoint_val = hw->channel_group[speed_mode].channel[channel_num].hpoint.hpoint; +} + +/** + * @brief Set LEDC the integer part of duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_val LEDC duty value, the range of duty setting is [0, (2**duty_resolution)] + * + * @return None + */ +static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t duty_val) +{ + hw->channel_group[speed_mode].channel[channel_num].duty_init.duty = duty_val << 4; +} + +/** + * @brief Get LEDC duty value + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_val Pointer to accept the LEDC duty value + * + * @return None + */ +static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val) +{ + *duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4); +} + +/** + * @brief Function to set fade parameters all-in-one + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir LEDC duty change direction, increase or decrease + * @param cycle The duty cycles + * @param scale The step scale + * @param step The number of increased or decreased times + * + * @return None + */ +static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) +{ + ledc_channel_gamma_fade_param_t range_param = { + .duty_inc = dir, + .duty_cycle = cycle, + .scale = scale, + .duty_num = step, + }; + LEDC_GAMMA_RAM.channel[channel_num].entry[range].val = range_param.val; +} + +/** + * @brief Set the total number of ranges in one fading + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range_num Total number of ranges (1 - SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX) of the fading configured + * + * @return None + */ +static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num) +{ + hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num; +} + +/** + * @brief Get the total number of ranges in one fading + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range_num Pointer to accept fade range number + * + * @return None + */ +static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num) +{ + *range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num; +} + +/** + * @brief Get fade configurations in gamma_rd register + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param range Gamma fade range index to get, 0 ~ SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + * @param dir Pointer to accept fade direction value + * @param cycle Pointer to accept fade cycle value + * @param scale Pointer to accept fade scale value + * @param step Pointer to accept fade step value + * + * @return None + */ +static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) +{ + ledc_channel_gamma_fade_param_t range_param = { + .val = LEDC_GAMMA_RAM.channel[channel_num].entry[range].val, + }; + + *dir = range_param.duty_inc; + *cycle = range_param.duty_cycle; + *scale = range_param.scale; + *step = range_param.duty_num; +} + +/** + * @brief Set the output enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param sig_out_en The output enable status + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_sig_out_en(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool sig_out_en) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.sig_out_en = sig_out_en; +} + +/** + * @brief Set the duty start + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param duty_start The duty start + * + * @return None + */ +static inline void ledc_ll_set_duty_start(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool duty_start) +{ + hw->channel_group[speed_mode].channel[channel_num].conf1.duty_start = duty_start; +} + +/** + * @brief Set output idle level + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param idle_level The output idle level + * + * @return None + */ +__attribute__((always_inline)) +static inline void ledc_ll_set_idle_level(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t idle_level) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.idle_lv = idle_level & 0x1; +} + +/** + * @brief Set fade end interrupt enable + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param fade_end_intr_en The fade end interrupt enable status + * + * @return None + */ +static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, bool fade_end_intr_en) +{ + uint32_t value = hw->int_ena.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_ena.val = fade_end_intr_en ? (value | BIT(int_en_base + channel_num)) : (value & (~(BIT(int_en_base + channel_num)))); +} + +/** + * @brief Get fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param intr_status The fade end interrupt status + * + * @return None + */ +static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, uint32_t *intr_status) +{ + uint32_t value = hw->int_st.val; + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + *intr_status = (value >> int_en_base) & 0xff; +} + +/** + * @brief Clear fade end interrupt status + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * + * @return None + */ +static inline void ledc_ll_clear_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num) +{ + uint32_t int_en_base = LEDC_DUTY_CHNG_END_CH0_INT_ENA_S; + hw->int_clr.val = BIT(int_en_base + channel_num); +} + +/** + * @brief Set timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param timer_sel LEDC timer index (0-3), select from ledc_timer_t + * + * @return None + */ +static inline void ledc_ll_bind_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t timer_sel) +{ + hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel = timer_sel; +} + +/** + * @brief Get timer index of the specified channel + * + * @param hw Beginning address of the peripheral registers + * @param speed_mode LEDC speed_mode, low-speed mode only + * @param channel_num LEDC channel index (0-5), select from ledc_channel_t + * @param timer_sel Pointer to accept the LEDC timer index + * + * @return None + */ +static inline void ledc_ll_get_channel_timer(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, ledc_timer_t *timer_sel) +{ + *timer_sel = (ledc_timer_t)(hw->channel_group[speed_mode].channel[channel_num].conf0.timer_sel); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32s2/include/hal/ledc_ll.h b/components/hal/esp32s2/include/hal/ledc_ll.h index ff7edd4c18..a9ed6babcd 100644 --- a/components/hal/esp32s2/include/hal/ledc_ll.h +++ b/components/hal/esp32s2/include/hal/ledc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" #include "soc/ledc_struct.h" +#include "soc/dport_reg.h" #include "hal/assert.h" #ifdef __cplusplus @@ -40,6 +41,49 @@ extern "C" { #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + if (enable) { + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + } else { + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST); + } +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + //resolve for compatibility +} /** * @brief Set LEDC low speed timer clock diff --git a/components/hal/esp32s3/include/hal/ledc_ll.h b/components/hal/esp32s3/include/hal/ledc_ll.h index 4a7ef5a6da..35c374c10b 100644 --- a/components/hal/esp32s3/include/hal/ledc_ll.h +++ b/components/hal/esp32s3/include/hal/ledc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "hal/ledc_types.h" #include "soc/ledc_periph.h" #include "soc/ledc_struct.h" +#include "soc/system_struct.h" #include "hal/assert.h" #ifdef __cplusplus @@ -35,6 +36,41 @@ extern "C" { #define LEDC_LL_GLOBAL_CLK_DEFAULT LEDC_SLOW_CLK_RC_FAST +/** + * @brief Enable peripheral register clock + * + * @param enable Enable/Disable + */ +static inline void ledc_ll_enable_bus_clock(bool enable) { + SYSTEM.perip_clk_en0.ledc_clk_en = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_bus_clock(__VA_ARGS__) + +/** + * @brief Reset whole peripheral register to init value defined by HW design + */ +static inline void ledc_ll_enable_reset_reg(bool enable) { + SYSTEM.perip_rst_en0.ledc_rst = enable; +} + +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__) + +/** + * @brief Enable LEDC function clock + * + * @param hw Beginning address of the peripheral registers + * @param en True to enable, false to disable + * + * @return None + */ +static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) { + //resolve for compatibility +} /** * @brief Set LEDC low speed timer clock diff --git a/components/hal/include/hal/ledc_hal.h b/components/hal/include/hal/ledc_hal.h index d01f0a8b3a..b914cb5778 100644 --- a/components/hal/include/hal/ledc_hal.h +++ b/components/hal/include/hal/ledc_hal.h @@ -302,50 +302,6 @@ void ledc_hal_set_hpoint(ledc_hal_context_t *hal, ledc_channel_t channel_num, ui */ void ledc_hal_get_duty(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t *duty_val); -/** - * @brief Set LEDC duty change direction - * - * @param hal Context of the HAL layer - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_direction LEDC duty change direction, increase or decrease - * - * @return None - */ -void ledc_hal_set_duty_direction(ledc_hal_context_t *hal, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction); - -/** - * @brief Set the number of increased or decreased times - * - * @param hal Context of the HAL layer - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_num The number of increased or decreased times - * - * @return None - */ -void ledc_hal_set_duty_num(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_num); - -/** - * @brief Set the duty cycles of increase or decrease - * - * @param hal Context of the HAL layer - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_cycle The duty cycles - * - * @return None - */ -void ledc_hal_set_duty_cycle(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_cycle); - -/** - * @brief Set the step scale of increase or decrease - * - * @param hal Context of the HAL layer - * @param channel_num LEDC channel index (0-7), select from ledc_channel_t - * @param duty_scale The step scale - * - * @return None - */ -void ledc_hal_set_duty_scale(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_scale); - /** * @brief Function to set fade parameters all-in-one * diff --git a/components/hal/ledc_hal.c b/components/hal/ledc_hal.c index d92ddbb5f1..6971957124 100644 --- a/components/hal/ledc_hal.c +++ b/components/hal/ledc_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -59,12 +59,6 @@ void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_ #if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED void ledc_hal_get_fade_param(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step) { - ledc_ll_set_duty_range_rd_addr(hal->dev, hal->speed_mode, channel_num, range); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - // On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue - // To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization - esp_rom_delay_us(5); -#endif - ledc_ll_get_fade_param(hal->dev, hal->speed_mode, channel_num, dir, cycle, scale, step); + ledc_ll_get_fade_param_range(hal->dev, hal->speed_mode, channel_num, range, dir, cycle, scale, step); } #endif diff --git a/components/hal/ledc_hal_iram.c b/components/hal/ledc_hal_iram.c index 2fd83606da..4cff5cfcd7 100644 --- a/components/hal/ledc_hal_iram.c +++ b/components/hal/ledc_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,46 +36,11 @@ void ledc_hal_get_duty(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint ledc_ll_get_duty(hal->dev, hal->speed_mode, channel_num, duty_val); } -void ledc_hal_set_duty_direction(ledc_hal_context_t *hal, ledc_channel_t channel_num, ledc_duty_direction_t duty_direction) -{ - ledc_ll_set_duty_direction(hal->dev, hal->speed_mode, channel_num, duty_direction); -} - -void ledc_hal_set_duty_num(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_num) -{ - ledc_ll_set_duty_num(hal->dev, hal->speed_mode, channel_num, duty_num); -} - -void ledc_hal_set_duty_cycle(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_cycle) -{ - ledc_ll_set_duty_cycle(hal->dev, hal->speed_mode, channel_num, duty_cycle); -} - -void ledc_hal_set_duty_scale(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_scale) -{ - ledc_ll_set_duty_scale(hal->dev, hal->speed_mode, channel_num, duty_scale); -} - void ledc_hal_set_fade_param(const ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t range, uint32_t dir, uint32_t cycle, uint32_t scale, uint32_t step) { #if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED HAL_ASSERT(range < SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX); - -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - // To workaround sync issue (C6, H2) - // This is to ensure the fade param write to the gamma_wr register would not mess up the last wr_addr - ledc_ll_set_duty_range_wr_addr(hal->dev, hal->speed_mode, channel_num, range); - esp_rom_delay_us(5); -#endif - - ledc_ll_set_fade_param(hal->dev, hal->speed_mode, channel_num, dir, cycle, scale, step); - ledc_ll_set_duty_range_wr_addr(hal->dev, hal->speed_mode, channel_num, range); -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 - // To workaround sync issue (C6, H2) - // This is to ensure the fade param in gamma_wr register can be written to the correct wr_addr - esp_rom_delay_us(5); -#endif - + ledc_ll_set_fade_param_range(hal->dev, hal->speed_mode, channel_num, range, dir, cycle, scale, step); #else // !SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED HAL_ASSERT(range == 0); ledc_ll_set_fade_param(hal->dev, hal->speed_mode, channel_num, dir, cycle, scale, step); @@ -83,10 +48,6 @@ void ledc_hal_set_fade_param(const ledc_hal_context_t *hal, ledc_channel_t chann } #if SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED -void ledc_hal_set_duty_range_wr_addr(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t duty_range) -{ - ledc_ll_set_duty_range_wr_addr(hal->dev, hal->speed_mode, channel_num, duty_range); -} void ledc_hal_set_range_number(ledc_hal_context_t *hal, ledc_channel_t channel_num, uint32_t range_num) { diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index e6d6e6a391..87d640b512 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -79,6 +79,10 @@ config SOC_GPSPI_SUPPORTED bool default y +config SOC_LEDC_SUPPORTED + bool + default y + config SOC_I2C_SUPPORTED bool default y @@ -525,19 +529,27 @@ config SOC_LEDC_SUPPORT_XTAL_CLOCK config SOC_LEDC_CHANNEL_NUM int - default 6 + default 8 config SOC_LEDC_TIMER_BIT_WIDTH int default 20 +config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED + bool + default y + +config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX + int + default 16 + config SOC_LEDC_SUPPORT_FADE_STOP bool default y -config SOC_LEDC_GAMMA_FADE_RANGE_MAX +config SOC_LEDC_FADE_PARAMS_BIT_WIDTH int - default 16 + default 10 config SOC_MMU_PAGE_SIZE_CONFIGURABLE bool diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h index 5319a235dd..69084671eb 100644 --- a/components/soc/esp32p4/include/soc/clk_tree_defs.h +++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h @@ -485,7 +485,6 @@ typedef enum { //////////////////////////////////////////////////LEDC///////////////////////////////////////////////////////////////// -//TODO: IDF-6510 /** * @brief Array initializer for all supported clock sources of LEDC */ @@ -496,11 +495,9 @@ typedef enum { */ typedef enum { LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ + LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - - LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */ } soc_periph_ledc_clk_src_legacy_t; //////////////////////////////////////////////////PARLIO//////////////////////////////////////////////////////////////// diff --git a/components/soc/esp32p4/include/soc/ledc_reg.h b/components/soc/esp32p4/include/soc/ledc_reg.h index 220f4a1c63..bd9d80ad45 100644 --- a/components/soc/esp32p4/include/soc/ledc_reg.h +++ b/components/soc/esp32p4/include/soc/ledc_reg.h @@ -11,12 +11,6 @@ extern "C" { #endif -/** - * TODO: IDF-6510 - * Please note, some xxx_CHn_xx registers, their fields are still named with xx_CH0_xx - * e.g. LEDC_CH1_CONF0_REG and LEDC_TIMER_SEL_CH0 - */ - /** LEDC_CH0_CONF0_REG register * Configuration register 0 for channel 0 */ @@ -133,785 +127,785 @@ extern "C" { * Configuration register 0 for channel 1 */ #define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 1 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH1 0x00000003U +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003U +#define LEDC_TIMER_SEL_CH1_S 0 +/** LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 1.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH1_S 2 +/** LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 1 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH1 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001U +#define LEDC_IDLE_LV_CH1_S 3 +/** LEDC_PARA_UP_CH1 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH1, LEDC_DUTY_START_CH1, * LEDC_SIG_OUT_EN_CH1, LEDC_TIMER_SEL_CH1, LEDC_DUTY_NUM_CH1, LEDC_DUTY_CYCLE_CH1, * LEDC_DUTY_SCALE_CH1, LEDC_DUTY_INC_CH1, and LEDC_OVF_CNT_EN_CH1 fields for channel * 1, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001U +#define LEDC_PARA_UP_CH1_S 4 +/** LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH1_INT interrupt * will be triggered when channel 1 overflows for (LEDC_OVF_NUM_CH1 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH1 0x000003FFU +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FFU +#define LEDC_OVF_NUM_CH1_S 5 +/** LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 1.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH1_S 15 +/** LEDC_OVF_CNT_RESET_CH1 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 1.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH1_S 16 /** LEDC_CH1_HPOINT_REG register * High point register for channel 1 */ #define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH1 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 1. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH1 0x000FFFFFU +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x000FFFFFU +#define LEDC_HPOINT_CH1_S 0 /** LEDC_CH1_DUTY_REG register * Initial duty cycle register for channel 1 */ #define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH1 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 1. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH1 0x01FFFFFFU +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_S 0 /** LEDC_CH1_CONF1_REG register * Configuration register 1 for channel 1 */ #define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH1 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001U +#define LEDC_DUTY_START_CH1_S 31 /** LEDC_CH1_DUTY_R_REG register * Current duty cycle register for channel 1 */ #define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH1_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 1. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH1_R 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_M (LEDC_DUTY_CH1_R_V << LEDC_DUTY_CH1_R_S) +#define LEDC_DUTY_CH1_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH1_R_S 0 /** LEDC_CH2_CONF0_REG register * Configuration register 0 for channel 2 */ #define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 2 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH2 0x00000003U +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003U +#define LEDC_TIMER_SEL_CH2_S 0 +/** LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 2.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH2_S 2 +/** LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 2 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH2 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001U +#define LEDC_IDLE_LV_CH2_S 3 +/** LEDC_PARA_UP_CH2 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH2, LEDC_DUTY_START_CH2, * LEDC_SIG_OUT_EN_CH2, LEDC_TIMER_SEL_CH2, LEDC_DUTY_NUM_CH2, LEDC_DUTY_CYCLE_CH2, * LEDC_DUTY_SCALE_CH2, LEDC_DUTY_INC_CH2, and LEDC_OVF_CNT_EN_CH2 fields for channel * 2, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001U +#define LEDC_PARA_UP_CH2_S 4 +/** LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH2_INT interrupt * will be triggered when channel 2 overflows for (LEDC_OVF_NUM_CH2 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH2 0x000003FFU +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FFU +#define LEDC_OVF_NUM_CH2_S 5 +/** LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 2.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH2_S 15 +/** LEDC_OVF_CNT_RESET_CH2 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 2.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH2_S 16 /** LEDC_CH2_HPOINT_REG register * High point register for channel 2 */ #define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH2 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 2. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH2 0x000FFFFFU +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x000FFFFFU +#define LEDC_HPOINT_CH2_S 0 /** LEDC_CH2_DUTY_REG register * Initial duty cycle register for channel 2 */ #define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH2 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 2. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH2 0x01FFFFFFU +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_S 0 /** LEDC_CH2_CONF1_REG register * Configuration register 1 for channel 2 */ #define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH2 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001U +#define LEDC_DUTY_START_CH2_S 31 /** LEDC_CH2_DUTY_R_REG register * Current duty cycle register for channel 2 */ #define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH2_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 2. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH2_R 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_M (LEDC_DUTY_CH2_R_V << LEDC_DUTY_CH2_R_S) +#define LEDC_DUTY_CH2_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH2_R_S 0 /** LEDC_CH3_CONF0_REG register * Configuration register 0 for channel 3 */ #define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 3 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH3 0x00000003U +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003U +#define LEDC_TIMER_SEL_CH3_S 0 +/** LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 3.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH3_S 2 +/** LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 3 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH3 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001U +#define LEDC_IDLE_LV_CH3_S 3 +/** LEDC_PARA_UP_CH3 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH3, LEDC_DUTY_START_CH3, * LEDC_SIG_OUT_EN_CH3, LEDC_TIMER_SEL_CH3, LEDC_DUTY_NUM_CH3, LEDC_DUTY_CYCLE_CH3, * LEDC_DUTY_SCALE_CH3, LEDC_DUTY_INC_CH3, and LEDC_OVF_CNT_EN_CH3 fields for channel * 3, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001U +#define LEDC_PARA_UP_CH3_S 4 +/** LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH3_INT interrupt * will be triggered when channel 3 overflows for (LEDC_OVF_NUM_CH3 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH3 0x000003FFU +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FFU +#define LEDC_OVF_NUM_CH3_S 5 +/** LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 3.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH3_S 15 +/** LEDC_OVF_CNT_RESET_CH3 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 3.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH3_S 16 /** LEDC_CH3_HPOINT_REG register * High point register for channel 3 */ #define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH3 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 3. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH3 0x000FFFFFU +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x000FFFFFU +#define LEDC_HPOINT_CH3_S 0 /** LEDC_CH3_DUTY_REG register * Initial duty cycle register for channel 3 */ #define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH3 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 3. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH3 0x01FFFFFFU +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_S 0 /** LEDC_CH3_CONF1_REG register * Configuration register 1 for channel 3 */ #define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH3 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001U +#define LEDC_DUTY_START_CH3_S 31 /** LEDC_CH3_DUTY_R_REG register * Current duty cycle register for channel 3 */ #define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH3_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 3. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH3_R 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_M (LEDC_DUTY_CH3_R_V << LEDC_DUTY_CH3_R_S) +#define LEDC_DUTY_CH3_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH3_R_S 0 /** LEDC_CH4_CONF0_REG register * Configuration register 0 for channel 4 */ #define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 4 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH4 0x00000003U +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003U +#define LEDC_TIMER_SEL_CH4_S 0 +/** LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 4.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH4_S 2 +/** LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 4 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH4 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001U +#define LEDC_IDLE_LV_CH4_S 3 +/** LEDC_PARA_UP_CH4 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH4, LEDC_DUTY_START_CH4, * LEDC_SIG_OUT_EN_CH4, LEDC_TIMER_SEL_CH4, LEDC_DUTY_NUM_CH4, LEDC_DUTY_CYCLE_CH4, * LEDC_DUTY_SCALE_CH4, LEDC_DUTY_INC_CH4, and LEDC_OVF_CNT_EN_CH4 fields for channel * 4, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001U +#define LEDC_PARA_UP_CH4_S 4 +/** LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH4_INT interrupt * will be triggered when channel 4 overflows for (LEDC_OVF_NUM_CH4 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH4 0x000003FFU +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FFU +#define LEDC_OVF_NUM_CH4_S 5 +/** LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 4.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH4_S 15 +/** LEDC_OVF_CNT_RESET_CH4 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 4.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH4_S 16 /** LEDC_CH4_HPOINT_REG register * High point register for channel 4 */ #define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH4 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 4. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH4 0x000FFFFFU +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x000FFFFFU +#define LEDC_HPOINT_CH4_S 0 /** LEDC_CH4_DUTY_REG register * Initial duty cycle register for channel 4 */ #define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH4 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 4. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH4 0x01FFFFFFU +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_S 0 /** LEDC_CH4_CONF1_REG register * Configuration register 1 for channel 4 */ #define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH4 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001U +#define LEDC_DUTY_START_CH4_S 31 /** LEDC_CH4_DUTY_R_REG register * Current duty cycle register for channel 4 */ #define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH4_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 4. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH4_R 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_M (LEDC_DUTY_CH4_R_V << LEDC_DUTY_CH4_R_S) +#define LEDC_DUTY_CH4_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH4_R_S 0 /** LEDC_CH5_CONF0_REG register * Configuration register 0 for channel 5 */ #define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 5 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH5 0x00000003U +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003U +#define LEDC_TIMER_SEL_CH5_S 0 +/** LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 5.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH5_S 2 +/** LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 5 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH5 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001U +#define LEDC_IDLE_LV_CH5_S 3 +/** LEDC_PARA_UP_CH5 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH5, LEDC_DUTY_START_CH5, * LEDC_SIG_OUT_EN_CH5, LEDC_TIMER_SEL_CH5, LEDC_DUTY_NUM_CH5, LEDC_DUTY_CYCLE_CH5, * LEDC_DUTY_SCALE_CH5, LEDC_DUTY_INC_CH5, and LEDC_OVF_CNT_EN_CH5 fields for channel * 5, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001U +#define LEDC_PARA_UP_CH5_S 4 +/** LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH5_INT interrupt * will be triggered when channel 5 overflows for (LEDC_OVF_NUM_CH5 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH5 0x000003FFU +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FFU +#define LEDC_OVF_NUM_CH5_S 5 +/** LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 5.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH5_S 15 +/** LEDC_OVF_CNT_RESET_CH5 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 5.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH5_S 16 /** LEDC_CH5_HPOINT_REG register * High point register for channel 5 */ #define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH5 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 5. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH5 0x000FFFFFU +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x000FFFFFU +#define LEDC_HPOINT_CH5_S 0 /** LEDC_CH5_DUTY_REG register * Initial duty cycle register for channel 5 */ #define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH5 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 5. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH5 0x01FFFFFFU +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_S 0 /** LEDC_CH5_CONF1_REG register * Configuration register 1 for channel 5 */ #define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH5 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001U +#define LEDC_DUTY_START_CH5_S 31 /** LEDC_CH5_DUTY_R_REG register * Current duty cycle register for channel 5 */ #define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH5_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 5. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH5_R 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_M (LEDC_DUTY_CH5_R_V << LEDC_DUTY_CH5_R_S) +#define LEDC_DUTY_CH5_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH5_R_S 0 /** LEDC_CH6_CONF0_REG register * Configuration register 0 for channel 6 */ #define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 6 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH6 0x00000003U +#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) +#define LEDC_TIMER_SEL_CH6_V 0x00000003U +#define LEDC_TIMER_SEL_CH6_S 0 +/** LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 6.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) +#define LEDC_SIG_OUT_EN_CH6_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH6_S 2 +/** LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 6 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH6 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH6 (BIT(3)) +#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) +#define LEDC_IDLE_LV_CH6_V 0x00000001U +#define LEDC_IDLE_LV_CH6_S 3 +/** LEDC_PARA_UP_CH6 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH6, LEDC_DUTY_START_CH6, * LEDC_SIG_OUT_EN_CH6, LEDC_TIMER_SEL_CH6, LEDC_DUTY_NUM_CH6, LEDC_DUTY_CYCLE_CH6, * LEDC_DUTY_SCALE_CH6, LEDC_DUTY_INC_CH6, and LEDC_OVF_CNT_EN_CH6 fields for channel * 6, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH6 (BIT(4)) +#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) +#define LEDC_PARA_UP_CH6_V 0x00000001U +#define LEDC_PARA_UP_CH6_S 4 +/** LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH6_INT interrupt * will be triggered when channel 6 overflows for (LEDC_OVF_NUM_CH6 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH6 0x000003FFU +#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) +#define LEDC_OVF_NUM_CH6_V 0x000003FFU +#define LEDC_OVF_NUM_CH6_S 5 +/** LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 6.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) +#define LEDC_OVF_CNT_EN_CH6_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH6_S 15 +/** LEDC_OVF_CNT_RESET_CH6 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 6.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) +#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH6_S 16 /** LEDC_CH6_HPOINT_REG register * High point register for channel 6 */ #define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH6 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 6. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH6 0x000FFFFFU +#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) +#define LEDC_HPOINT_CH6_V 0x000FFFFFU +#define LEDC_HPOINT_CH6_S 0 /** LEDC_CH6_DUTY_REG register * Initial duty cycle register for channel 6 */ #define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH6 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 6. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH6 0x01FFFFFFU +#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) +#define LEDC_DUTY_CH6_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_S 0 /** LEDC_CH6_CONF1_REG register * Configuration register 1 for channel 6 */ #define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH6 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH6 (BIT(31)) +#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) +#define LEDC_DUTY_START_CH6_V 0x00000001U +#define LEDC_DUTY_START_CH6_S 31 /** LEDC_CH6_DUTY_R_REG register * Current duty cycle register for channel 6 */ #define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH6_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 6. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH6_R 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_M (LEDC_DUTY_CH6_R_V << LEDC_DUTY_CH6_R_S) +#define LEDC_DUTY_CH6_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH6_R_S 0 /** LEDC_CH7_CONF0_REG register * Configuration register 0 for channel 7 */ #define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) -/** LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; +/** LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel 7 selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ -#define LEDC_TIMER_SEL_CH0 0x00000003U -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003U -#define LEDC_TIMER_SEL_CH0_S 0 -/** LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; +#define LEDC_TIMER_SEL_CH7 0x00000003U +#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) +#define LEDC_TIMER_SEL_CH7_V 0x00000003U +#define LEDC_TIMER_SEL_CH7_S 0 +/** LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel 7.\\0: Signal output * disable\\1: Signal output enable */ -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001U -#define LEDC_SIG_OUT_EN_CH0_S 2 -/** LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; +#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) +#define LEDC_SIG_OUT_EN_CH7_V 0x00000001U +#define LEDC_SIG_OUT_EN_CH7_S 2 +/** LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; * Configures the output value when channel 7 is inactive. Valid only when * LEDC_SIG_OUT_EN_CH7 is 0.\\0: Output level is low\\1: Output level is high */ -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001U -#define LEDC_IDLE_LV_CH0_S 3 -/** LEDC_PARA_UP_CH0 : WT; bitpos: [4]; default: 0; +#define LEDC_IDLE_LV_CH7 (BIT(3)) +#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) +#define LEDC_IDLE_LV_CH7_V 0x00000001U +#define LEDC_IDLE_LV_CH7_S 3 +/** LEDC_PARA_UP_CH7 : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CH7, LEDC_DUTY_START_CH7, * LEDC_SIG_OUT_EN_CH7, LEDC_TIMER_SEL_CH7, LEDC_DUTY_NUM_CH7, LEDC_DUTY_CYCLE_CH7, * LEDC_DUTY_SCALE_CH7, LEDC_DUTY_INC_CH7, and LEDC_OVF_CNT_EN_CH7 fields for channel * 7, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001U -#define LEDC_PARA_UP_CH0_S 4 -/** LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; +#define LEDC_PARA_UP_CH7 (BIT(4)) +#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) +#define LEDC_PARA_UP_CH7_V 0x00000001U +#define LEDC_PARA_UP_CH7_S 4 +/** LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH7_INT interrupt * will be triggered when channel 7 overflows for (LEDC_OVF_NUM_CH7 + 1) times. */ -#define LEDC_OVF_NUM_CH0 0x000003FFU -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FFU -#define LEDC_OVF_NUM_CH0_S 5 -/** LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; +#define LEDC_OVF_NUM_CH7 0x000003FFU +#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) +#define LEDC_OVF_NUM_CH7_V 0x000003FFU +#define LEDC_OVF_NUM_CH7_S 5 +/** LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel 7.\\0: Disable\\1: Enable */ -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001U -#define LEDC_OVF_CNT_EN_CH0_S 15 -/** LEDC_OVF_CNT_RESET_CH0 : WT; bitpos: [16]; default: 0; +#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) +#define LEDC_OVF_CNT_EN_CH7_V 0x00000001U +#define LEDC_OVF_CNT_EN_CH7_S 15 +/** LEDC_OVF_CNT_RESET_CH7 : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel 7.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001U -#define LEDC_OVF_CNT_RESET_CH0_S 16 +#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) +#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001U +#define LEDC_OVF_CNT_RESET_CH7_S 16 /** LEDC_CH7_HPOINT_REG register * High point register for channel 7 */ #define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) -/** LEDC_HPOINT_CH0 : R/W; bitpos: [19:0]; default: 0; +/** LEDC_HPOINT_CH7 : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel 7. The output value changes to * high when the selected timers has reached the value specified by this register. */ -#define LEDC_HPOINT_CH0 0x000FFFFFU -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x000FFFFFU -#define LEDC_HPOINT_CH0_S 0 +#define LEDC_HPOINT_CH7 0x000FFFFFU +#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) +#define LEDC_HPOINT_CH7_V 0x000FFFFFU +#define LEDC_HPOINT_CH7_S 0 /** LEDC_CH7_DUTY_REG register * Initial duty cycle register for channel 7 */ #define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) -/** LEDC_DUTY_CH0 : R/W; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH7 : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel 7. */ -#define LEDC_DUTY_CH0 0x01FFFFFFU -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_S 0 +#define LEDC_DUTY_CH7 0x01FFFFFFU +#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) +#define LEDC_DUTY_CH7_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_S 0 /** LEDC_CH7_CONF1_REG register * Configuration register 1 for channel 7 */ #define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) -/** LEDC_DUTY_START_CH0 : R/W/SC; bitpos: [31]; default: 0; +/** LEDC_DUTY_START_CH7 : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001U -#define LEDC_DUTY_START_CH0_S 31 +#define LEDC_DUTY_START_CH7 (BIT(31)) +#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) +#define LEDC_DUTY_START_CH7_V 0x00000001U +#define LEDC_DUTY_START_CH7_S 31 /** LEDC_CH7_DUTY_R_REG register * Current duty cycle register for channel 7 */ #define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) -/** LEDC_DUTY_CH0_R : RO; bitpos: [24:0]; default: 0; +/** LEDC_DUTY_CH7_R : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel 7. */ -#define LEDC_DUTY_CH0_R 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_M (LEDC_DUTY_CH0_R_V << LEDC_DUTY_CH0_R_S) -#define LEDC_DUTY_CH0_R_V 0x01FFFFFFU -#define LEDC_DUTY_CH0_R_S 0 +#define LEDC_DUTY_CH7_R 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_M (LEDC_DUTY_CH7_R_V << LEDC_DUTY_CH7_R_S) +#define LEDC_DUTY_CH7_R_V 0x01FFFFFFU +#define LEDC_DUTY_CH7_R_S 0 /** LEDC_TIMER0_CONF_REG register * Timer 0 configuration register @@ -979,187 +973,187 @@ extern "C" { * Timer 1 configuration register */ #define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; +/** LEDC_TIMER1_DUTY_RES : R/W; bitpos: [4:0]; default: 0; * Configures the range of the counter in timer 1. */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; +#define LEDC_TIMER1_DUTY_RES 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER1_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [22:5]; default: 0; * Configures the divisor for the divider in timer 1.The least significant eight bits * represent the fractional part. */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; +#define LEDC_CLK_DIV_TIMER1 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER1_S 5 +/** LEDC_TIMER1_PAUSE : R/W; bitpos: [23]; default: 0; * Configures whether or not to pause the counter in timer 1.\\0: Normal\\1: Pause */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; +#define LEDC_TIMER1_PAUSE (BIT(23)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001U +#define LEDC_TIMER1_PAUSE_S 23 +/** LEDC_TIMER1_RST : R/W; bitpos: [24]; default: 1; * Configures whether or not to reset timer 1. The counter will show 0 after * reset.\\0: Not reset\\1: Reset */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; +#define LEDC_TIMER1_RST (BIT(24)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001U +#define LEDC_TIMER1_RST_S 24 +/** LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [25]; default: 0; * Configures which clock is timer 1 selected. Unused. */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; +#define LEDC_TICK_SEL_TIMER1 (BIT(25)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001U +#define LEDC_TICK_SEL_TIMER1_S 25 +/** LEDC_TIMER1_PARA_UP : WT; bitpos: [26]; default: 0; * Configures whether or not to update LEDC_CLK_DIV_TIMER1 and * LEDC_TIMER1_DUTY_RES.\\0: Invalid. No effect\\1: Update */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 +#define LEDC_TIMER1_PARA_UP (BIT(26)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001U +#define LEDC_TIMER1_PARA_UP_S 26 /** LEDC_TIMER1_VALUE_REG register * Timer 1 current counter value register */ #define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER1_CNT : RO; bitpos: [19:0]; default: 0; * Represents the current counter value of timer 1. */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 +#define LEDC_TIMER1_CNT 0x000FFFFFU +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_S 0 /** LEDC_TIMER2_CONF_REG register * Timer 2 configuration register */ #define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; +/** LEDC_TIMER2_DUTY_RES : R/W; bitpos: [4:0]; default: 0; * Configures the range of the counter in timer 2. */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; +#define LEDC_TIMER2_DUTY_RES 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER2_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [22:5]; default: 0; * Configures the divisor for the divider in timer 2.The least significant eight bits * represent the fractional part. */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; +#define LEDC_CLK_DIV_TIMER2 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER2_S 5 +/** LEDC_TIMER2_PAUSE : R/W; bitpos: [23]; default: 0; * Configures whether or not to pause the counter in timer 2.\\0: Normal\\1: Pause */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; +#define LEDC_TIMER2_PAUSE (BIT(23)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001U +#define LEDC_TIMER2_PAUSE_S 23 +/** LEDC_TIMER2_RST : R/W; bitpos: [24]; default: 1; * Configures whether or not to reset timer 2. The counter will show 0 after * reset.\\0: Not reset\\1: Reset */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; +#define LEDC_TIMER2_RST (BIT(24)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001U +#define LEDC_TIMER2_RST_S 24 +/** LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [25]; default: 0; * Configures which clock is timer 2 selected. Unused. */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; +#define LEDC_TICK_SEL_TIMER2 (BIT(25)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001U +#define LEDC_TICK_SEL_TIMER2_S 25 +/** LEDC_TIMER2_PARA_UP : WT; bitpos: [26]; default: 0; * Configures whether or not to update LEDC_CLK_DIV_TIMER2 and * LEDC_TIMER2_DUTY_RES.\\0: Invalid. No effect\\1: Update */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 +#define LEDC_TIMER2_PARA_UP (BIT(26)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001U +#define LEDC_TIMER2_PARA_UP_S 26 /** LEDC_TIMER2_VALUE_REG register * Timer 2 current counter value register */ #define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER2_CNT : RO; bitpos: [19:0]; default: 0; * Represents the current counter value of timer 2. */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 +#define LEDC_TIMER2_CNT 0x000FFFFFU +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_S 0 /** LEDC_TIMER3_CONF_REG register * Timer 3 configuration register */ #define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) -/** LEDC_TIMER0_DUTY_RES : R/W; bitpos: [4:0]; default: 0; +/** LEDC_TIMER3_DUTY_RES : R/W; bitpos: [4:0]; default: 0; * Configures the range of the counter in timer 3. */ -#define LEDC_TIMER0_DUTY_RES 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000001FU -#define LEDC_TIMER0_DUTY_RES_S 0 -/** LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [22:5]; default: 0; +#define LEDC_TIMER3_DUTY_RES 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000001FU +#define LEDC_TIMER3_DUTY_RES_S 0 +/** LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [22:5]; default: 0; * Configures the divisor for the divider in timer 3.The least significant eight bits * represent the fractional part. */ -#define LEDC_CLK_DIV_TIMER0 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFFU -#define LEDC_CLK_DIV_TIMER0_S 5 -/** LEDC_TIMER0_PAUSE : R/W; bitpos: [23]; default: 0; +#define LEDC_CLK_DIV_TIMER3 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFFU +#define LEDC_CLK_DIV_TIMER3_S 5 +/** LEDC_TIMER3_PAUSE : R/W; bitpos: [23]; default: 0; * Configures whether or not to pause the counter in timer 3.\\0: Normal\\1: Pause */ -#define LEDC_TIMER0_PAUSE (BIT(23)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001U -#define LEDC_TIMER0_PAUSE_S 23 -/** LEDC_TIMER0_RST : R/W; bitpos: [24]; default: 1; +#define LEDC_TIMER3_PAUSE (BIT(23)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001U +#define LEDC_TIMER3_PAUSE_S 23 +/** LEDC_TIMER3_RST : R/W; bitpos: [24]; default: 1; * Configures whether or not to reset timer 3. The counter will show 0 after * reset.\\0: Not reset\\1: Reset */ -#define LEDC_TIMER0_RST (BIT(24)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001U -#define LEDC_TIMER0_RST_S 24 -/** LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [25]; default: 0; +#define LEDC_TIMER3_RST (BIT(24)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001U +#define LEDC_TIMER3_RST_S 24 +/** LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [25]; default: 0; * Configures which clock is timer 3 selected. Unused. */ -#define LEDC_TICK_SEL_TIMER0 (BIT(25)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001U -#define LEDC_TICK_SEL_TIMER0_S 25 -/** LEDC_TIMER0_PARA_UP : WT; bitpos: [26]; default: 0; +#define LEDC_TICK_SEL_TIMER3 (BIT(25)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001U +#define LEDC_TICK_SEL_TIMER3_S 25 +/** LEDC_TIMER3_PARA_UP : WT; bitpos: [26]; default: 0; * Configures whether or not to update LEDC_CLK_DIV_TIMER3 and * LEDC_TIMER3_DUTY_RES.\\0: Invalid. No effect\\1: Update */ -#define LEDC_TIMER0_PARA_UP (BIT(26)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001U -#define LEDC_TIMER0_PARA_UP_S 26 +#define LEDC_TIMER3_PARA_UP (BIT(26)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001U +#define LEDC_TIMER3_PARA_UP_S 26 /** LEDC_TIMER3_VALUE_REG register * Timer 3 current counter value register */ #define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) -/** LEDC_TIMER0_CNT : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER3_CNT : RO; bitpos: [19:0]; default: 0; * Represents the current counter value of timer 3. */ -#define LEDC_TIMER0_CNT 0x000FFFFFU -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_S 0 +#define LEDC_TIMER3_CNT 0x000FFFFFU +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_S 0 /** LEDC_INT_RAW_REG register * Interrupt raw status register @@ -1813,197 +1807,197 @@ extern "C" { * Ledc ch1 gamma config register. */ #define LEDC_CH1_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x104) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH1_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch1. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH1_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_M (LEDC_CH1_GAMMA_ENTRY_NUM_V << LEDC_CH1_GAMMA_ENTRY_NUM_S) +#define LEDC_CH1_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH1_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH1_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch1.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH1_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH1_GAMMA_PAUSE_M (LEDC_CH1_GAMMA_PAUSE_V << LEDC_CH1_GAMMA_PAUSE_S) +#define LEDC_CH1_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH1_GAMMA_PAUSE_S 5 +/** LEDC_CH1_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch1.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH1_GAMMA_RESUME (BIT(6)) +#define LEDC_CH1_GAMMA_RESUME_M (LEDC_CH1_GAMMA_RESUME_V << LEDC_CH1_GAMMA_RESUME_S) +#define LEDC_CH1_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH1_GAMMA_RESUME_S 6 /** LEDC_CH2_GAMMA_CONF_REG register * Ledc ch2 gamma config register. */ #define LEDC_CH2_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x108) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH2_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch2. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH2_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_M (LEDC_CH2_GAMMA_ENTRY_NUM_V << LEDC_CH2_GAMMA_ENTRY_NUM_S) +#define LEDC_CH2_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH2_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH2_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch2.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH2_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH2_GAMMA_PAUSE_M (LEDC_CH2_GAMMA_PAUSE_V << LEDC_CH2_GAMMA_PAUSE_S) +#define LEDC_CH2_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH2_GAMMA_PAUSE_S 5 +/** LEDC_CH2_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch2.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH2_GAMMA_RESUME (BIT(6)) +#define LEDC_CH2_GAMMA_RESUME_M (LEDC_CH2_GAMMA_RESUME_V << LEDC_CH2_GAMMA_RESUME_S) +#define LEDC_CH2_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH2_GAMMA_RESUME_S 6 /** LEDC_CH3_GAMMA_CONF_REG register * Ledc ch3 gamma config register. */ #define LEDC_CH3_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x10c) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH3_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch3. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH3_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_M (LEDC_CH3_GAMMA_ENTRY_NUM_V << LEDC_CH3_GAMMA_ENTRY_NUM_S) +#define LEDC_CH3_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH3_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH3_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch3.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH3_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH3_GAMMA_PAUSE_M (LEDC_CH3_GAMMA_PAUSE_V << LEDC_CH3_GAMMA_PAUSE_S) +#define LEDC_CH3_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH3_GAMMA_PAUSE_S 5 +/** LEDC_CH3_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch3.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH3_GAMMA_RESUME (BIT(6)) +#define LEDC_CH3_GAMMA_RESUME_M (LEDC_CH3_GAMMA_RESUME_V << LEDC_CH3_GAMMA_RESUME_S) +#define LEDC_CH3_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH3_GAMMA_RESUME_S 6 /** LEDC_CH4_GAMMA_CONF_REG register * Ledc ch4 gamma config register. */ #define LEDC_CH4_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x110) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH4_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch4. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH4_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_M (LEDC_CH4_GAMMA_ENTRY_NUM_V << LEDC_CH4_GAMMA_ENTRY_NUM_S) +#define LEDC_CH4_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH4_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH4_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch4.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH4_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH4_GAMMA_PAUSE_M (LEDC_CH4_GAMMA_PAUSE_V << LEDC_CH4_GAMMA_PAUSE_S) +#define LEDC_CH4_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH4_GAMMA_PAUSE_S 5 +/** LEDC_CH4_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch4.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH4_GAMMA_RESUME (BIT(6)) +#define LEDC_CH4_GAMMA_RESUME_M (LEDC_CH4_GAMMA_RESUME_V << LEDC_CH4_GAMMA_RESUME_S) +#define LEDC_CH4_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH4_GAMMA_RESUME_S 6 /** LEDC_CH5_GAMMA_CONF_REG register * Ledc ch5 gamma config register. */ #define LEDC_CH5_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x114) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH5_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch5. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH5_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_M (LEDC_CH5_GAMMA_ENTRY_NUM_V << LEDC_CH5_GAMMA_ENTRY_NUM_S) +#define LEDC_CH5_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH5_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH5_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch5.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH5_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH5_GAMMA_PAUSE_M (LEDC_CH5_GAMMA_PAUSE_V << LEDC_CH5_GAMMA_PAUSE_S) +#define LEDC_CH5_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH5_GAMMA_PAUSE_S 5 +/** LEDC_CH5_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch5.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH5_GAMMA_RESUME (BIT(6)) +#define LEDC_CH5_GAMMA_RESUME_M (LEDC_CH5_GAMMA_RESUME_V << LEDC_CH5_GAMMA_RESUME_S) +#define LEDC_CH5_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH5_GAMMA_RESUME_S 6 /** LEDC_CH6_GAMMA_CONF_REG register * Ledc ch6 gamma config register. */ #define LEDC_CH6_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x118) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH6_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch6. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH6_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_M (LEDC_CH6_GAMMA_ENTRY_NUM_V << LEDC_CH6_GAMMA_ENTRY_NUM_S) +#define LEDC_CH6_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH6_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH6_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch6.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH6_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH6_GAMMA_PAUSE_M (LEDC_CH6_GAMMA_PAUSE_V << LEDC_CH6_GAMMA_PAUSE_S) +#define LEDC_CH6_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH6_GAMMA_PAUSE_S 5 +/** LEDC_CH6_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch6.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH6_GAMMA_RESUME (BIT(6)) +#define LEDC_CH6_GAMMA_RESUME_M (LEDC_CH6_GAMMA_RESUME_V << LEDC_CH6_GAMMA_RESUME_S) +#define LEDC_CH6_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH6_GAMMA_RESUME_S 6 /** LEDC_CH7_GAMMA_CONF_REG register * Ledc ch7 gamma config register. */ #define LEDC_CH7_GAMMA_CONF_REG (DR_REG_LEDC_BASE + 0x11c) -/** LEDC_CH0_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; +/** LEDC_CH7_GAMMA_ENTRY_NUM : R/W; bitpos: [4:0]; default: 0; * Configures the number of duty cycle fading rages for LEDC ch7. */ -#define LEDC_CH0_GAMMA_ENTRY_NUM 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_M (LEDC_CH0_GAMMA_ENTRY_NUM_V << LEDC_CH0_GAMMA_ENTRY_NUM_S) -#define LEDC_CH0_GAMMA_ENTRY_NUM_V 0x0000001FU -#define LEDC_CH0_GAMMA_ENTRY_NUM_S 0 -/** LEDC_CH0_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; +#define LEDC_CH7_GAMMA_ENTRY_NUM 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_M (LEDC_CH7_GAMMA_ENTRY_NUM_V << LEDC_CH7_GAMMA_ENTRY_NUM_S) +#define LEDC_CH7_GAMMA_ENTRY_NUM_V 0x0000001FU +#define LEDC_CH7_GAMMA_ENTRY_NUM_S 0 +/** LEDC_CH7_GAMMA_PAUSE : WT; bitpos: [5]; default: 0; * Configures whether or not to pause duty cycle fading of LEDC ch7.\\0: Invalid. No * effect\\1: Pause */ -#define LEDC_CH0_GAMMA_PAUSE (BIT(5)) -#define LEDC_CH0_GAMMA_PAUSE_M (LEDC_CH0_GAMMA_PAUSE_V << LEDC_CH0_GAMMA_PAUSE_S) -#define LEDC_CH0_GAMMA_PAUSE_V 0x00000001U -#define LEDC_CH0_GAMMA_PAUSE_S 5 -/** LEDC_CH0_GAMMA_RESUME : WT; bitpos: [6]; default: 0; +#define LEDC_CH7_GAMMA_PAUSE (BIT(5)) +#define LEDC_CH7_GAMMA_PAUSE_M (LEDC_CH7_GAMMA_PAUSE_V << LEDC_CH7_GAMMA_PAUSE_S) +#define LEDC_CH7_GAMMA_PAUSE_V 0x00000001U +#define LEDC_CH7_GAMMA_PAUSE_S 5 +/** LEDC_CH7_GAMMA_RESUME : WT; bitpos: [6]; default: 0; * Configures whether or nor to resume duty cycle fading of LEDC ch7.\\0: Invalid. No * effect\\1: Resume */ -#define LEDC_CH0_GAMMA_RESUME (BIT(6)) -#define LEDC_CH0_GAMMA_RESUME_M (LEDC_CH0_GAMMA_RESUME_V << LEDC_CH0_GAMMA_RESUME_S) -#define LEDC_CH0_GAMMA_RESUME_V 0x00000001U -#define LEDC_CH0_GAMMA_RESUME_S 6 +#define LEDC_CH7_GAMMA_RESUME (BIT(6)) +#define LEDC_CH7_GAMMA_RESUME_M (LEDC_CH7_GAMMA_RESUME_V << LEDC_CH7_GAMMA_RESUME_S) +#define LEDC_CH7_GAMMA_RESUME_V 0x00000001U +#define LEDC_CH7_GAMMA_RESUME_S 6 /** LEDC_EVT_TASK_EN0_REG register * Ledc event task enable bit register0. @@ -2732,37 +2726,37 @@ extern "C" { * Ledc timer1 compare value register. */ #define LEDC_TIMER1_CMP_REG (DR_REG_LEDC_BASE + 0x144) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; +/** LEDC_TIMER1_CMP : R/W; bitpos: [19:0]; default: 0; * Configures the comparison value for LEDC timer1. */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 +#define LEDC_TIMER1_CMP 0x000FFFFFU +#define LEDC_TIMER1_CMP_M (LEDC_TIMER1_CMP_V << LEDC_TIMER1_CMP_S) +#define LEDC_TIMER1_CMP_V 0x000FFFFFU +#define LEDC_TIMER1_CMP_S 0 /** LEDC_TIMER2_CMP_REG register * Ledc timer2 compare value register. */ #define LEDC_TIMER2_CMP_REG (DR_REG_LEDC_BASE + 0x148) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; +/** LEDC_TIMER2_CMP : R/W; bitpos: [19:0]; default: 0; * Configures the comparison value for LEDC timer2. */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 +#define LEDC_TIMER2_CMP 0x000FFFFFU +#define LEDC_TIMER2_CMP_M (LEDC_TIMER2_CMP_V << LEDC_TIMER2_CMP_S) +#define LEDC_TIMER2_CMP_V 0x000FFFFFU +#define LEDC_TIMER2_CMP_S 0 /** LEDC_TIMER3_CMP_REG register * Ledc timer3 compare value register. */ #define LEDC_TIMER3_CMP_REG (DR_REG_LEDC_BASE + 0x14c) -/** LEDC_TIMER0_CMP : R/W; bitpos: [19:0]; default: 0; +/** LEDC_TIMER3_CMP : R/W; bitpos: [19:0]; default: 0; * Configures the comparison value for LEDC timer3. */ -#define LEDC_TIMER0_CMP 0x000FFFFFU -#define LEDC_TIMER0_CMP_M (LEDC_TIMER0_CMP_V << LEDC_TIMER0_CMP_S) -#define LEDC_TIMER0_CMP_V 0x000FFFFFU -#define LEDC_TIMER0_CMP_S 0 +#define LEDC_TIMER3_CMP 0x000FFFFFU +#define LEDC_TIMER3_CMP_M (LEDC_TIMER3_CMP_V << LEDC_TIMER3_CMP_S) +#define LEDC_TIMER3_CMP_V 0x000FFFFFU +#define LEDC_TIMER3_CMP_S 0 /** LEDC_TIMER0_CNT_CAP_REG register * Ledc timer0 captured count value register. @@ -2780,37 +2774,37 @@ extern "C" { * Ledc timer1 captured count value register. */ #define LEDC_TIMER1_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x154) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER1_CNT_CAP : RO; bitpos: [19:0]; default: 0; * Represents the captured LEDC timer1 count value. */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 +#define LEDC_TIMER1_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_M (LEDC_TIMER1_CNT_CAP_V << LEDC_TIMER1_CNT_CAP_S) +#define LEDC_TIMER1_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER1_CNT_CAP_S 0 /** LEDC_TIMER2_CNT_CAP_REG register * Ledc timer2 captured count value register. */ #define LEDC_TIMER2_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x158) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER2_CNT_CAP : RO; bitpos: [19:0]; default: 0; * Represents the captured LEDC timer2 count value. */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 +#define LEDC_TIMER2_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_M (LEDC_TIMER2_CNT_CAP_V << LEDC_TIMER2_CNT_CAP_S) +#define LEDC_TIMER2_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER2_CNT_CAP_S 0 /** LEDC_TIMER3_CNT_CAP_REG register * Ledc timer3 captured count value register. */ #define LEDC_TIMER3_CNT_CAP_REG (DR_REG_LEDC_BASE + 0x15c) -/** LEDC_TIMER0_CNT_CAP : RO; bitpos: [19:0]; default: 0; +/** LEDC_TIMER3_CNT_CAP : RO; bitpos: [19:0]; default: 0; * Represents the captured LEDC timer3 count value. */ -#define LEDC_TIMER0_CNT_CAP 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_M (LEDC_TIMER0_CNT_CAP_V << LEDC_TIMER0_CNT_CAP_S) -#define LEDC_TIMER0_CNT_CAP_V 0x000FFFFFU -#define LEDC_TIMER0_CNT_CAP_S 0 +#define LEDC_TIMER3_CNT_CAP 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_M (LEDC_TIMER3_CNT_CAP_V << LEDC_TIMER3_CNT_CAP_S) +#define LEDC_TIMER3_CNT_CAP_V 0x000FFFFFU +#define LEDC_TIMER3_CNT_CAP_S 0 /** LEDC_CONF_REG register * LEDC global configuration register @@ -2917,6 +2911,2832 @@ extern "C" { #define LEDC_LEDC_DATE_V 0x0FFFFFFFU #define LEDC_LEDC_DATE_S 0 +/** LEDC gamma fade config ram registers + * 16 words (32bit) per channel * 8 channels + */ +#define LEDC_CH0_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x400) +/* LEDC_CH0_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_SCALE_M ((LEDC_CH0_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x404) +/* LEDC_CH0_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_SCALE_M ((LEDC_CH0_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x408) +/* LEDC_CH0_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_SCALE_M ((LEDC_CH0_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x40c) +/* LEDC_CH0_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_SCALE_M ((LEDC_CH0_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x410) +/* LEDC_CH0_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_SCALE_M ((LEDC_CH0_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x414) +/* LEDC_CH0_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_SCALE_M ((LEDC_CH0_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x418) +/* LEDC_CH0_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_SCALE_M ((LEDC_CH0_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x41c) +/* LEDC_CH0_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_SCALE_M ((LEDC_CH0_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x420) +/* LEDC_CH0_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_SCALE_M ((LEDC_CH0_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x424) +/* LEDC_CH0_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_SCALE_M ((LEDC_CH0_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x428) +/* LEDC_CH0_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_SCALE_M ((LEDC_CH0_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x42c) +/* LEDC_CH0_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_SCALE_M ((LEDC_CH0_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x430) +/* LEDC_CH0_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_SCALE_M ((LEDC_CH0_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x434) +/* LEDC_CH0_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_SCALE_M ((LEDC_CH0_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x438) +/* LEDC_CH0_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_SCALE_M ((LEDC_CH0_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH0_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x43c) +/* LEDC_CH0_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH0_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_SCALE_M ((LEDC_CH0_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH0_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH0_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH0_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH0_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH0_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH1_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x440) +/* LEDC_CH1_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_SCALE_M ((LEDC_CH1_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x444) +/* LEDC_CH1_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_SCALE_M ((LEDC_CH1_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x448) +/* LEDC_CH1_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_SCALE_M ((LEDC_CH1_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x44c) +/* LEDC_CH1_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_SCALE_M ((LEDC_CH1_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x450) +/* LEDC_CH1_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_SCALE_M ((LEDC_CH1_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x454) +/* LEDC_CH1_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_SCALE_M ((LEDC_CH1_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x458) +/* LEDC_CH1_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_SCALE_M ((LEDC_CH1_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x45c) +/* LEDC_CH1_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_SCALE_M ((LEDC_CH1_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x460) +/* LEDC_CH1_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_SCALE_M ((LEDC_CH1_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x464) +/* LEDC_CH1_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_SCALE_M ((LEDC_CH1_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x468) +/* LEDC_CH1_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_SCALE_M ((LEDC_CH1_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x46c) +/* LEDC_CH1_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_SCALE_M ((LEDC_CH1_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x470) +/* LEDC_CH1_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_SCALE_M ((LEDC_CH1_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x474) +/* LEDC_CH1_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_SCALE_M ((LEDC_CH1_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x478) +/* LEDC_CH1_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_SCALE_M ((LEDC_CH1_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH1_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x47c) +/* LEDC_CH1_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH1_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_SCALE_M ((LEDC_CH1_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH1_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH1_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH1_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH1_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH1_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH2_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x480) +/* LEDC_CH2_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_SCALE_M ((LEDC_CH2_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x484) +/* LEDC_CH2_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_SCALE_M ((LEDC_CH2_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x488) +/* LEDC_CH2_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_SCALE_M ((LEDC_CH2_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x48c) +/* LEDC_CH2_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_SCALE_M ((LEDC_CH2_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x490) +/* LEDC_CH2_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_SCALE_M ((LEDC_CH2_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x494) +/* LEDC_CH2_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_SCALE_M ((LEDC_CH2_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x498) +/* LEDC_CH2_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_SCALE_M ((LEDC_CH2_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x49c) +/* LEDC_CH2_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_SCALE_M ((LEDC_CH2_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x4a0) +/* LEDC_CH2_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_SCALE_M ((LEDC_CH2_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x4a4) +/* LEDC_CH2_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_SCALE_M ((LEDC_CH2_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x4a8) +/* LEDC_CH2_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_SCALE_M ((LEDC_CH2_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x4ac) +/* LEDC_CH2_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_SCALE_M ((LEDC_CH2_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x4b0) +/* LEDC_CH2_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_SCALE_M ((LEDC_CH2_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x4b4) +/* LEDC_CH2_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_SCALE_M ((LEDC_CH2_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x4b8) +/* LEDC_CH2_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_SCALE_M ((LEDC_CH2_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH2_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x4bc) +/* LEDC_CH2_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH2_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_SCALE_M ((LEDC_CH2_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH2_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH2_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH2_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH2_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH2_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH3_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x4c0) +/* LEDC_CH3_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_SCALE_M ((LEDC_CH3_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x4c4) +/* LEDC_CH3_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_SCALE_M ((LEDC_CH3_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x4c8) +/* LEDC_CH3_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_SCALE_M ((LEDC_CH3_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x4cc) +/* LEDC_CH3_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_SCALE_M ((LEDC_CH3_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x4d0) +/* LEDC_CH3_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_SCALE_M ((LEDC_CH3_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x4d4) +/* LEDC_CH3_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_SCALE_M ((LEDC_CH3_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x4d8) +/* LEDC_CH3_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_SCALE_M ((LEDC_CH3_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x4dc) +/* LEDC_CH3_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_SCALE_M ((LEDC_CH3_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x4e0) +/* LEDC_CH3_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_SCALE_M ((LEDC_CH3_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x4e4) +/* LEDC_CH3_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_SCALE_M ((LEDC_CH3_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x4e8) +/* LEDC_CH3_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_SCALE_M ((LEDC_CH3_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x4ec) +/* LEDC_CH3_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_SCALE_M ((LEDC_CH3_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x4f0) +/* LEDC_CH3_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_SCALE_M ((LEDC_CH3_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x4f4) +/* LEDC_CH3_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_SCALE_M ((LEDC_CH3_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x4f8) +/* LEDC_CH3_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_SCALE_M ((LEDC_CH3_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH3_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x4fc) +/* LEDC_CH3_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH3_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_SCALE_M ((LEDC_CH3_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH3_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH3_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH3_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH3_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH3_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH4_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x500) +/* LEDC_CH4_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_SCALE_M ((LEDC_CH4_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x504) +/* LEDC_CH4_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_SCALE_M ((LEDC_CH4_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x508) +/* LEDC_CH4_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_SCALE_M ((LEDC_CH4_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x50c) +/* LEDC_CH4_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_SCALE_M ((LEDC_CH4_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x510) +/* LEDC_CH4_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_SCALE_M ((LEDC_CH4_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x514) +/* LEDC_CH4_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_SCALE_M ((LEDC_CH4_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x518) +/* LEDC_CH4_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_SCALE_M ((LEDC_CH4_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x51c) +/* LEDC_CH4_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_SCALE_M ((LEDC_CH4_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x520) +/* LEDC_CH4_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_SCALE_M ((LEDC_CH4_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x524) +/* LEDC_CH4_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_SCALE_M ((LEDC_CH4_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x528) +/* LEDC_CH4_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_SCALE_M ((LEDC_CH4_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x52c) +/* LEDC_CH4_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_SCALE_M ((LEDC_CH4_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x530) +/* LEDC_CH4_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_SCALE_M ((LEDC_CH4_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x534) +/* LEDC_CH4_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_SCALE_M ((LEDC_CH4_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x538) +/* LEDC_CH4_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_SCALE_M ((LEDC_CH4_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH4_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x53c) +/* LEDC_CH4_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH4_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_SCALE_M ((LEDC_CH4_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH4_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH4_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH4_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH4_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH4_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH5_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x540) +/* LEDC_CH5_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_SCALE_M ((LEDC_CH5_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x544) +/* LEDC_CH5_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_SCALE_M ((LEDC_CH5_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x548) +/* LEDC_CH5_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_SCALE_M ((LEDC_CH5_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x54c) +/* LEDC_CH5_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_SCALE_M ((LEDC_CH5_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x550) +/* LEDC_CH5_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_SCALE_M ((LEDC_CH5_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x554) +/* LEDC_CH5_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_SCALE_M ((LEDC_CH5_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x558) +/* LEDC_CH5_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_SCALE_M ((LEDC_CH5_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x55c) +/* LEDC_CH5_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_SCALE_M ((LEDC_CH5_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x560) +/* LEDC_CH5_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_SCALE_M ((LEDC_CH5_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x564) +/* LEDC_CH5_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_SCALE_M ((LEDC_CH5_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x568) +/* LEDC_CH5_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_SCALE_M ((LEDC_CH5_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x56c) +/* LEDC_CH5_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_SCALE_M ((LEDC_CH5_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x570) +/* LEDC_CH5_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_SCALE_M ((LEDC_CH5_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x574) +/* LEDC_CH5_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_SCALE_M ((LEDC_CH5_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x578) +/* LEDC_CH5_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_SCALE_M ((LEDC_CH5_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH5_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x57c) +/* LEDC_CH5_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH5_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_SCALE_M ((LEDC_CH5_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH5_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH5_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH5_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH5_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH5_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH6_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x580) +/* LEDC_CH6_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_SCALE_M ((LEDC_CH6_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x584) +/* LEDC_CH6_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_SCALE_M ((LEDC_CH6_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x588) +/* LEDC_CH6_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_SCALE_M ((LEDC_CH6_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x58c) +/* LEDC_CH6_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_SCALE_M ((LEDC_CH6_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x590) +/* LEDC_CH6_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_SCALE_M ((LEDC_CH6_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x594) +/* LEDC_CH6_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_SCALE_M ((LEDC_CH6_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x598) +/* LEDC_CH6_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_SCALE_M ((LEDC_CH6_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x59c) +/* LEDC_CH6_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_SCALE_M ((LEDC_CH6_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x5a0) +/* LEDC_CH6_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_SCALE_M ((LEDC_CH6_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x5a4) +/* LEDC_CH6_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_SCALE_M ((LEDC_CH6_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x5a8) +/* LEDC_CH6_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_SCALE_M ((LEDC_CH6_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x5ac) +/* LEDC_CH6_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_SCALE_M ((LEDC_CH6_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x5b0) +/* LEDC_CH6_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_SCALE_M ((LEDC_CH6_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x5b4) +/* LEDC_CH6_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_SCALE_M ((LEDC_CH6_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x5b8) +/* LEDC_CH6_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_SCALE_M ((LEDC_CH6_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH6_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x5bc) +/* LEDC_CH6_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH6_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_SCALE_M ((LEDC_CH6_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH6_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH6_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH6_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH6_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH6_GAMMA_RANGE15_DUTY_INC_S 0 + + +#define LEDC_CH7_GAMMA_RANGE0_REG (DR_REG_LEDC_BASE + 0x5c0) +/* LEDC_CH7_GAMMA_RANGE0_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE0_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_SCALE_M ((LEDC_CH7_GAMMA_RANGE0_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE0_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE0_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE0_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE0_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE0_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE1_REG (DR_REG_LEDC_BASE + 0x5c4) +/* LEDC_CH7_GAMMA_RANGE1_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE1_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_SCALE_M ((LEDC_CH7_GAMMA_RANGE1_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE1_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE1_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE1_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE1_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE1_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE2_REG (DR_REG_LEDC_BASE + 0x5c8) +/* LEDC_CH7_GAMMA_RANGE2_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE2_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_SCALE_M ((LEDC_CH7_GAMMA_RANGE2_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE2_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE2_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE2_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE2_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE2_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE3_REG (DR_REG_LEDC_BASE + 0x5cc) +/* LEDC_CH7_GAMMA_RANGE3_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE3_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_SCALE_M ((LEDC_CH7_GAMMA_RANGE3_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE3_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE3_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE3_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE3_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE3_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE4_REG (DR_REG_LEDC_BASE + 0x5d0) +/* LEDC_CH7_GAMMA_RANGE4_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE4_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_SCALE_M ((LEDC_CH7_GAMMA_RANGE4_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE4_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE4_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE4_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE4_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE4_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE5_REG (DR_REG_LEDC_BASE + 0x5d4) +/* LEDC_CH7_GAMMA_RANGE5_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE5_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_SCALE_M ((LEDC_CH7_GAMMA_RANGE5_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE5_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE5_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE5_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE5_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE5_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE6_REG (DR_REG_LEDC_BASE + 0x5d8) +/* LEDC_CH7_GAMMA_RANGE6_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE6_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_SCALE_M ((LEDC_CH7_GAMMA_RANGE6_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE6_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE6_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE6_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE6_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE6_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE7_REG (DR_REG_LEDC_BASE + 0x5dc) +/* LEDC_CH7_GAMMA_RANGE7_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE7_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_SCALE_M ((LEDC_CH7_GAMMA_RANGE7_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE7_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE7_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE7_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE7_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE7_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE8_REG (DR_REG_LEDC_BASE + 0x5e0) +/* LEDC_CH7_GAMMA_RANGE8_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE8_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_SCALE_M ((LEDC_CH7_GAMMA_RANGE8_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE8_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE8_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE8_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE8_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE8_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE9_REG (DR_REG_LEDC_BASE + 0x5e4) +/* LEDC_CH7_GAMMA_RANGE9_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE9_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_SCALE_M ((LEDC_CH7_GAMMA_RANGE9_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE9_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE9_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE9_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE9_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE9_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE10_REG (DR_REG_LEDC_BASE + 0x5e8) +/* LEDC_CH7_GAMMA_RANGE10_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE10_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_SCALE_M ((LEDC_CH7_GAMMA_RANGE10_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE10_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE10_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE10_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE10_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE10_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE11_REG (DR_REG_LEDC_BASE + 0x5ec) +/* LEDC_CH7_GAMMA_RANGE11_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE11_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_SCALE_M ((LEDC_CH7_GAMMA_RANGE11_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE11_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE11_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE11_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE11_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE11_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE12_REG (DR_REG_LEDC_BASE + 0x5f0) +/* LEDC_CH7_GAMMA_RANGE12_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE12_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_SCALE_M ((LEDC_CH7_GAMMA_RANGE12_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE12_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE12_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE12_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE12_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE12_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE13_REG (DR_REG_LEDC_BASE + 0x5f4) +/* LEDC_CH7_GAMMA_RANGE13_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE13_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_SCALE_M ((LEDC_CH7_GAMMA_RANGE13_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE13_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE13_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE13_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE13_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE13_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE14_REG (DR_REG_LEDC_BASE + 0x5f8) +/* LEDC_CH7_GAMMA_RANGE14_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE14_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_SCALE_M ((LEDC_CH7_GAMMA_RANGE14_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE14_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE14_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE14_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE14_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE14_DUTY_INC_S 0 + +#define LEDC_CH7_GAMMA_RANGE15_REG (DR_REG_LEDC_BASE + 0x5fc) +/* LEDC_CH7_GAMMA_RANGE15_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_M ((LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_NUM_S 21 +/* LEDC_CH7_GAMMA_RANGE15_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_SCALE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_SCALE_M ((LEDC_CH7_GAMMA_RANGE15_SCALE_V)<<(LEDC_CH7_GAMMA_RANGE15_SCALE_S)) +#define LEDC_CH7_GAMMA_RANGE15_SCALE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_SCALE_S 11 +/* LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE 0x000003FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_M ((LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V)<<(LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_V 0x3FF +#define LEDC_CH7_GAMMA_RANGE15_DUTY_CYCLE_S 1 +/* LEDC_CH7_GAMMA_RANGE15_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */ +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_M (BIT(0)) +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_V 0x1 +#define LEDC_CH7_GAMMA_RANGE15_DUTY_INC_S 0 + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/ledc_struct.h b/components/soc/esp32p4/include/soc/ledc_struct.h index 3007b26203..170ed2d3ad 100644 --- a/components/soc/esp32p4/include/soc/ledc_struct.h +++ b/components/soc/esp32p4/include/soc/ledc_struct.h @@ -16,42 +16,42 @@ extern "C" { */ typedef union { struct { - /** timer_sel_ch0 : R/W; bitpos: [1:0]; default: 0; + /** timer_sel : R/W; bitpos: [1:0]; default: 0; * Configures which timer is channel n selected.\\0: Select timer0\\1: Select * timer1\\2: Select timer2\\3: Select timer3 */ - uint32_t timer_sel_ch0:2; - /** sig_out_en_ch0 : R/W; bitpos: [2]; default: 0; + uint32_t timer_sel:2; + /** sig_out_en : R/W; bitpos: [2]; default: 0; * Configures whether or not to enable signal output on channel n.\\0: Signal output * disable\\1: Signal output enable */ - uint32_t sig_out_en_ch0:1; - /** idle_lv_ch0 : R/W; bitpos: [3]; default: 0; + uint32_t sig_out_en:1; + /** idle_lv : R/W; bitpos: [3]; default: 0; * Configures the output value when channel n is inactive. Valid only when * LEDC_SIG_OUT_EN_CHn is 0.\\0: Output level is low\\1: Output level is high */ - uint32_t idle_lv_ch0:1; - /** para_up_ch0 : WT; bitpos: [4]; default: 0; + uint32_t idle_lv:1; + /** para_up : WT; bitpos: [4]; default: 0; * Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn, * LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn, * LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel * n, and will be automatically cleared by hardware.\\0: Invalid. No effect\\1: Update */ - uint32_t para_up_ch0:1; - /** ovf_num_ch0 : R/W; bitpos: [14:5]; default: 0; + uint32_t para_up:1; + /** ovf_num : R/W; bitpos: [14:5]; default: 0; * Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt * will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times. */ - uint32_t ovf_num_ch0:10; - /** ovf_cnt_en_ch0 : R/W; bitpos: [15]; default: 0; + uint32_t ovf_num:10; + /** ovf_cnt_en : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the ovf_cnt of channel n.\\0: Disable\\1: Enable */ - uint32_t ovf_cnt_en_ch0:1; - /** ovf_cnt_reset_ch0 : WT; bitpos: [16]; default: 0; + uint32_t ovf_cnt_en:1; + /** ovf_cnt_reset : WT; bitpos: [16]; default: 0; * Configures whether or not to reset the ovf_cnt of channel n.\\0: Invalid. No * effect\\1: Reset the ovf_cnt */ - uint32_t ovf_cnt_reset_ch0:1; + uint32_t ovf_cnt_reset:1; uint32_t reserved_17:15; }; uint32_t val; @@ -62,11 +62,11 @@ typedef union { */ typedef union { struct { - /** hpoint_ch0 : R/W; bitpos: [19:0]; default: 0; + /** hpoint : R/W; bitpos: [19:0]; default: 0; * Configures high point of signal output on channel n. The output value changes to * high when the selected timers has reached the value specified by this register. */ - uint32_t hpoint_ch0:20; + uint32_t hpoint:20; uint32_t reserved_20:12; }; uint32_t val; @@ -77,10 +77,10 @@ typedef union { */ typedef union { struct { - /** duty_ch0 : R/W; bitpos: [24:0]; default: 0; + /** duty : R/W; bitpos: [24:0]; default: 0; * Configures the duty of signal output on channel n. */ - uint32_t duty_ch0:25; + uint32_t duty:25; uint32_t reserved_25:7; }; uint32_t val; @@ -92,11 +92,11 @@ typedef union { typedef union { struct { uint32_t reserved_0:31; - /** duty_start_ch0 : R/W/SC; bitpos: [31]; default: 0; + /** duty_start : R/W/SC; bitpos: [31]; default: 0; * Configures whether the duty cycle fading configurations take effect.\\0: Not take * effect\\1: Take effect */ - uint32_t duty_start_ch0:1; + uint32_t duty_start:1; }; uint32_t val; } ledc_chn_conf1_reg_t; @@ -109,7 +109,7 @@ typedef union { /** duty_ch0_r : RO; bitpos: [24:0]; default: 0; * Represents the current duty of output signal on channel n. */ - uint32_t duty_ch0_r:25; + uint32_t duty:25; uint32_t reserved_25:7; }; uint32_t val; @@ -122,33 +122,33 @@ typedef union { */ typedef union { struct { - /** timer0_duty_res : R/W; bitpos: [4:0]; default: 0; + /** duty_res : R/W; bitpos: [4:0]; default: 0; * Configures the range of the counter in timer n. */ - uint32_t timer0_duty_res:5; - /** clk_div_timer0 : R/W; bitpos: [22:5]; default: 0; + uint32_t duty_res:5; + /** clk_div : R/W; bitpos: [22:5]; default: 0; * Configures the divisor for the divider in timer n.The least significant eight bits * represent the fractional part. */ - uint32_t clk_div_timer0:18; - /** timer0_pause : R/W; bitpos: [23]; default: 0; + uint32_t clk_div:18; + /** pause : R/W; bitpos: [23]; default: 0; * Configures whether or not to pause the counter in timer n.\\0: Normal\\1: Pause */ - uint32_t timer0_pause:1; - /** timer0_rst : R/W; bitpos: [24]; default: 1; + uint32_t pause:1; + /** rst : R/W; bitpos: [24]; default: 1; * Configures whether or not to reset timer n. The counter will show 0 after * reset.\\0: Not reset\\1: Reset */ - uint32_t timer0_rst:1; - /** tick_sel_timer0 : R/W; bitpos: [25]; default: 0; + uint32_t rst:1; + /** tick_sel : R/W; bitpos: [25]; default: 0; * Configures which clock is timer n selected. Unused. */ - uint32_t tick_sel_timer0:1; - /** timer0_para_up : WT; bitpos: [26]; default: 0; + uint32_t tick_sel:1; + /** para_up : WT; bitpos: [26]; default: 0; * Configures whether or not to update LEDC_CLK_DIV_TIMERn and * LEDC_TIMERn_DUTY_RES.\\0: Invalid. No effect\\1: Update */ - uint32_t timer0_para_up:1; + uint32_t para_up:1; uint32_t reserved_27:5; }; uint32_t val; @@ -159,10 +159,10 @@ typedef union { */ typedef union { struct { - /** timer0_cnt : RO; bitpos: [19:0]; default: 0; + /** cnt : RO; bitpos: [19:0]; default: 0; * Represents the current counter value of timer n. */ - uint32_t timer0_cnt:20; + uint32_t cnt:20; uint32_t reserved_20:12; }; uint32_t val; @@ -1088,7 +1088,7 @@ typedef union { /** timer0_cnt_cap : RO; bitpos: [19:0]; default: 0; * Represents the captured LEDC timern count value. */ - uint32_t timer0_cnt_cap:20; + uint32_t timer_cnt_cap:20; uint32_t reserved_20:12; }; uint32_t val; @@ -1181,11 +1181,11 @@ typedef union { } ledc_date_reg_t; typedef struct { - volatile ledc_chn_conf0_reg_t ch0_conf0; - volatile ledc_chn_hpoint_reg_t ch0_hpoint; - volatile ledc_chn_duty_reg_t ch0_duty; - volatile ledc_chn_conf1_reg_t ch0_conf1; - volatile ledc_chn_duty_r_reg_t ch0_duty_r; + volatile ledc_chn_conf0_reg_t conf0; + volatile ledc_chn_hpoint_reg_t hpoint; + volatile ledc_chn_duty_reg_t duty_init; + volatile ledc_chn_conf1_reg_t conf1; + volatile ledc_chn_duty_r_reg_t duty_r; } ledc_chn_reg_t; typedef struct { @@ -1193,8 +1193,8 @@ typedef struct { } ledc_ch_group_reg_t; typedef struct { - volatile ledc_timern_conf_reg_t timer0_conf; - volatile ledc_timern_value_reg_t timer0_value; + volatile ledc_timern_conf_reg_t conf; + volatile ledc_timern_value_reg_t value; } ledc_timerx_reg_t; typedef struct { @@ -1205,7 +1205,7 @@ typedef struct { volatile ledc_ch_group_reg_t channel_group[1]; volatile ledc_timer_group_reg_t timer_group[1]; volatile ledc_int_raw_reg_t int_raw; - volatile ledc_int_st_reg_t int_st; + volatile ledc_int_st_reg_t int_st; volatile ledc_int_ena_reg_t int_ena; volatile ledc_int_clr_reg_t int_clr; uint32_t reserved_0d0[12]; @@ -1222,8 +1222,35 @@ typedef struct { } ledc_dev_t; +/** + * Gamma fade param group ram type + */ +typedef union { + struct { + uint32_t duty_inc :1; + uint32_t duty_cycle :10; + uint32_t scale :10; + uint32_t duty_num :10; + uint32_t reserved :1; + }; + uint32_t val; +} ledc_channel_gamma_fade_param_t; + +typedef struct { + ledc_channel_gamma_fade_param_t entry[16]; +} ledc_gamma_channel_t; + +typedef struct { + volatile ledc_gamma_channel_t channel[8]; +} ledc_gamma_ram_t; + + +extern ledc_dev_t LEDC; +extern ledc_gamma_ram_t LEDC_GAMMA_RAM; + #ifndef __cplusplus _Static_assert(sizeof(ledc_dev_t) == 0x178, "Invalid size of ledc_dev_t structure"); +_Static_assert(sizeof(ledc_gamma_ram_t) == 0x200, "Invalid size of ledc_gamma_ram_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 6215de6f11..25ea22b0e8 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -53,7 +53,7 @@ // #define SOC_RMT_SUPPORTED 1 //TODO: IDF-7476 // #define SOC_SDM_SUPPORTED 1 //TODO: IDF-7551 #define SOC_GPSPI_SUPPORTED 1 -// #define SOC_LEDC_SUPPORTED 1 //TODO: IDF-6510 +#define SOC_LEDC_SUPPORTED 1 #define SOC_I2C_SUPPORTED 1 //TODO: IDF-6507, TODO: IDF-7491 #define SOC_SYSTIMER_SUPPORTED 1 // #define SOC_AES_SUPPORTED 1 //TODO: IDF-6519 @@ -263,10 +263,12 @@ /*-------------------------- LEDC CAPS ---------------------------------------*/ #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) -#define SOC_LEDC_CHANNEL_NUM (6) +#define SOC_LEDC_CHANNEL_NUM (8) #define SOC_LEDC_TIMER_BIT_WIDTH (20) +#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) +#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) #define SOC_LEDC_SUPPORT_FADE_STOP (1) -#define SOC_LEDC_GAMMA_FADE_RANGE_MAX (16) +#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) /*-------------------------- MMU CAPS ----------------------------------------*/ #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (0) diff --git a/components/soc/esp32p4/ld/esp32p4.peripherals.ld b/components/soc/esp32p4/ld/esp32p4.peripherals.ld index 059a30e4b7..dd04e11bb3 100644 --- a/components/soc/esp32p4/ld/esp32p4.peripherals.ld +++ b/components/soc/esp32p4/ld/esp32p4.peripherals.ld @@ -20,6 +20,7 @@ PROVIDE ( UHCI0 = 0x500DF000 ); PROVIDE ( RMT = 0x500A2000 ); PROVIDE ( RMTMEM = 0x500A2800 ); PROVIDE ( LEDC = 0x500D3000 ); +PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 ); PROVIDE ( TIMERG0 = 0x500C2000 ); PROVIDE ( TIMERG1 = 0x500C3000 ); PROVIDE ( SYSTIMER = 0x500E2000 ); diff --git a/components/soc/esp32p4/ledc_periph.c b/components/soc/esp32p4/ledc_periph.c index 867ad4bfd6..6258f357a5 100644 --- a/components/soc/esp32p4/ledc_periph.c +++ b/components/soc/esp32p4/ledc_periph.c @@ -11,5 +11,7 @@ Bunch of constants for every LEDC peripheral: GPIO signals */ const ledc_signal_conn_t ledc_periph_signal[1] = { - + { + .sig_out0_idx = LEDC_LS_SIG_OUT_PAD_OUT0_IDX, + } }; diff --git a/docs/docs_not_updated/esp32p4.txt b/docs/docs_not_updated/esp32p4.txt index a421688534..62a3fca4de 100644 --- a/docs/docs_not_updated/esp32p4.txt +++ b/docs/docs_not_updated/esp32p4.txt @@ -112,7 +112,6 @@ api-reference/peripherals/touch_element.rst api-reference/peripherals/lcd.rst api-reference/peripherals/ana_cmpr.rst api-reference/peripherals/secure_element.rst -api-reference/peripherals/ledc.rst api-reference/peripherals/temp_sensor.rst api-reference/peripherals/sdio_slave.rst api-reference/peripherals/clk_tree.rst diff --git a/docs/en/api-reference/peripherals/ledc.rst b/docs/en/api-reference/peripherals/ledc.rst index b828810044..c865ca5618 100644 --- a/docs/en/api-reference/peripherals/ledc.rst +++ b/docs/en/api-reference/peripherals/ledc.rst @@ -1,7 +1,7 @@ LED Control (LEDC) ================== -{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16"} +{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16"} :link_to_translation:`zh_CN:[中文]` @@ -150,7 +150,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f - 40 MHz - Dynamic Frequency Scaling compatible -.. only:: esp32c6 +.. only:: esp32c6 or esp32p4 .. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks :widths: 15 15 30 diff --git a/docs/zh_CN/api-reference/peripherals/ledc.rst b/docs/zh_CN/api-reference/peripherals/ledc.rst index 34227b787f..0f4e382756 100644 --- a/docs/zh_CN/api-reference/peripherals/ledc.rst +++ b/docs/zh_CN/api-reference/peripherals/ledc.rst @@ -1,7 +1,7 @@ LED PWM 控制器 ============== -{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16"} +{IDF_TARGET_LEDC_MAX_FADE_RANGE_NUM: default="1", esp32c6="16", esp32h2="16", esp32p4="16"} :link_to_translation:`en:[English]` @@ -88,7 +88,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 * - RC_FAST_CLK - ~ 8 MHz - 低速 - - 支持动态调频 (DFS) 功能，支持Light-sleep模式 + - 支持动态调频（DFS）功能，支持 Light-sleep 模式 .. only:: esp32s2 @@ -107,7 +107,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - 支持动态调频 (DFS) 功能 * - RC_FAST_CLK - ~ 8 MHz - - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式 + - 支持动态调频（DFS）功能，支持 Light-sleep 模式 * - XTAL_CLK - 40 MHz - 支持动态调频 (DFS) 功能 @@ -145,12 +145,12 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - / * - RC_FAST_CLK - ~ 20 MHz - - 支持动态调频 (DFS) 功能，支持Light-sleep模式 + - 支持动态调频（DFS）功能，支持 Light-sleep 模式 * - XTAL_CLK - 40 MHz - 支持动态调频 (DFS) 功能 -.. only:: esp32c6 +.. only:: esp32c6 or esp32p4 .. list-table:: {IDF_TARGET_NAME} LEDC 时钟源特性 :widths: 10 10 30 @@ -164,7 +164,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - / * - RC_FAST_CLK - ~ 20 MHz - - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式 + - 支持动态调频（DFS）功能，支持 Light-sleep 模式 * - XTAL_CLK - 40 MHz - 支持动态调频 (DFS) 功能 @@ -183,7 +183,7 @@ LED PWM 控制器可在无需 CPU 干预的情况下自动改变占空比，实 - / * - RC_FAST_CLK - ~ 8 MHz - - 支持动态调频 (DFS) 功能，支持 Light-sleep 模式 + - 支持动态调频（DFS）功能，支持 Light-sleep 模式 * - XTAL_CLK - 32 MHz - 支持动态调频 (DFS) 功能 diff --git a/examples/peripherals/ledc/ledc_basic/README.md b/examples/peripherals/ledc/ledc_basic/README.md index 36827f21f8..ef73df1c5a 100644 --- a/examples/peripherals/ledc/ledc_basic/README.md +++ b/examples/peripherals/ledc/ledc_basic/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # _LEDC Basic Example_ @@ -23,7 +23,7 @@ Connect the GPIO to an oscilloscope to see the generated signal: ### Configure the project -The example uses fixed PWM frequency of 5 kHz, duty cycle in 50%, and output GPIO pin. To change them, adjust `LEDC_FREQUENCY`, `LEDC_DUTY`, `LEDC_OUTPUT_IO` macros at the top of ledc_basic_example_main.c. +The example uses fixed PWM frequency of 4 kHz, duty cycle in 50%, and output GPIO pin. To change them, adjust `LEDC_FREQUENCY`, `LEDC_DUTY`, `LEDC_OUTPUT_IO` macros at the top of ledc_basic_example_main.c. Depending on the selected `LEDC_FREQUENCY`, you will need to change the `LEDC_DUTY_RES`. diff --git a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c index b0ce4474dc..840c5bcd87 100644 --- a/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c +++ b/examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c @@ -16,7 +16,7 @@ #define LEDC_CHANNEL LEDC_CHANNEL_0 #define LEDC_DUTY_RES LEDC_TIMER_13_BIT // Set duty resolution to 13 bits #define LEDC_DUTY (4096) // Set duty to 50%. (2 ** 13) * 50% = 4096 -#define LEDC_FREQUENCY (5000) // Frequency in Hertz. Set frequency at 5 kHz +#define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz /* Warning: * For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2, ESP32P4 targets, @@ -31,7 +31,7 @@ static void example_ledc_init(void) .speed_mode = LEDC_MODE, .timer_num = LEDC_TIMER, .duty_resolution = LEDC_DUTY_RES, - .freq_hz = LEDC_FREQUENCY, // Set output frequency at 5 kHz + .freq_hz = LEDC_FREQUENCY, // Set output frequency at 4 kHz .clk_cfg = LEDC_AUTO_CLK }; ESP_ERROR_CHECK(ledc_timer_config(&ledc_timer)); diff --git a/examples/peripherals/ledc/ledc_fade/README.md b/examples/peripherals/ledc/ledc_fade/README.md index 2f7aa78ae7..7a667117ce 100644 --- a/examples/peripherals/ledc/ledc_fade/README.md +++ b/examples/peripherals/ledc/ledc_fade/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # _LEDC Fade Example_ diff --git a/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c b/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c index ada11d47bb..7c962c4d49 100644 --- a/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c +++ b/examples/peripherals/ledc/ledc_fade/main/ledc_fade_example_main.c @@ -89,7 +89,7 @@ void app_main(void) */ ledc_timer_config_t ledc_timer = { .duty_resolution = LEDC_TIMER_13_BIT, // resolution of PWM duty - .freq_hz = 5000, // frequency of PWM signal + .freq_hz = 4000, // frequency of PWM signal .speed_mode = LEDC_LS_MODE, // timer mode .timer_num = LEDC_LS_TIMER, // timer index .clk_cfg = LEDC_AUTO_CLK, // Auto select the source clock diff --git a/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md b/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md index 3bd47b1aa4..eec57753b5 100644 --- a/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md +++ b/examples/peripherals/ledc/ledc_gamma_curve_fade/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32-C6 | ESP32-H2 | -| ----------------- | -------- | -------- | +| Supported Targets | ESP32-C6 | ESP32-H2 | ESP32-P4 | +| ----------------- | -------- | -------- | -------- | # _LEDC Gamma Curve Fade Example_ diff --git a/examples/peripherals/ledc/ledc_gamma_curve_fade/main/ledc_gamma_curve_fade_example_main.c b/examples/peripherals/ledc/ledc_gamma_curve_fade/main/ledc_gamma_curve_fade_example_main.c index 9277866e8e..b47e82bc64 100644 --- a/examples/peripherals/ledc/ledc_gamma_curve_fade/main/ledc_gamma_curve_fade_example_main.c +++ b/examples/peripherals/ledc/ledc_gamma_curve_fade/main/ledc_gamma_curve_fade_example_main.c @@ -28,7 +28,7 @@ #define LEDC_MODE LEDC_LOW_SPEED_MODE #define LEDC_DUTY_RES LEDC_TIMER_13_BIT // Set duty resolution to 13 bits -#define LEDC_FREQUENCY (5000) // Frequency in Hertz. Set frequency at 5 kHz +#define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz // Define two RGB LEDs IOs and channels #define LEDC_RED_IO (0) @@ -225,7 +225,7 @@ static void example_rgb_ledc_init(void) .speed_mode = LEDC_MODE, .timer_num = LEDC_TIMER, .duty_resolution = LEDC_DUTY_RES, - .freq_hz = LEDC_FREQUENCY, // Set output frequency at 5 kHz + .freq_hz = LEDC_FREQUENCY, // Set output frequency at 4 kHz .clk_cfg = LEDC_AUTO_CLK }; ESP_ERROR_CHECK(ledc_timer_config(&ledc_timer));