From b8c6c5334f5b3abd1d7236157652cdb9fedc2e44 Mon Sep 17 00:00:00 2001 From: Omar Chebib Date: Wed, 16 Jun 2021 15:19:55 +0800 Subject: [PATCH] i2c: modify examples to work out of the box on ESP32S3 On ESP32S3, the default I2C pins of the examples are already used by USB. This commit changes the default pins. --- components/driver/test/test_i2c.c | 31 +- components/hal/esp32/include/hal/uart_ll.h | 61 + components/hal/esp32c3/include/hal/uart_ll.h | 61 + components/hal/esp32h2/include/hal/uart_ll.h | 61 + components/hal/esp32s2/include/hal/uart_ll.h | 61 + components/hal/esp32s3/include/hal/i2c_ll.h | 111 +- components/hal/esp32s3/include/hal/uart_ll.h | 61 + components/soc/esp32s3/include/soc/i2c_reg.h | 2391 ++++++++++------- .../soc/esp32s3/include/soc/i2c_struct.h | 1578 ++++++++--- .../soc/esp32s3/include/soc/rtc_i2c_reg.h | 1415 +++++----- .../soc/esp32s3/include/soc/rtc_i2c_struct.h | 994 +++++-- docs/en/api-reference/peripherals/i2c.rst | 19 + .../peripherals/i2c/i2c_self_test/README.md | 26 +- .../i2c/i2c_self_test/main/Kconfig.projbuild | 6 +- examples/peripherals/i2c/i2c_tools/README.md | 13 +- .../i2c/i2c_tools/main/cmd_i2ctools.c | 9 + 16 files changed, 4543 insertions(+), 2355 deletions(-) diff --git a/components/driver/test/test_i2c.c b/components/driver/test/test_i2c.c index c22e361ba5..ccf0e9d7d7 100644 --- a/components/driver/test/test_i2c.c +++ b/components/driver/test/test_i2c.c @@ -23,13 +23,14 @@ #include "driver/periph_ctrl.h" #include "esp_rom_gpio.h" #include "hal/gpio_hal.h" +#include "hal/uart_ll.h" #define DATA_LENGTH 512 /*!auto_baud.en = enable ? 1 : 0; +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.min_cnt; +} + /** * @brief Force UART xoff. * diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 237dcb9e25..8bef9e80c8 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -891,6 +891,67 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) return UART_RX_TOUT_THRHD_V; } +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + hw->conf0.autobaud_en = enable ? 1 : 0; +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.min_cnt; +} + /** * @brief Force UART xoff. * diff --git a/components/hal/esp32h2/include/hal/uart_ll.h b/components/hal/esp32h2/include/hal/uart_ll.h index c166e472f5..fc748348d6 100644 --- a/components/hal/esp32h2/include/hal/uart_ll.h +++ b/components/hal/esp32h2/include/hal/uart_ll.h @@ -891,6 +891,67 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) return UART_RX_TOUT_THRHD_V; } +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + hw->conf0.autobaud_en = enable ? 1 : 0; +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.min_cnt; +} + /** * @brief Force UART xoff. * diff --git a/components/hal/esp32s2/include/hal/uart_ll.h b/components/hal/esp32s2/include/hal/uart_ll.h index 6c9ee531aa..15b96f8bed 100644 --- a/components/hal/esp32s2/include/hal/uart_ll.h +++ b/components/hal/esp32s2/include/hal/uart_ll.h @@ -827,6 +827,67 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) return UART_RX_TOUT_THRHD_V; } +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + hw->auto_baud.en = enable ? 1 : 0; +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.min_cnt; +} + /** * @brief Force UART xoff. * diff --git a/components/hal/esp32s3/include/hal/i2c_ll.h b/components/hal/esp32s3/include/hal/i2c_ll.h index 1aa9290ba7..566ada8b3f 100644 --- a/components/hal/esp32s3/include/hal/i2c_ll.h +++ b/components/hal/esp32s3/include/hal/i2c_ll.h @@ -58,7 +58,7 @@ typedef enum { * @brief Data structure for calculating I2C bus timing. */ typedef struct { - uint16_t clkm_div; /*!< I2C core clock devider */ + uint16_t clkm_div; /*!< I2C core clock divider */ uint16_t scl_low; /*!< I2C scl low period */ uint16_t scl_high; /*!< I2C scl hight period */ uint16_t scl_wait_high; /*!< I2C scl wait_high period */ @@ -150,19 +150,19 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg) { hw->clk_conf.sclk_div_num = bus_cfg->clkm_div - 1; //scl period - hw->scl_low_period.period = bus_cfg->scl_low - 1; - hw->scl_high_period.period = bus_cfg->scl_high; + hw->scl_low_period.scl_low_period = bus_cfg->scl_low - 1; + hw->scl_high_period.scl_high_period = bus_cfg->scl_high; //sda sample - hw->sda_hold.time = bus_cfg->sda_hold; - hw->sda_sample.time = bus_cfg->sda_sample; + hw->sda_hold.sda_hold_time = bus_cfg->sda_hold; + hw->sda_sample.sda_sample_time = bus_cfg->sda_sample; //setup - hw->scl_rstart_setup.time = bus_cfg->setup; - hw->scl_stop_setup.time = bus_cfg->setup; + hw->scl_rstart_setup.scl_rstart_setup_time = bus_cfg->setup; + hw->scl_stop_setup.scl_stop_setup_time = bus_cfg->setup; //hold - hw->scl_start_hold.time = bus_cfg->hold - 1; - hw->scl_stop_hold.time = bus_cfg->hold; - hw->timeout.tout = bus_cfg->tout; - hw->timeout.time_out_en = 1; + hw->scl_start_hold.scl_start_hold_time = bus_cfg->hold - 1; + hw->scl_stop_hold.scl_stop_hold_time = bus_cfg->hold; + hw->to.time_out_value = bus_cfg->tout; + hw->to.time_out_en = 1; } /** @@ -203,8 +203,8 @@ static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw) static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int high_period, int low_period) { int high_period_output = high_period - 10; // The rising edge by open-drain output + internal pullup (about 50K) is slow - hw->scl_low_period.period = low_period - 1; - hw->scl_high_period.period = high_period_output; + hw->scl_low_period.scl_low_period = low_period - 1; + hw->scl_high_period.scl_high_period = high_period_output; hw->scl_high_period.scl_wait_high_period = high_period - high_period_output; } @@ -282,7 +282,7 @@ static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en) */ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout) { - hw->timeout.tout = tout; + hw->to.time_out_value = tout; } /** @@ -296,8 +296,8 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout) */ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en) { - hw->slave_addr.addr = slave_addr; - hw->slave_addr.en_10bit = addr_10bit_en; + hw->slave_addr.slave_addr = slave_addr; + hw->slave_addr.addr_10bit_en = addr_10bit_en; } /** @@ -311,7 +311,10 @@ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, boo */ static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd_idx) { - hw->command[cmd_idx].val = cmd.val; + _Static_assert(sizeof(i2c_comd0_reg_t) == sizeof(i2c_hw_cmd_t), + "i2c_comdX_reg_t structure size must be equal to i2c_hw_cmd_t structure size"); + volatile i2c_hw_cmd_t* commands = (volatile i2c_hw_cmd_t*) &hw->comd0; + commands[cmd_idx].val = cmd.val; } /** @@ -325,8 +328,8 @@ static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_hw_cmd_t cmd, int cmd */ static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold) { - hw->scl_rstart_setup.time = start_setup; - hw->scl_start_hold.time = start_hold - 1; + hw->scl_rstart_setup.scl_rstart_setup_time = start_setup; + hw->scl_start_hold.scl_start_hold_time = start_hold - 1; } /** @@ -340,8 +343,8 @@ static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int s */ static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold) { - hw->scl_stop_setup.time = stop_setup; - hw->scl_stop_hold.time = stop_hold; + hw->scl_stop_setup.scl_stop_setup_time = stop_setup; + hw->scl_stop_hold.scl_stop_hold_time = stop_hold; } /** @@ -355,8 +358,8 @@ static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int sto */ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_hold) { - hw->sda_hold.time = sda_hold; - hw->sda_sample.time = sda_sample; + hw->sda_hold.sda_hold_time = sda_hold; + hw->sda_sample.sda_sample_time = sda_sample; } /** @@ -369,7 +372,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_ */ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) { - hw->fifo_conf.tx_fifo_wm_thrhd = empty_thr; + hw->fifo_conf.txfifo_wm_thrhd = empty_thr; } /** @@ -382,7 +385,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr) */ static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr) { - hw->fifo_conf.rx_fifo_wm_thrhd = full_thr; + hw->fifo_conf.rxfifo_wm_thrhd = full_thr; } /** @@ -426,8 +429,8 @@ static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode */ static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sda_hold) { - *sda_hold = hw->sda_hold.time; - *sda_sample = hw->sda_sample.time; + *sda_hold = hw->sda_hold.sda_hold_time; + *sda_sample = hw->sda_sample.sda_sample_time; } /** @@ -439,7 +442,7 @@ static inline void i2c_ll_get_sda_timing(i2c_dev_t *hw, int *sda_sample, int *sd */ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw) { - return hw->date; + return hw->date.val; } /** @@ -475,7 +478,7 @@ static inline bool i2c_ll_is_master_mode(i2c_dev_t *hw) */ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) { - return hw->sr.rx_fifo_cnt; + return hw->sr.rxfifo_cnt; } /** @@ -487,7 +490,7 @@ static inline uint32_t i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw) */ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) { - return SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt; + return SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt; } /** @@ -499,7 +502,7 @@ static inline uint32_t i2c_ll_get_txfifo_len(i2c_dev_t *hw) */ static inline uint32_t i2c_ll_get_tout(i2c_dev_t *hw) { - return hw->timeout.tout; + return hw->to.time_out_value; } /** @@ -525,8 +528,8 @@ static inline void i2c_ll_trans_start(i2c_dev_t *hw) */ static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) { - *setup_time = hw->scl_rstart_setup.time; - *hold_time = hw->scl_start_hold.time + 1; + *setup_time = hw->scl_rstart_setup.scl_rstart_setup_time; + *hold_time = hw->scl_start_hold.scl_start_hold_time + 1; } /** @@ -540,8 +543,8 @@ static inline void i2c_ll_get_start_timing(i2c_dev_t *hw, int *setup_time, int * */ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *hold_time) { - *setup_time = hw->scl_stop_setup.time; - *hold_time = hw->scl_stop_hold.time; + *setup_time = hw->scl_stop_setup.scl_stop_setup_time; + *hold_time = hw->scl_stop_hold.scl_stop_hold_time; } /** @@ -555,8 +558,8 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h */ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period) { - *high_period = hw->scl_high_period.period + hw->scl_high_period.scl_wait_high_period; - *low_period = hw->scl_low_period.period + 1; + *high_period = hw->scl_high_period.scl_high_period + hw->scl_high_period.scl_wait_high_period; + *low_period = hw->scl_low_period.scl_low_period + 1; } /** @@ -571,7 +574,7 @@ static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *l static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for (int i = 0; i< len; i++) { - hw->fifo_data.data = ptr[i]; + hw->data.fifo_rdata = ptr[i]; } } @@ -587,7 +590,7 @@ static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) { for(int i = 0; i < len; i++) { - ptr[i] = hw->fifo_data.data; + ptr[i] = hw->data.fifo_rdata; } } @@ -603,13 +606,13 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len) static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) { if (filter_num > 0) { - hw->filter_cfg.scl_thres = filter_num; - hw->filter_cfg.sda_thres = filter_num; - hw->filter_cfg.scl_en = 1; - hw->filter_cfg.sda_en = 1; + hw->filter_cfg.scl_filter_thres = filter_num; + hw->filter_cfg.sda_filter_thres = filter_num; + hw->filter_cfg.scl_filter_en = 1; + hw->filter_cfg.sda_filter_en = 1; } else { - hw->filter_cfg.scl_en = 0; - hw->filter_cfg.sda_en = 0; + hw->filter_cfg.scl_filter_en = 0; + hw->filter_cfg.sda_filter_en = 0; } } @@ -622,7 +625,7 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num) */ static inline uint8_t i2c_ll_get_filter(i2c_dev_t *hw) { - return hw->filter_cfg.scl_thres; + return hw->filter_cfg.scl_filter_thres; } /** @@ -825,15 +828,15 @@ static inline void i2c_ll_set_source_clk(i2c_dev_t *hw, i2c_sclk_t src_clk) static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) { typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.arbitration_lost) { + if (int_sts.arbitration_lost_int_st) { *event = I2C_INTR_EVENT_ARBIT_LOST; - } else if (int_sts.nack) { + } else if (int_sts.nack_int_st) { *event = I2C_INTR_EVENT_NACK; - } else if (int_sts.time_out) { + } else if (int_sts.time_out_int_st) { *event = I2C_INTR_EVENT_TOUT; - } else if (int_sts.end_detect) { + } else if (int_sts.end_detect_int_st) { *event = I2C_INTR_EVENT_END_DET; - } else if (int_sts.trans_complete) { + } else if (int_sts.trans_complete_int_st) { *event = I2C_INTR_EVENT_TRANS_DONE; } else { *event = I2C_INTR_EVENT_ERR; @@ -851,11 +854,11 @@ static inline void i2c_ll_master_get_event(i2c_dev_t *hw, i2c_intr_event_t *even static inline void i2c_ll_slave_get_event(i2c_dev_t *hw, i2c_intr_event_t *event) { typeof(hw->int_status) int_sts = hw->int_status; - if (int_sts.tx_fifo_wm) { + if (int_sts.txfifo_wm_int_st) { *event = I2C_INTR_EVENT_TXFIFO_EMPTY; - } else if (int_sts.trans_complete) { + } else if (int_sts.trans_complete_int_st) { *event = I2C_INTR_EVENT_TRANS_DONE; - } else if (int_sts.rx_fifo_wm) { + } else if (int_sts.rxfifo_wm_int_st) { *event = I2C_INTR_EVENT_RXFIFO_FULL; } else { *event = I2C_INTR_EVENT_ERR; diff --git a/components/hal/esp32s3/include/hal/uart_ll.h b/components/hal/esp32s3/include/hal/uart_ll.h index 24bc307cea..130e1f2909 100644 --- a/components/hal/esp32s3/include/hal/uart_ll.h +++ b/components/hal/esp32s3/include/hal/uart_ll.h @@ -858,6 +858,67 @@ FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw) return UART_RX_TOUT_THRHD_V; } +/** + * @brief Configure the auto baudrate. + * + * @param hw Beginning address of the peripheral registers. + * @param enable Boolean marking whether the auto baudrate should be enabled or not. + */ +FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable) +{ + hw->conf0.autobaud_en = enable ? 1 : 0; +} + +/** + * @brief Get the RXD edge count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw) +{ + return hw->rxd_cnt.edge_cnt; +} + +/** + * @brief Get the positive pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw) +{ + return hw->pospulse.min_cnt; +} + +/** + * @brief Get the negative pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw) +{ + return hw->negpulse.min_cnt; +} + +/** + * @brief Get the high pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw) +{ + return hw->highpulse.min_cnt; +} + +/** + * @brief Get the low pulse minimum count. + * + * @param hw Beginning address of the peripheral registers. + */ +FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw) +{ + return hw->lowpulse.min_cnt; +} + /** * @brief Force UART xoff. * diff --git a/components/soc/esp32s3/include/soc/i2c_reg.h b/components/soc/esp32s3/include/soc/i2c_reg.h index a269d71694..5d19afa1c3 100644 --- a/components/soc/esp32s3/include/soc/i2c_reg.h +++ b/components/soc/esp32s3/include/soc/i2c_reg.h @@ -1,1126 +1,1431 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_I2C_REG_H_ -#define _SOC_I2C_REG_H_ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) -/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: This register is used to configure for how long SCL remains low in master mode, -in I2C module clock cycles. .*/ -#define I2C_SCL_LOW_PERIOD 0x000001FF -#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) -#define I2C_SCL_LOW_PERIOD_V 0x1FF +/** I2C_SCL_LOW_PERIOD_REG register + * Configures the low level width of the SCL + * Clock + */ +#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) +/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_LOW_PERIOD 0x000001FFU +#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) +#define I2C_SCL_LOW_PERIOD_V 0x000001FFU #define I2C_SCL_LOW_PERIOD_S 0 -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) -/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: This is the enable bit to support the 7bit general call function. .*/ -#define I2C_ADDR_BROADCASTING_EN (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_V 0x1 -#define I2C_ADDR_BROADCASTING_EN_S 14 -/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the enable bit to check if the r/w bit of 10bit addressing consists with - I2C protocol.*/ -#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 -#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 -/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: This is the enable bit for slave to send data automatically.*/ -#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_V 0x1 -#define I2C_SLV_TX_AUTO_START_EN_S 12 -/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: synchronization bit.*/ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (BIT(11)) -#define I2C_CONF_UPGATE_V 0x1 -#define I2C_CONF_UPGATE_S 11 -/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: This register is used to reset the scl FMS..*/ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (BIT(10)) -#define I2C_FSM_RST_V 0x1 -#define I2C_FSM_RST_S 10 -/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: This is the enable bit for arbitration_lost..*/ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (BIT(9)) -#define I2C_ARBITRATION_EN_V 0x1 -#define I2C_ARBITRATION_EN_S 9 -/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (BIT(8)) -#define I2C_CLK_EN_V 0x1 -#define I2C_CLK_EN_S 8 -/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ -/*description: This bit is used to control the storage mode for received data.; 1: receive data - from the least significant bit;; 0: receive data from the most significant bit..*/ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (BIT(7)) -#define I2C_RX_LSB_FIRST_V 0x1 -#define I2C_RX_LSB_FIRST_S 7 -/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This bit is used to control the sending mode for data needing to be sent. ; 1: s -end data from the least significant bit;; 0: send data from the most significant - bit..*/ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (BIT(6)) -#define I2C_TX_LSB_FIRST_V 0x1 -#define I2C_TX_LSB_FIRST_S 6 -/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to start sending the data in txfifo. .*/ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (BIT(5)) -#define I2C_TRANS_START_V 0x1 -#define I2C_TRANS_START_S 5 -/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to configure the module as an I2C Master. Clear this bit to configu -re the; module as an I2C Slave. .*/ -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (BIT(4)) -#define I2C_MS_MODE_V 0x1 -#define I2C_MS_MODE_S 4 -/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This register is used to configure the ACK value that need to sent by master whe -n the rx_fifo_cnt has reached the threshold..*/ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_V 0x1 -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This register is used to select the sample mode.; 1: sample SDA data on the SCL -low level.; 0: sample SDA data on the SCL high level..*/ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_V 0x1 -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ -/*description: 0: direct output; 1: open drain output..*/ -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (BIT(1)) -#define I2C_SCL_FORCE_OUT_V 0x1 -#define I2C_SCL_FORCE_OUT_S 1 -/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ -/*description: 0: direct output; 1: open drain output..*/ +/** I2C_CTR_REG register + * Transmission setting + */ +#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) +/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 1; + * 0: direct output; 1: open drain output. + */ #define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (BIT(0)) -#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) +#define I2C_SDA_FORCE_OUT_V 0x00000001U #define I2C_SDA_FORCE_OUT_S 0 +/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 1; + * 0: direct output; 1: open drain output. + */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) +#define I2C_SCL_FORCE_OUT_V 0x00000001U +#define I2C_SCL_FORCE_OUT_S 1 +/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) +#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) +#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define I2C_RX_FULL_ACK_LEVEL_S 3 +/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) +#define I2C_MS_MODE_V 0x00000001U +#define I2C_MS_MODE_S 4 +/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) +#define I2C_TRANS_START_V 0x00000001U +#define I2C_TRANS_START_S 5 +/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit; + * 0: send data from the most significant bit. + */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) +#define I2C_TX_LSB_FIRST_V 0x00000001U +#define I2C_TX_LSB_FIRST_S 6 +/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit; + * 0: receive data from the most significant bit. + */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) +#define I2C_RX_LSB_FIRST_V 0x00000001U +#define I2C_RX_LSB_FIRST_S 7 +/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; + * Reserved + */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) +#define I2C_CLK_EN_V 0x00000001U +#define I2C_CLK_EN_S 8 +/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) +#define I2C_ARBITRATION_EN_V 0x00000001U +#define I2C_ARBITRATION_EN_S 9 +/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) +#define I2C_FSM_RST_V 0x00000001U +#define I2C_FSM_RST_S 10 +/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; + * synchronization bit + */ +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) +#define I2C_CONF_UPGATE_V 0x00000001U +#define I2C_CONF_UPGATE_S 11 +/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) +#define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U +#define I2C_SLV_TX_AUTO_START_EN_S 12 +/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 +/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) +#define I2C_ADDR_BROADCASTING_EN_V 0x00000001U +#define I2C_ADDR_BROADCASTING_EN_S 14 -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) -/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: This field indicates the states of the state machine used to produce SCL.; 0: Id -le; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop.*/ -#define I2C_SCL_STATE_LAST 0x00000007 -#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) -#define I2C_SCL_STATE_LAST_V 0x7 -#define I2C_SCL_STATE_LAST_S 28 -/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: This field indicates the states of the I2C module state machine. ; 0: Idle; 1: A -ddress shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK.*/ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) -#define I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ -/*description: This field stores the amount of received data in RAM. .*/ -#define I2C_TXFIFO_CNT 0x0000003F -#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) -#define I2C_TXFIFO_CNT_V 0x3F -#define I2C_TXFIFO_CNT_S 18 -/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ -/*description: The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beg -inning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty i -n slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode..*/ -#define I2C_STRETCH_CAUSE 0x00000003 -#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) -#define I2C_STRETCH_CAUSE_V 0x3 -#define I2C_STRETCH_CAUSE_S 14 -/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: This field represents the amount of data needed to be sent. .*/ -#define I2C_RXFIFO_CNT 0x0000003F -#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) -#define I2C_RXFIFO_CNT_V 0x3F -#define I2C_RXFIFO_CNT_S 8 -/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: When configured as an I2C Slave, and the address sent by the master is; equal to - the address of the slave, then this bit will be of high level..*/ -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (BIT(5)) -#define I2C_SLAVE_ADDRESSED_V 0x1 -#define I2C_SLAVE_ADDRESSED_S 5 -/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. .*/ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (BIT(4)) -#define I2C_BUS_BUSY_V 0x1 -#define I2C_BUS_BUSY_S 4 -/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: When the I2C controller loses control of SCL line, this register changes to 1..*/ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (BIT(3)) -#define I2C_ARB_LOST_V 0x1 -#define I2C_ARB_LOST_S 3 -/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: When in slave mode, 1: master reads from slave; 0: master writes to slave..*/ -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (BIT(1)) -#define I2C_SLAVE_RW_V 0x1 -#define I2C_SLAVE_RW_S 1 -/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The received ACK value in master mode or slave mode. 0: ACK, 1: NACK..*/ +/** I2C_SR_REG register + * Describe I2C work status. + */ +#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) +/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ #define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (BIT(0)) -#define I2C_RESP_REC_V 0x1 +#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) +#define I2C_RESP_REC_V 0x00000001U #define I2C_RESP_REC_S 0 +/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave; 0: master writes to slave. + */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S) +#define I2C_SLAVE_RW_V 0x00000001U +#define I2C_SLAVE_RW_S 1 +/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) +#define I2C_ARB_LOST_V 0x00000001U +#define I2C_ARB_LOST_S 3 +/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. + */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) +#define I2C_BUS_BUSY_V 0x00000001U +#define I2C_BUS_BUSY_S 4 +/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) +#define I2C_SLAVE_ADDRESSED_V 0x00000001U +#define I2C_SLAVE_ADDRESSED_S 5 +/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ +#define I2C_RXFIFO_CNT 0x0000003FU +#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) +#define I2C_RXFIFO_CNT_V 0x0000003FU +#define I2C_RXFIFO_CNT_S 8 +/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ +#define I2C_STRETCH_CAUSE 0x00000003U +#define I2C_STRETCH_CAUSE_M (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S) +#define I2C_STRETCH_CAUSE_V 0x00000003U +#define I2C_STRETCH_CAUSE_S 14 +/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ +#define I2C_TXFIFO_CNT 0x0000003FU +#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) +#define I2C_TXFIFO_CNT_V 0x0000003FU +#define I2C_TXFIFO_CNT_S 18 +/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: + * Wait ACK + */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) +#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop + */ +#define I2C_SCL_STATE_LAST 0x00000007U +#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) +#define I2C_SCL_STATE_LAST_V 0x00000007U +#define I2C_SCL_STATE_LAST_S 28 -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) -/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This is the enable bit for time out control..*/ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (BIT(5)) -#define I2C_TIME_OUT_EN_V 0x1 -#define I2C_TIME_OUT_EN_S 5 -/* I2C_TIME_OUT_VALUE : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: This register is used to configure the timeout for receiving a data bit in APB; -clock cycles. .*/ -#define I2C_TIME_OUT_VALUE 0x0000001F -#define I2C_TIME_OUT_VALUE_M ((I2C_TIME_OUT_VALUE_V)<<(I2C_TIME_OUT_VALUE_S)) -#define I2C_TIME_OUT_VALUE_V 0x1F +/** I2C_TO_REG register + * Setting time out control for receiving data. + */ +#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) +/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ +#define I2C_TIME_OUT_VALUE 0x0000001FU +#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) +#define I2C_TIME_OUT_VALUE_V 0x0000001FU #define I2C_TIME_OUT_VALUE_S 0 +/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) +#define I2C_TIME_OUT_EN_V 0x00000001U +#define I2C_TIME_OUT_EN_S 5 -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) -/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: This field is used to enable the slave 10-bit addressing mode in master mode. .*/ -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (BIT(31)) -#define I2C_ADDR_10BIT_EN_V 0x1 -#define I2C_ADDR_10BIT_EN_S 31 -/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: When configured as an I2C Slave, this field is used to configure the slave addre -ss..*/ -#define I2C_SLAVE_ADDR 0x00007FFF -#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) -#define I2C_SLAVE_ADDR_V 0x7FFF +/** I2C_SLAVE_ADDR_REG register + * Local slave address setting + */ +#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) +/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ +#define I2C_SLAVE_ADDR 0x00007FFFU +#define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) +#define I2C_SLAVE_ADDR_V 0x00007FFFU #define I2C_SLAVE_ADDR_S 0 +/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) +#define I2C_ADDR_10BIT_EN_V 0x00000001U +#define I2C_ADDR_10BIT_EN_S 31 -#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) -/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ -/*description: The received data in I2C slave mode..*/ -#define I2C_SLAVE_RW_POINT 0x000000FF -#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) -#define I2C_SLAVE_RW_POINT_V 0xFF -#define I2C_SLAVE_RW_POINT_S 22 -/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ -/*description: This is the offset address of APB bus writing to txfifo..*/ -#define I2C_TXFIFO_WADDR 0x0000001F -#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) -#define I2C_TXFIFO_WADDR_V 0x1F -#define I2C_TXFIFO_WADDR_S 15 -/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ -/*description: This is the offset address of i2c module reading from txfifo..*/ -#define I2C_TXFIFO_RADDR 0x0000001F -#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) -#define I2C_TXFIFO_RADDR_V 0x1F -#define I2C_TXFIFO_RADDR_S 10 -/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ -/*description: This is the offset address of i2c module receiving data and writing to rxfifo..*/ -#define I2C_RXFIFO_WADDR 0x0000001F -#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) -#define I2C_RXFIFO_WADDR_V 0x1F -#define I2C_RXFIFO_WADDR_S 5 -/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ -/*description: This is the offset address of the APB reading from rxfifo.*/ -#define I2C_RXFIFO_RADDR 0x0000001F -#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) -#define I2C_RXFIFO_RADDR_V 0x1F +/** I2C_FIFO_ST_REG register + * FIFO status register. + */ +#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) +/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ +#define I2C_RXFIFO_RADDR 0x0000001FU +#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) +#define I2C_RXFIFO_RADDR_V 0x0000001FU #define I2C_RXFIFO_RADDR_S 0 +/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ +#define I2C_RXFIFO_WADDR 0x0000001FU +#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) +#define I2C_RXFIFO_WADDR_V 0x0000001FU +#define I2C_RXFIFO_WADDR_S 5 +/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ +#define I2C_TXFIFO_RADDR 0x0000001FU +#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) +#define I2C_TXFIFO_RADDR_V 0x0000001FU +#define I2C_TXFIFO_RADDR_S 10 +/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ +#define I2C_TXFIFO_WADDR 0x0000001FU +#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) +#define I2C_TXFIFO_WADDR_V 0x0000001FU +#define I2C_TXFIFO_WADDR_S 15 +/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ +#define I2C_SLAVE_RW_POINT 0x000000FFU +#define I2C_SLAVE_RW_POINT_M (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S) +#define I2C_SLAVE_RW_POINT_V 0x000000FFU +#define I2C_SLAVE_RW_POINT_S 22 -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) -/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ -/*description: The control enable bit of FIFO pointer in non-fifo access mode. This bit control -s the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and -empty..*/ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (BIT(14)) -#define I2C_FIFO_PRT_EN_V 0x1 -#define I2C_FIFO_PRT_EN_S 14 -/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to reset tx-fifo..*/ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (BIT(13)) -#define I2C_TX_FIFO_RST_V 0x1 -#define I2C_TX_FIFO_RST_S 13 -/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to reset rx-fifo..*/ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (BIT(12)) -#define I2C_RX_FIFO_RST_V 0x1 -#define I2C_RX_FIFO_RST_S 12 -/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: When this bit is set to 1, the byte received after the I2C address byte represen -ts the offset address in the I2C Slave RAM. .*/ -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_V 0x1 -#define I2C_FIFO_ADDR_CFG_EN_S 11 -/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to enable APB nonfifo access. .*/ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (BIT(10)) -#define I2C_NONFIFO_EN_V 0x1 -#define I2C_NONFIFO_EN_S 10 -/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ -/*description: The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_pr -t_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfi -fo_wm_int_raw bit will be valid. .*/ -#define I2C_TXFIFO_WM_THRHD 0x0000001F -#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) -#define I2C_TXFIFO_WM_THRHD_V 0x1F -#define I2C_TXFIFO_WM_THRHD_S 5 -/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ -/*description: The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_pr -t_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfif -o_wm_int_raw bit will be valid. .*/ -#define I2C_RXFIFO_WM_THRHD 0x0000001F -#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) -#define I2C_RXFIFO_WM_THRHD_V 0x1F +/** I2C_FIFO_CONF_REG register + * FIFO configuration register. + */ +#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) +/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ +#define I2C_RXFIFO_WM_THRHD 0x0000001FU +#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) +#define I2C_RXFIFO_WM_THRHD_V 0x0000001FU #define I2C_RXFIFO_WM_THRHD_S 0 +/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ +#define I2C_TXFIFO_WM_THRHD 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) +#define I2C_TXFIFO_WM_THRHD_V 0x0000001FU +#define I2C_TXFIFO_WM_THRHD_S 5 +/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) +#define I2C_NONFIFO_EN_V 0x00000001U +#define I2C_NONFIFO_EN_S 10 +/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) +#define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) +#define I2C_RX_FIFO_RST_V 0x00000001U +#define I2C_RX_FIFO_RST_S 12 +/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) +#define I2C_TX_FIFO_RST_V 0x00000001U +#define I2C_TX_FIFO_RST_S 13 +/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) +#define I2C_FIFO_PRT_EN_V 0x00000001U +#define I2C_FIFO_PRT_EN_S 14 -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) -/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: The value of rx FIFO read data..*/ -#define I2C_FIFO_RDATA 0x000000FF -#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) -#define I2C_FIFO_RDATA_V 0xFF +/** I2C_DATA_REG register + * Rx FIFO read data. + */ +#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) +/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ +#define I2C_FIFO_RDATA 0x000000FFU +#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) +#define I2C_FIFO_RDATA_V 0x000000FFU #define I2C_FIFO_RDATA_S 0 -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) -/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt..*/ -#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_V 0x1 -#define I2C_GENERAL_CALL_INT_RAW_S 17 -/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 -#define I2C_SLAVE_STRETCH_INT_RAW_S 16 -/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_DET_START_INT interrupt..*/ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (BIT(15)) -#define I2C_DET_START_INT_RAW_V 0x1 -#define I2C_DET_START_INT_RAW_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt..*/ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt..*/ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt..*/ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt..*/ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (BIT(10)) -#define I2C_NACK_INT_RAW_V 0x1 -#define I2C_NACK_INT_RAW_S 10 -/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt..*/ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (BIT(9)) -#define I2C_TRANS_START_INT_RAW_V 0x1 -#define I2C_TRANS_START_INT_RAW_S 9 -/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. .*/ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_V 0x1 -#define I2C_TIME_OUT_INT_RAW_S 8 -/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. .*/ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (BIT(3)) -#define I2C_END_DETECT_INT_RAW_V 0x1 -#define I2C_END_DETECT_INT_RAW_S 3 -/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt..*/ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ -/*description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt..*/ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_V 0x1 -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt..*/ +/** I2C_INT_RAW_REG register + * Raw interrupt status + */ +#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) +/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ #define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_V 0x1 +#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) +#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U #define I2C_RXFIFO_WM_INT_RAW_S 0 +/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) +#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_WM_INT_RAW_S 1 +/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) +#define I2C_END_DETECT_INT_RAW_V 0x00000001U +#define I2C_END_DETECT_INT_RAW_S 3 +/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) +#define I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define I2C_TIME_OUT_INT_RAW_S 8 +/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) +#define I2C_TRANS_START_INT_RAW_V 0x00000001U +#define I2C_TRANS_START_INT_RAW_S 9 +/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) +#define I2C_NACK_INT_RAW_V 0x00000001U +#define I2C_NACK_INT_RAW_S 10 +/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_RAW_S 11 +/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_RAW_S 12 +/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) +#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) +#define I2C_DET_START_INT_RAW_V 0x00000001U +#define I2C_DET_START_INT_RAW_S 15 +/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 +/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S) +#define I2C_GENERAL_CALL_INT_RAW_V 0x00000001U +#define I2C_GENERAL_CALL_INT_RAW_S 17 -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) -/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit for I2C_GENARAL_CALL_INT interrupt..*/ -#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_V 0x1 -#define I2C_GENERAL_CALL_INT_CLR_S 17 -/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 -#define I2C_SLAVE_STRETCH_INT_CLR_S 16 -/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_DET_START_INT interrupt..*/ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (BIT(15)) -#define I2C_DET_START_INT_CLR_V 0x1 -#define I2C_DET_START_INT_CLR_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt..*/ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt..*/ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt..*/ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt..*/ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (BIT(10)) -#define I2C_NACK_INT_CLR_V 0x1 -#define I2C_NACK_INT_CLR_S 10 -/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_TRANS_START_INT interrupt..*/ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (BIT(9)) -#define I2C_TRANS_START_INT_CLR_V 0x1 -#define I2C_TRANS_START_INT_CLR_S 9 -/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. .*/ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_V 0x1 -#define I2C_TIME_OUT_INT_CLR_S 8 -/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. .*/ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (BIT(3)) -#define I2C_END_DETECT_INT_CLR_V 0x1 -#define I2C_END_DETECT_INT_CLR_S 3 -/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt..*/ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt..*/ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_V 0x1 -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt..*/ +/** I2C_INT_CLR_REG register + * Interrupt clear bits + */ +#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) +/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ #define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_V 0x1 +#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) +#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U #define I2C_RXFIFO_WM_INT_CLR_S 0 +/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) +#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_WM_INT_CLR_S 1 +/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) +#define I2C_END_DETECT_INT_CLR_V 0x00000001U +#define I2C_END_DETECT_INT_CLR_S 3 +/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) +#define I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define I2C_TIME_OUT_INT_CLR_S 8 +/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) +#define I2C_TRANS_START_INT_CLR_V 0x00000001U +#define I2C_TRANS_START_INT_CLR_S 9 +/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) +#define I2C_NACK_INT_CLR_V 0x00000001U +#define I2C_NACK_INT_CLR_S 10 +/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_CLR_S 11 +/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_CLR_S 12 +/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) +#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) +#define I2C_DET_START_INT_CLR_V 0x00000001U +#define I2C_DET_START_INT_CLR_S 15 +/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 +/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S) +#define I2C_GENERAL_CALL_INT_CLR_V 0x00000001U +#define I2C_GENERAL_CALL_INT_CLR_S 17 -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) -/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt..*/ -#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_V 0x1 -#define I2C_GENERAL_CALL_INT_ENA_S 17 -/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ENA_S 16 -/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_DET_START_INT interrupt..*/ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (BIT(15)) -#define I2C_DET_START_INT_ENA_V 0x1 -#define I2C_DET_START_INT_ENA_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt..*/ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt..*/ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt..*/ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt..*/ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (BIT(10)) -#define I2C_NACK_INT_ENA_V 0x1 -#define I2C_NACK_INT_ENA_S 10 -/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt..*/ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (BIT(9)) -#define I2C_TRANS_START_INT_ENA_V 0x1 -#define I2C_TRANS_START_INT_ENA_S 9 -/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. .*/ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_V 0x1 -#define I2C_TIME_OUT_INT_ENA_S 8 -/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. .*/ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (BIT(3)) -#define I2C_END_DETECT_INT_ENA_V 0x1 -#define I2C_END_DETECT_INT_ENA_S 3 -/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt..*/ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt..*/ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_V 0x1 -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt..*/ +/** I2C_INT_ENA_REG register + * Interrupt enable bits + */ +#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) +/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ #define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_V 0x1 +#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) +#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U #define I2C_RXFIFO_WM_INT_ENA_S 0 +/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) +#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ENA_S 1 +/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) +#define I2C_END_DETECT_INT_ENA_V 0x00000001U +#define I2C_END_DETECT_INT_ENA_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) +#define I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define I2C_TIME_OUT_INT_ENA_S 8 +/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) +#define I2C_TRANS_START_INT_ENA_V 0x00000001U +#define I2C_TRANS_START_INT_ENA_S 9 +/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) +#define I2C_NACK_INT_ENA_V 0x00000001U +#define I2C_NACK_INT_ENA_S 10 +/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ENA_S 11 +/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ENA_S 12 +/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) +#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) +#define I2C_DET_START_INT_ENA_V 0x00000001U +#define I2C_DET_START_INT_ENA_S 15 +/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 +/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S) +#define I2C_GENERAL_CALL_INT_ENA_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ENA_S 17 -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) -/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt..*/ -#define I2C_GENERAL_CALL_INT_ST (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_V 0x1 -#define I2C_GENERAL_CALL_INT_ST_S 17 -/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ST_S 16 -/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_DET_START_INT interrupt..*/ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (BIT(15)) -#define I2C_DET_START_INT_ST_V 0x1 -#define I2C_DET_START_INT_ST_S 15 -/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt..*/ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt..*/ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_ST_TO_INT_ST_S 13 -/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt..*/ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_V 0x1 -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt..*/ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_V 0x1 -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt..*/ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (BIT(10)) -#define I2C_NACK_INT_ST_V 0x1 -#define I2C_NACK_INT_ST_S 10 -/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt..*/ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (BIT(9)) -#define I2C_TRANS_START_INT_ST_V 0x1 -#define I2C_TRANS_START_INT_ST_S 9 -/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. .*/ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (BIT(8)) -#define I2C_TIME_OUT_INT_ST_V 0x1 -#define I2C_TIME_OUT_INT_ST_S 8 -/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt..*/ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. .*/ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. .*/ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (BIT(3)) -#define I2C_END_DETECT_INT_ST_V 0x1 -#define I2C_END_DETECT_INT_ST_S 3 -/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt..*/ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_V 0x1 -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt..*/ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_V 0x1 -#define I2C_TXFIFO_WM_INT_ST_S 1 -/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt..*/ +/** I2C_INT_STATUS_REG register + * Status of captured I2C communication events + */ +#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) +/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ #define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_V 0x1 +#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) +#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U #define I2C_RXFIFO_WM_INT_ST_S 0 +/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) +#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define I2C_TXFIFO_WM_INT_ST_S 1 +/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) +#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) +#define I2C_END_DETECT_INT_ST_V 0x00000001U +#define I2C_END_DETECT_INT_ST_S 3 +/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) +#define I2C_TIME_OUT_INT_ST_V 0x00000001U +#define I2C_TIME_OUT_INT_ST_S 8 +/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) +#define I2C_TRANS_START_INT_ST_V 0x00000001U +#define I2C_TRANS_START_INT_ST_S 9 +/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) +#define I2C_NACK_INT_ST_V 0x00000001U +#define I2C_NACK_INT_ST_S 10 +/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) +#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define I2C_TXFIFO_OVF_INT_ST_S 11 +/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) +#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define I2C_RXFIFO_UDF_INT_ST_S 12 +/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) +#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_ST_TO_INT_ST_S 13 +/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) +#define I2C_DET_START_INT_ST_V 0x00000001U +#define I2C_DET_START_INT_ST_S 15 +/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x00000001U +#define I2C_SLAVE_STRETCH_INT_ST_S 16 +/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S) +#define I2C_GENERAL_CALL_INT_ST_V 0x00000001U +#define I2C_GENERAL_CALL_INT_ST_S 17 -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) -/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: This register is used to configure the time to hold the data after the negative; - edge of SCL, in I2C module clock cycles. .*/ -#define I2C_SDA_HOLD_TIME 0x000001FF -#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) -#define I2C_SDA_HOLD_TIME_V 0x1FF +/** I2C_SDA_HOLD_REG register + * Configures the hold time after a negative SCL edge. + */ +#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) +/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ +#define I2C_SDA_HOLD_TIME 0x000001FFU +#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) +#define I2C_SDA_HOLD_TIME_V 0x000001FFU #define I2C_SDA_HOLD_TIME_S 0 -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) -/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: This register is used to configure for how long SDA is sampled, in I2C module cl -ock cycles. .*/ -#define I2C_SDA_SAMPLE_TIME 0x000001FF -#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) -#define I2C_SDA_SAMPLE_TIME_V 0x1FF +/** I2C_SDA_SAMPLE_REG register + * Configures the sample time after a positive SCL edge. + */ +#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) +/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ +#define I2C_SDA_SAMPLE_TIME 0x000001FFU +#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) +#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU #define I2C_SDA_SAMPLE_TIME_S 0 -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) -/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ -/*description: This register is used to configure for the SCL_FSM's waiting period for SCL high - level in master mode, in I2C module clock cycles. .*/ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F -#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ -/*description: This register is used to configure for how long SCL remains high in master mode, - in I2C module clock cycles. .*/ -#define I2C_SCL_HIGH_PERIOD 0x000001FF -#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) -#define I2C_SCL_HIGH_PERIOD_V 0x1FF +/** I2C_SCL_HIGH_PERIOD_REG register + * Configures the high level width of SCL + */ +#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) +/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ +#define I2C_SCL_HIGH_PERIOD 0x000001FFU +#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) +#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU #define I2C_SCL_HIGH_PERIOD_S 0 +/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) -/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: This register is used to configure the time between the negative edge; of SDA an -d the negative edge of SCL for a START condition, in I2C module clock cycles. .*/ -#define I2C_SCL_START_HOLD_TIME 0x000001FF -#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) -#define I2C_SCL_START_HOLD_TIME_V 0x1FF +/** I2C_SCL_START_HOLD_REG register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) +/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ +#define I2C_SCL_START_HOLD_TIME 0x000001FFU +#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) +#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU #define I2C_SCL_START_HOLD_TIME_S 0 -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) -/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: This register is used to configure the time between the positive; edge of SCL an -d the negative edge of SDA for a RESTART condition, in I2C module clock cycles. .*/ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF -#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF +/** I2C_SCL_RSTART_SETUP_REG register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) +/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_S 0 -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) -/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: This register is used to configure the delay after the STOP condition,; in I2C m -odule clock cycles. .*/ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FF -#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) -#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF +/** I2C_SCL_STOP_HOLD_REG register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) +/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ +#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) +#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_S 0 -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) -/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ -/*description: This register is used to configure the time between the positive edge; of SCL an -d the positive edge of SDA, in I2C module clock cycles. .*/ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FF -#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) -#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF +/** I2C_SCL_STOP_SETUP_REG register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) +/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ +#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) +#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU #define I2C_SCL_STOP_SETUP_TIME_S 0 -#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SDA. .*/ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (BIT(9)) -#define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 9 -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: This is the filter enable bit for SCL. .*/ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (BIT(8)) -#define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 8 -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ -/*description: When a pulse on the SDA input has smaller width than this register value; in I2C - module clock cycles, the I2C controller will ignore that pulse. .*/ -#define I2C_SDA_FILTER_THRES 0x0000000F -#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0xF -#define I2C_SDA_FILTER_THRES_S 4 -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: When a pulse on the SCL input has smaller width than this register value; in I2C - module clock cycles, the I2C controller will ignore that pulse. .*/ -#define I2C_SCL_FILTER_THRES 0x0000000F -#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0xF +/** I2C_FILTER_CFG_REG register + * SCL and SDA filter configuration register + */ +#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) +/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SCL_FILTER_THRES 0x0000000FU +#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) +#define I2C_SCL_FILTER_THRES_V 0x0000000FU #define I2C_SCL_FILTER_THRES_S 0 +/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ +#define I2C_SDA_FILTER_THRES 0x0000000FU +#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) +#define I2C_SDA_FILTER_THRES_V 0x0000000FU +#define I2C_SDA_FILTER_THRES_S 4 +/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) +#define I2C_SCL_FILTER_EN_V 0x00000001U +#define I2C_SCL_FILTER_EN_S 8 +/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) +#define I2C_SDA_FILTER_EN_V 0x00000001U +#define I2C_SDA_FILTER_EN_S 9 -#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) -/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: The clock switch for i2c module.*/ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (BIT(21)) -#define I2C_SCLK_ACTIVE_V 0x1 -#define I2C_SCLK_ACTIVE_S 21 -/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The clock selection for i2c module:0-XTAL;1-CLK_8MHz..*/ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (BIT(20)) -#define I2C_SCLK_SEL_V 0x1 -#define I2C_SCLK_SEL_S 20 -/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ -/*description: the denominator of the fractional part of the fractional divisor for i2c module.*/ -#define I2C_SCLK_DIV_B 0x0000003F -#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) -#define I2C_SCLK_DIV_B_V 0x3F -#define I2C_SCLK_DIV_B_S 14 -/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ -/*description: the numerator of the fractional part of the fractional divisor for i2c module.*/ -#define I2C_SCLK_DIV_A 0x0000003F -#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) -#define I2C_SCLK_DIV_A_V 0x3F -#define I2C_SCLK_DIV_A_S 8 -/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ -/*description: the integral part of the fractional divisor for i2c module.*/ -#define I2C_SCLK_DIV_NUM 0x000000FF -#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) -#define I2C_SCLK_DIV_NUM_V 0xFF +/** I2C_CLK_CONF_REG register + * I2C CLK configuration register + */ +#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) +/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_NUM 0x000000FFU +#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) +#define I2C_SCLK_DIV_NUM_V 0x000000FFU #define I2C_SCLK_DIV_NUM_S 0 +/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_A 0x0000003FU +#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) +#define I2C_SCLK_DIV_A_V 0x0000003FU +#define I2C_SCLK_DIV_A_S 8 +/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ +#define I2C_SCLK_DIV_B 0x0000003FU +#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) +#define I2C_SCLK_DIV_B_V 0x0000003FU +#define I2C_SCLK_DIV_B_S 14 +/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL;1-CLK_8MHz. + */ +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) +#define I2C_SCLK_SEL_V 0x00000001U +#define I2C_SCLK_SEL_S 20 +/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) +#define I2C_SCLK_ACTIVE_V 0x00000001U +#define I2C_SCLK_ACTIVE_S 21 -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) -/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 0 is done in I2C Master mode, this bit changes to high; level. .*/ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (BIT(31)) -#define I2C_COMMAND0_DONE_V 0x1 -#define I2C_COMMAND0_DONE_S 31 -/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 0. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND0 0x00003FFF -#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) -#define I2C_COMMAND0_V 0x3FFF +/** I2C_COMD0_REG register + * I2C command register 0 + */ +#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) +/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND0 0x00003FFFU +#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) +#define I2C_COMMAND0_V 0x00003FFFU #define I2C_COMMAND0_S 0 +/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) +#define I2C_COMMAND0_DONE_V 0x00000001U +#define I2C_COMMAND0_DONE_S 31 -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) -/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 1 is done in I2C Master mode, this bit changes to high; level. .*/ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (BIT(31)) -#define I2C_COMMAND1_DONE_V 0x1 -#define I2C_COMMAND1_DONE_S 31 -/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 1. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND1 0x00003FFF -#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) -#define I2C_COMMAND1_V 0x3FFF +/** I2C_COMD1_REG register + * I2C command register 1 + */ +#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) +/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND1 0x00003FFFU +#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) +#define I2C_COMMAND1_V 0x00003FFFU #define I2C_COMMAND1_S 0 +/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) +#define I2C_COMMAND1_DONE_V 0x00000001U +#define I2C_COMMAND1_DONE_S 31 -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) -/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 2 is done in I2C Master mode, this bit changes to high; Level..*/ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (BIT(31)) -#define I2C_COMMAND2_DONE_V 0x1 -#define I2C_COMMAND2_DONE_S 31 -/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 2. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND2 0x00003FFF -#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) -#define I2C_COMMAND2_V 0x3FFF +/** I2C_COMD2_REG register + * I2C command register 2 + */ +#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) +/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND2 0x00003FFFU +#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) +#define I2C_COMMAND2_V 0x00003FFFU #define I2C_COMMAND2_S 0 +/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) +#define I2C_COMMAND2_DONE_V 0x00000001U +#define I2C_COMMAND2_DONE_S 31 -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) -/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 3 is done in I2C Master mode, this bit changes to high; level. .*/ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (BIT(31)) -#define I2C_COMMAND3_DONE_V 0x1 -#define I2C_COMMAND3_DONE_S 31 -/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 3. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND3 0x00003FFF -#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) -#define I2C_COMMAND3_V 0x3FFF +/** I2C_COMD3_REG register + * I2C command register 3 + */ +#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) +/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND3 0x00003FFFU +#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) +#define I2C_COMMAND3_V 0x00003FFFU #define I2C_COMMAND3_S 0 +/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) +#define I2C_COMMAND3_DONE_V 0x00000001U +#define I2C_COMMAND3_DONE_S 31 -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) -/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 4 is done in I2C Master mode, this bit changes to high; level. .*/ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (BIT(31)) -#define I2C_COMMAND4_DONE_V 0x1 -#define I2C_COMMAND4_DONE_S 31 -/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 4. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND4 0x00003FFF -#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) -#define I2C_COMMAND4_V 0x3FFF +/** I2C_COMD4_REG register + * I2C command register 4 + */ +#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) +/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND4 0x00003FFFU +#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) +#define I2C_COMMAND4_V 0x00003FFFU #define I2C_COMMAND4_S 0 +/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) +#define I2C_COMMAND4_DONE_V 0x00000001U +#define I2C_COMMAND4_DONE_S 31 -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) -/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 5 is done in I2C Master mode, this bit changes to high level. .*/ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (BIT(31)) -#define I2C_COMMAND5_DONE_V 0x1 -#define I2C_COMMAND5_DONE_S 31 -/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 5. It consists of three parts:; op_code is the co -mmand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the n -umber of bytes that need to be sent or received.; ack_check_en, ack_exp and ack -are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND5 0x00003FFF -#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) -#define I2C_COMMAND5_V 0x3FFF +/** I2C_COMD5_REG register + * I2C command register 5 + */ +#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) +/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND5 0x00003FFFU +#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) +#define I2C_COMMAND5_V 0x00003FFFU #define I2C_COMMAND5_S 0 +/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) +#define I2C_COMMAND5_DONE_V 0x00000001U +#define I2C_COMMAND5_DONE_S 31 -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) -/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 6 is done in I2C Master mode, this bit changes to high level. .*/ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (BIT(31)) -#define I2C_COMMAND6_DONE_V 0x1 -#define I2C_COMMAND6_DONE_S 31 -/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 6. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND6 0x00003FFF -#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) -#define I2C_COMMAND6_V 0x3FFF +/** I2C_COMD6_REG register + * I2C command register 6 + */ +#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) +/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND6 0x00003FFFU +#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) +#define I2C_COMMAND6_V 0x00003FFFU #define I2C_COMMAND6_S 0 +/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) +#define I2C_COMMAND6_DONE_V 0x00000001U +#define I2C_COMMAND6_DONE_S 31 -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) -/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ -/*description: When command 7 is done in I2C Master mode, this bit changes to high level..*/ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (BIT(31)) -#define I2C_COMMAND7_DONE_V 0x1 -#define I2C_COMMAND7_DONE_S 31 -/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ -/*description: This is the content of command 7. It consists of three parts: ; op_code is the c -ommand, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.; Byte_num represents the -number of bytes that need to be sent or received.; ack_check_en, ack_exp and ack - are used to control the ACK bit. See I2C cmd structure for more; Information..*/ -#define I2C_COMMAND7 0x00003FFF -#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) -#define I2C_COMMAND7_V 0x3FFF +/** I2C_COMD7_REG register + * I2C command register 7 + */ +#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) +/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ +#define I2C_COMMAND7 0x00003FFFU +#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) +#define I2C_COMMAND7_V 0x00003FFFU #define I2C_COMMAND7_S 0 +/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) +#define I2C_COMMAND7_DONE_V 0x00000001U +#define I2C_COMMAND7_DONE_S 31 -#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) -/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: The threshold value of SCL_FSM state unchanged period. It should be o more than -23.*/ -#define I2C_SCL_ST_TO_REG 0x0000001F -#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) -#define I2C_SCL_ST_TO_REG_V 0x1F -#define I2C_SCL_ST_TO_REG_S 0 +/** I2C_SCL_ST_TIME_OUT_REG register + * SCL status time out register + */ +#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) +/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ +#define I2C_SCL_ST_TO_I2C 0x0000001FU +#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) +#define I2C_SCL_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_ST_TO_I2C_S 0 -#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) -/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ -/*description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more -than 23.*/ -#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F -#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) -#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F -#define I2C_SCL_MAIN_ST_TO_REG_S 0 +/** I2C_SCL_MAIN_ST_TIME_OUT_REG register + * SCL main status time out register + */ +#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) +/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ +#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) +#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU +#define I2C_SCL_MAIN_ST_TO_I2C_S 0 -#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) -/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not pow -er down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low..*/ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (BIT(7)) -#define I2C_SDA_PD_EN_V 0x1 -#define I2C_SDA_PD_EN_S 7 -/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not pow -er down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low..*/ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (BIT(6)) -#define I2C_SCL_PD_EN_V 0x1 -#define I2C_SCL_PD_EN_S 6 -/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ -/*description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst -_slv_en is 1..*/ -#define I2C_SCL_RST_SLV_NUM 0x0000001F -#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) -#define I2C_SCL_RST_SLV_NUM_V 0x1F -#define I2C_SCL_RST_SLV_NUM_S 1 -/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ -/*description: When I2C master is IDLE, set this bit to send out SCL pulses. The number of puls -es equals to reg_scl_rst_slv_num[4:0]..*/ +/** I2C_SCL_SP_CONF_REG register + * Power configuration register + */ +#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) +/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ #define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (BIT(0)) -#define I2C_SCL_RST_SLV_EN_V 0x1 +#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) +#define I2C_SCL_RST_SLV_EN_V 0x00000001U #define I2C_SCL_RST_SLV_EN_S 0 +/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ +#define I2C_SCL_RST_SLV_NUM 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) +#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define I2C_SCL_RST_SLV_NUM_S 1 +/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) +#define I2C_SCL_PD_EN_V 0x00000001U +#define I2C_SCL_PD_EN_S 6 +/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) +#define I2C_SDA_PD_EN_V 0x00000001U +#define I2C_SDA_PD_EN_S 7 -#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) -/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set the ACK level when slave controlling ACK level function enables..*/ -#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 -#define I2C_SLAVE_BYTE_ACK_LVL_S 13 -/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The enable bit for slave to control ACK level function..*/ -#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 -#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 -/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear the I2C slave SCL stretch function..*/ -#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 -/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL ou -tput line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch e -vent happens. The stretch cause can be seen in reg_stretch_cause..*/ -#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_EN_S 10 -/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: Configure the period of I2C slave stretching SCL line..*/ -#define I2C_STRETCH_PROTECT_NUM 0x000003FF -#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) -#define I2C_STRETCH_PROTECT_NUM_V 0x3FF +/** I2C_SCL_STRETCH_CONF_REG register + * Set SCL stretch of I2C slave + */ +#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) +/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ +#define I2C_STRETCH_PROTECT_NUM 0x000003FFU +#define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) +#define I2C_STRETCH_PROTECT_NUM_V 0x000003FFU #define I2C_STRETCH_PROTECT_NUM_S 0 +/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 +/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 +/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 +/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x00000001U +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ -/*description: This is the the version register..*/ -#define I2C_DATE 0xFFFFFFFF -#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) -#define I2C_DATE_V 0xFFFFFFFF +/** I2C_DATE_REG register + * Version register + */ +#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) +/** I2C_DATE : R/W; bitpos: [31:0]; default: 537330177; + * This is the the version register. + */ +#define I2C_DATE 0xFFFFFFFFU +#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) +#define I2C_DATE_V 0xFFFFFFFFU #define I2C_DATE_S 0 -#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) - -#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) +/** I2C_TXFIFO_START_ADDR_REG register + * I2C TXFIFO base address register + */ +#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) +/** I2C_TXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ +#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) +#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_TXFIFO_START_ADDR_S 0 +/** I2C_RXFIFO_START_ADDR_REG register + * I2C RXFIFO base address register + */ +#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) +/** I2C_RXFIFO_START_ADDR : RO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ +#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) +#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2C_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/esp32s3/include/soc/i2c_struct.h index f4b3f17900..27f6ce9d2b 100644 --- a/components/soc/esp32s3/include/soc/i2c_struct.h +++ b/components/soc/esp32s3/include/soc/i2c_struct.h @@ -1,412 +1,1190 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_I2C_STRUCT_H_ -#define _SOC_I2C_STRUCT_H_ - +/** Copyright 2021 Espressif Systems (Shanghai) CO LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t period : 9; /*This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } scl_low_period; - union { - struct { - uint32_t sda_force_out : 1; /*0: direct output; 1: open drain output.*/ - uint32_t scl_force_out : 1; /*0: direct output; 1: open drain output.*/ - uint32_t sample_scl_level : 1; /*This register is used to select the sample mode.; 1: sample SDA data on the SCL low level.; 0: sample SDA data on the SCL high level.*/ - uint32_t rx_full_ack_level : 1; /*This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold.*/ - uint32_t ms_mode : 1; /*Set this bit to configure the module as an I2C Master. Clear this bit to configure the; module as an I2C Slave. */ - uint32_t trans_start : 1; /*Set this bit to start sending the data in txfifo. */ - uint32_t tx_lsb_first : 1; /*This bit is used to control the sending mode for data needing to be sent. ; 1: send data from the least significant bit;; 0: send data from the most significant bit.*/ - uint32_t rx_lsb_first : 1; /*This bit is used to control the storage mode for received data.; 1: receive data from the least significant bit;; 0: receive data from the most significant bit.*/ - uint32_t clk_en : 1; /*Reserved*/ - uint32_t arbitration_en : 1; /*This is the enable bit for arbitration_lost.*/ - uint32_t fsm_rst : 1; /*This register is used to reset the scl FMS.*/ - uint32_t conf_upgate : 1; /*synchronization bit*/ - uint32_t slv_tx_auto_start_en : 1; /*This is the enable bit for slave to send data automatically*/ - uint32_t addr_10bit_rw_check_en : 1; /*This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol*/ - uint32_t addr_broadcasting_en : 1; /*This is the enable bit to support the 7bit general call function. */ - uint32_t reserved15 : 17; /*Reserved*/ - }; - uint32_t val; - } ctr; - union { - struct { - uint32_t resp_rec : 1; /*The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.*/ - uint32_t slave_rw : 1; /*When in slave mode, 1: master reads from slave; 0: master writes to slave.*/ - uint32_t reserved2 : 1; /*Reserved*/ - uint32_t arb_lost : 1; /*When the I2C controller loses control of SCL line, this register changes to 1.*/ - uint32_t bus_busy : 1; /*1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. */ - uint32_t slave_addressed : 1; /*When configured as an I2C Slave, and the address sent by the master is; equal to the address of the slave, then this bit will be of high level.*/ - uint32_t reserved6 : 1; /*Reserved*/ - uint32_t reserved7 : 1; /*Reserved*/ - uint32_t rx_fifo_cnt : 6; /*This field represents the amount of data needed to be sent. */ - uint32_t stretch_cause : 2; /*The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.*/ - uint32_t reserved16 : 2; /*Reserved*/ - uint32_t tx_fifo_cnt : 6; /*This field stores the amount of received data in RAM. */ - uint32_t scl_main_state_last : 3; /*This field indicates the states of the I2C module state machine. ; 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK*/ - uint32_t reserved27 : 1; /*Reserved*/ - uint32_t scl_state_last : 3; /*This field indicates the states of the state machine used to produce SCL.; 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop*/ - uint32_t reserved31 : 1; /*Reserved*/ - }; - uint32_t val; - } sr; - union { - struct { - uint32_t tout : 5; /*This register is used to configure the timeout for receiving a data bit in APB; clock cycles. */ - uint32_t time_out_en : 1; /*This is the enable bit for time out control.*/ - uint32_t reserved6 : 26; /*Reserved*/ - }; - uint32_t val; - } timeout; - union { - struct { - uint32_t addr : 15; /*When configured as an I2C Slave, this field is used to configure the slave address.*/ - uint32_t reserved15 : 16; /*Reserved*/ - uint32_t en_10bit : 1; /*This field is used to enable the slave 10-bit addressing mode in master mode. */ - }; - uint32_t val; - } slave_addr; - union { - struct { - uint32_t rx_fifo_raddr : 5; /*This is the offset address of the APB reading from rxfifo*/ - uint32_t rx_fifo_waddr : 5; /*This is the offset address of i2c module receiving data and writing to rxfifo.*/ - uint32_t tx_fifo_raddr : 5; /*This is the offset address of i2c module reading from txfifo.*/ - uint32_t tx_fifo_waddr : 5; /*This is the offset address of APB bus writing to txfifo.*/ - uint32_t reserved20 : 1; /*Reserved*/ - uint32_t reserved21 : 1; /*Reserved*/ - uint32_t slave_rw_point : 8; /*The received data in I2C slave mode.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } fifo_st; - union { - struct { - uint32_t rx_fifo_wm_thrhd : 5; /*The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. */ - uint32_t tx_fifo_wm_thrhd : 5; /*The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. */ - uint32_t nonfifo_en : 1; /*Set this bit to enable APB nonfifo access. */ - uint32_t fifo_addr_cfg_en : 1; /*When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. */ - uint32_t rx_fifo_rst : 1; /*Set this bit to reset rx-fifo.*/ - uint32_t tx_fifo_rst : 1; /*Set this bit to reset tx-fifo.*/ - uint32_t fifo_prt_en : 1; /*The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.*/ - uint32_t reserved15 : 5; /*Reserved*/ - uint32_t reserved20 : 6; /*Reserved*/ - uint32_t reserved26 : 1; /*Reserved*/ - uint32_t reserved27 : 5; /*Reserved*/ - }; - uint32_t val; - } fifo_conf; - union { - struct { - uint32_t data : 8; /*The value of rx FIFO read data.*/ - uint32_t reserved8 : 24; /*Reserved*/ - }; - uint32_t val; - } fifo_data; - union { - struct { - uint32_t rx_fifo_wm : 1; /*The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.*/ - uint32_t tx_fifo_wm : 1; /*The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.*/ - uint32_t rx_fifo_ovf : 1; /*The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.*/ - uint32_t end_detect : 1; /*The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t byte_trans_done : 1; /*The raw interrupt bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t arbitration_lost : 1; /*The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. */ - uint32_t mst_tx_fifo_udf : 1; /*The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t trans_complete : 1; /*The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t time_out : 1; /*The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. */ - uint32_t trans_start : 1; /*The raw interrupt bit for the I2C_TRANS_START_INT interrupt.*/ - uint32_t nack : 1; /*The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t tx_fifo_ovf : 1; /*The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.*/ - uint32_t rx_fifo_udf : 1; /*The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt.*/ - uint32_t scl_st_to : 1; /*The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.*/ - uint32_t scl_main_st_to : 1; /*The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/ - uint32_t det_start : 1; /*The raw interrupt bit for I2C_DET_START_INT interrupt.*/ - uint32_t slave_stretch : 1; /*The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t general_call : 1; /*The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.*/ - uint32_t reserved18 : 14; /*Reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rx_fifo_wm : 1; /*Set this bit to clear I2C_RXFIFO_WM_INT interrupt.*/ - uint32_t tx_fifo_wm : 1; /*Set this bit to clear I2C_TXFIFO_WM_INT interrupt.*/ - uint32_t rx_fifo_ovf : 1; /*Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.*/ - uint32_t end_detect : 1; /*Set this bit to clear the I2C_END_DETECT_INT interrupt. */ - uint32_t byte_trans_done : 1; /*Set this bit to clear the I2C_END_DETECT_INT interrupt. */ - uint32_t arbitration_lost : 1; /*Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. */ - uint32_t mst_tx_fifo_udf : 1; /*Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t trans_complete : 1; /*Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t time_out : 1; /*Set this bit to clear the I2C_TIME_OUT_INT interrupt. */ - uint32_t trans_start : 1; /*Set this bit to clear the I2C_TRANS_START_INT interrupt.*/ - uint32_t nack : 1; /*Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t tx_fifo_ovf : 1; /*Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.*/ - uint32_t rx_fifo_udf : 1; /*Set this bit to clear I2C_RXFIFO_UDF_INT interrupt.*/ - uint32_t scl_st_to : 1; /*Set this bit to clear I2C_SCL_ST_TO_INT interrupt.*/ - uint32_t scl_main_st_to : 1; /*Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.*/ - uint32_t det_start : 1; /*Set this bit to clear I2C_DET_START_INT interrupt.*/ - uint32_t slave_stretch : 1; /*Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t general_call : 1; /*Set this bit for I2C_GENARAL_CALL_INT interrupt.*/ - uint32_t reserved18 : 14; /*Reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t rx_fifo_wm : 1; /*The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.*/ - uint32_t tx_fifo_wm : 1; /*The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.*/ - uint32_t rx_fifo_ovf : 1; /*The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.*/ - uint32_t end_detect : 1; /*The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t byte_trans_done : 1; /*The interrupt enable bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t arbitration_lost : 1; /*The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. */ - uint32_t mst_tx_fifo_udf : 1; /*The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t trans_complete : 1; /*The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t time_out : 1; /*The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. */ - uint32_t trans_start : 1; /*The interrupt enable bit for the I2C_TRANS_START_INT interrupt.*/ - uint32_t nack : 1; /*The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t tx_fifo_ovf : 1; /*The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.*/ - uint32_t rx_fifo_udf : 1; /*The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt.*/ - uint32_t scl_st_to : 1; /*The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.*/ - uint32_t scl_main_st_to : 1; /*The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/ - uint32_t det_start : 1; /*The interrupt enable bit for I2C_DET_START_INT interrupt.*/ - uint32_t slave_stretch : 1; /*The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t general_call : 1; /*The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.*/ - uint32_t reserved18 : 14; /*Reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rx_fifo_wm : 1; /*The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.*/ - uint32_t tx_fifo_wm : 1; /*The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.*/ - uint32_t rx_fifo_ovf : 1; /*The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.*/ - uint32_t end_detect : 1; /*The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t byte_trans_done : 1; /*The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. */ - uint32_t arbitration_lost : 1; /*The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. */ - uint32_t mst_tx_fifo_udf : 1; /*The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t trans_complete : 1; /*The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.*/ - uint32_t time_out : 1; /*The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. */ - uint32_t trans_start : 1; /*The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.*/ - uint32_t nack : 1; /*The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t tx_fifo_ovf : 1; /*The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.*/ - uint32_t rx_fifo_udf : 1; /*The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt.*/ - uint32_t scl_st_to : 1; /*The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.*/ - uint32_t scl_main_st_to : 1; /*The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.*/ - uint32_t det_start : 1; /*The masked interrupt status bit for I2C_DET_START_INT interrupt.*/ - uint32_t slave_stretch : 1; /*The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.*/ - uint32_t general_call : 1; /*The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.*/ - uint32_t reserved18 : 14; /*Reserved*/ - }; - uint32_t val; - } int_status; - union { - struct { - uint32_t time : 9; /*This register is used to configure the time to hold the data after the negative; edge of SCL, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } sda_hold; - union { - struct { - uint32_t time : 9; /*This register is used to configure for how long SDA is sampled, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } sda_sample; - union { - struct { - uint32_t period : 9; /*This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. */ - uint32_t scl_wait_high_period : 7; /*This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. */ - uint32_t reserved16 : 16; /*Reserved*/ - }; - uint32_t val; - } scl_high_period; - uint32_t reserved_3c; - union { - struct { - uint32_t time : 9; /*This register is used to configure the time between the negative edge; of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } scl_start_hold; - union { - struct { - uint32_t time : 9; /*This register is used to configure the time between the positive; edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } scl_rstart_setup; - union { - struct { - uint32_t time : 9; /*This register is used to configure the delay after the STOP condition,; in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } scl_stop_hold; - union { - struct { - uint32_t time : 9; /*This register is used to configure the time between the positive edge; of SCL and the positive edge of SDA, in I2C module clock cycles. */ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } scl_stop_setup; - union { - struct { - uint32_t scl_thres : 4; /*When a pulse on the SCL input has smaller width than this register value; in I2C module clock cycles, the I2C controller will ignore that pulse. */ - uint32_t sda_thres : 4; /*When a pulse on the SDA input has smaller width than this register value; in I2C module clock cycles, the I2C controller will ignore that pulse. */ - uint32_t scl_en : 1; /*This is the filter enable bit for SCL. */ - uint32_t sda_en : 1; /*This is the filter enable bit for SDA. */ - uint32_t reserved10 : 22; /*Reserved*/ - }; - uint32_t val; - } filter_cfg; - union { - struct { - uint32_t sclk_div_num : 8; /*the integral part of the fractional divisor for i2c module*/ - uint32_t sclk_div_a : 6; /*the numerator of the fractional part of the fractional divisor for i2c module*/ - uint32_t sclk_div_b : 6; /*the denominator of the fractional part of the fractional divisor for i2c module*/ - uint32_t sclk_sel : 1; /*The clock selection for i2c module:0-XTAL;1-CLK_8MHz.*/ - uint32_t sclk_active : 1; /*The clock switch for i2c module*/ - uint32_t reserved22 : 10; /*Reserved*/ - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ - uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ - uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ - uint32_t reserved14: 17; - uint32_t done: 1; - }; - uint32_t val; - } command[8]; - union { - struct { - uint32_t scl_st_to : 5; /*The threshold value of SCL_FSM state unchanged period. It should be o more than 23*/ - uint32_t reserved5 : 27; /*Reserved*/ - }; - uint32_t val; - } scl_st_time_out; - union { - struct { - uint32_t scl_main_st_to : 5; /*The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23*/ - uint32_t reserved5 : 27; /*Reserved*/ - }; - uint32_t val; - } scl_main_st_time_out; - union { - struct { - uint32_t scl_rst_slv_en : 1; /*When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0].*/ - uint32_t scl_rst_slv_num : 5; /*Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1.*/ - uint32_t scl_pd_en : 1; /*The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.*/ - uint32_t sda_pd_en : 1; /*The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.*/ - uint32_t reserved8 : 24; /*Reserved*/ - }; - uint32_t val; - } scl_sp_conf; - union { - struct { - uint32_t stretch_protect_num : 10; /*Configure the period of I2C slave stretching SCL line.*/ - uint32_t slave_scl_stretch_en : 1; /*The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause.*/ - uint32_t slave_scl_stretch_clr : 1; /*Set this bit to clear the I2C slave SCL stretch function.*/ - uint32_t slave_byte_ack_ctl_en : 1; /*The enable bit for slave to control ACK level function.*/ - uint32_t slave_byte_ack_level : 1; /*Set the ACK level when slave controlling ACK level function enables.*/ - uint32_t reserved14 : 18; /*Reserved*/ - }; - uint32_t val; - } scl_stretch_conf; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t date; - uint32_t reserved_fc; - uint32_t txfifo_start_addr; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t rxfifo_start_addr; +/** Group: Timing registers */ +/** Type of scl_low_period register + * Configures the low level width of the SCL + * Clock + */ +typedef union { + struct { + /** scl_low_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains low in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_low_period:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_low_period_reg_t; + +/** Type of sda_hold register + * Configures the hold time after a negative SCL edge. + */ +typedef union { + struct { + /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure the time to hold the data after the negative + * edge of SCL, in I2C module clock cycles. + */ + uint32_t sda_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_hold_reg_t; + +/** Type of sda_sample register + * Configures the sample time after a positive SCL edge. + */ +typedef union { + struct { + /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SDA is sampled, in I2C module clock + * cycles. + */ + uint32_t sda_sample_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_sda_sample_reg_t; + +/** Type of scl_high_period register + * Configures the high level width of SCL + */ +typedef union { + struct { + /** scl_high_period : R/W; bitpos: [8:0]; default: 0; + * This register is used to configure for how long SCL remains high in master mode, in + * I2C module clock cycles. + */ + uint32_t scl_high_period:9; + /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; + * This register is used to configure for the SCL_FSM's waiting period for SCL high + * level in master mode, in I2C module clock cycles. + */ + uint32_t scl_wait_high_period:7; + uint32_t reserved_16:16; + }; + uint32_t val; +} i2c_scl_high_period_reg_t; + +/** Type of scl_start_hold register + * Configures the delay between the SDA and SCL negative edge for a start condition + */ +typedef union { + struct { + /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the negative edge + * of SDA and the negative edge of SCL for a START condition, in I2C module clock + * cycles. + */ + uint32_t scl_start_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_start_hold_reg_t; + +/** Type of scl_rstart_setup register + * Configures the delay between the positive + * edge of SCL and the negative edge of SDA + */ +typedef union { + struct { + /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive + * edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module + * clock cycles. + */ + uint32_t scl_rstart_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_rstart_setup_reg_t; + +/** Type of scl_stop_hold register + * Configures the delay after the SCL clock + * edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the delay after the STOP condition, + * in I2C module clock cycles. + */ + uint32_t scl_stop_hold_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_hold_reg_t; + +/** Type of scl_stop_setup register + * Configures the delay between the SDA and + * SCL positive edge for a stop condition + */ +typedef union { + struct { + /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8; + * This register is used to configure the time between the positive edge + * of SCL and the positive edge of SDA, in I2C module clock cycles. + */ + uint32_t scl_stop_setup_time:9; + uint32_t reserved_9:23; + }; + uint32_t val; +} i2c_scl_stop_setup_reg_t; + +/** Type of scl_st_time_out register + * SCL status time out register + */ +typedef union { + struct { + /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + */ + uint32_t scl_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_st_time_out_reg_t; + +/** Type of scl_main_st_time_out register + * SCL main status time out register + */ +typedef union { + struct { + /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; + * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more + * than 23 + */ + uint32_t scl_main_st_to_i2c:5; + uint32_t reserved_5:27; + }; + uint32_t val; +} i2c_scl_main_st_time_out_reg_t; + + +/** Group: Configuration registers */ +/** Type of ctr register + * Transmission setting + */ +typedef union { + struct { + /** sda_force_out : R/W; bitpos: [0]; default: 1; + * 0: direct output; 1: open drain output. + */ + uint32_t sda_force_out:1; + /** scl_force_out : R/W; bitpos: [1]; default: 1; + * 0: direct output; 1: open drain output. + */ + uint32_t scl_force_out:1; + /** sample_scl_level : R/W; bitpos: [2]; default: 0; + * This register is used to select the sample mode. + * 1: sample SDA data on the SCL low level. + * 0: sample SDA data on the SCL high level. + */ + uint32_t sample_scl_level:1; + /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; + * This register is used to configure the ACK value that need to sent by master when + * the rx_fifo_cnt has reached the threshold. + */ + uint32_t rx_full_ack_level:1; + /** ms_mode : R/W; bitpos: [4]; default: 0; + * Set this bit to configure the module as an I2C Master. Clear this bit to configure + * the + * module as an I2C Slave. + */ + uint32_t ms_mode:1; + /** trans_start : WT; bitpos: [5]; default: 0; + * Set this bit to start sending the data in txfifo. + */ + uint32_t trans_start:1; + /** tx_lsb_first : R/W; bitpos: [6]; default: 0; + * This bit is used to control the sending mode for data needing to be sent. + * 1: send data from the least significant bit; + * 0: send data from the most significant bit. + */ + uint32_t tx_lsb_first:1; + /** rx_lsb_first : R/W; bitpos: [7]; default: 0; + * This bit is used to control the storage mode for received data. + * 1: receive data from the least significant bit; + * 0: receive data from the most significant bit. + */ + uint32_t rx_lsb_first:1; + /** clk_en : R/W; bitpos: [8]; default: 0; + * Reserved + */ + uint32_t clk_en:1; + /** arbitration_en : R/W; bitpos: [9]; default: 1; + * This is the enable bit for arbitration_lost. + */ + uint32_t arbitration_en:1; + /** fsm_rst : WT; bitpos: [10]; default: 0; + * This register is used to reset the scl FMS. + */ + uint32_t fsm_rst:1; + /** conf_upgate : WT; bitpos: [11]; default: 0; + * synchronization bit + */ + uint32_t conf_upgate:1; + /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; + * This is the enable bit for slave to send data automatically + */ + uint32_t slv_tx_auto_start_en:1; + /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; + * This is the enable bit to check if the r/w bit of 10bit addressing consists with + * I2C protocol + */ + uint32_t addr_10bit_rw_check_en:1; + /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; + * This is the enable bit to support the 7bit general call function. + */ + uint32_t addr_broadcasting_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_ctr_reg_t; + +/** Type of to register + * Setting time out control for receiving data. + */ +typedef union { + struct { + /** time_out_value : R/W; bitpos: [4:0]; default: 16; + * This register is used to configure the timeout for receiving a data bit in APB + * clock cycles. + */ + uint32_t time_out_value:5; + /** time_out_en : R/W; bitpos: [5]; default: 0; + * This is the enable bit for time out control. + */ + uint32_t time_out_en:1; + uint32_t reserved_6:26; + }; + uint32_t val; +} i2c_to_reg_t; + +/** Type of slave_addr register + * Local slave address setting + */ +typedef union { + struct { + /** slave_addr : R/W; bitpos: [14:0]; default: 0; + * When configured as an I2C Slave, this field is used to configure the slave address. + */ + uint32_t slave_addr:15; + uint32_t reserved_15:16; + /** addr_10bit_en : R/W; bitpos: [31]; default: 0; + * This field is used to enable the slave 10-bit addressing mode in master mode. + */ + uint32_t addr_10bit_en:1; + }; + uint32_t val; +} i2c_slave_addr_reg_t; + +/** Type of fifo_conf register + * FIFO configuration register. + */ +typedef union { + struct { + /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11; + * The water mark threshold of rx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than + * reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. + */ + uint32_t rxfifo_wm_thrhd:5; + /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4; + * The water mark threshold of tx FIFO in nonfifo access mode. When + * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than + * reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. + */ + uint32_t txfifo_wm_thrhd:5; + /** nonfifo_en : R/W; bitpos: [10]; default: 0; + * Set this bit to enable APB nonfifo access. + */ + uint32_t nonfifo_en:1; + /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; + * When this bit is set to 1, the byte received after the I2C address byte represents + * the offset address in the I2C Slave RAM. + */ + uint32_t fifo_addr_cfg_en:1; + /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; + * Set this bit to reset rx-fifo. + */ + uint32_t rx_fifo_rst:1; + /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; + * Set this bit to reset tx-fifo. + */ + uint32_t tx_fifo_rst:1; + /** fifo_prt_en : R/W; bitpos: [14]; default: 1; + * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls + * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. + */ + uint32_t fifo_prt_en:1; + uint32_t reserved_15:17; + }; + uint32_t val; +} i2c_fifo_conf_reg_t; + +/** Type of filter_cfg register + * SCL and SDA filter configuration register + */ +typedef union { + struct { + /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0; + * When a pulse on the SCL input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t scl_filter_thres:4; + /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; + * When a pulse on the SDA input has smaller width than this register value + * in I2C module clock cycles, the I2C controller will ignore that pulse. + */ + uint32_t sda_filter_thres:4; + /** scl_filter_en : R/W; bitpos: [8]; default: 1; + * This is the filter enable bit for SCL. + */ + uint32_t scl_filter_en:1; + /** sda_filter_en : R/W; bitpos: [9]; default: 1; + * This is the filter enable bit for SDA. + */ + uint32_t sda_filter_en:1; + uint32_t reserved_10:22; + }; + uint32_t val; +} i2c_filter_cfg_reg_t; + +/** Type of clk_conf register + * I2C CLK configuration register + */ +typedef union { + struct { + /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; + * the integral part of the fractional divisor for i2c module + */ + uint32_t sclk_div_num:8; + /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; + * the numerator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_a:6; + /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; + * the denominator of the fractional part of the fractional divisor for i2c module + */ + uint32_t sclk_div_b:6; + /** sclk_sel : R/W; bitpos: [20]; default: 0; + * The clock selection for i2c module:0-XTAL;1-CLK_8MHz. + */ + uint32_t sclk_sel:1; + /** sclk_active : R/W; bitpos: [21]; default: 1; + * The clock switch for i2c module + */ + uint32_t sclk_active:1; + uint32_t reserved_22:10; + }; + uint32_t val; +} i2c_clk_conf_reg_t; + +/** Type of scl_sp_conf register + * Power configuration register + */ +typedef union { + struct { + /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0; + * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses + * equals to reg_scl_rst_slv_num[4:0]. + */ + uint32_t scl_rst_slv_en:1; + /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; + * Configure the pulses of SCL generated in I2C master mode. Valid when + * reg_scl_rst_slv_en is 1. + */ + uint32_t scl_rst_slv_num:5; + /** scl_pd_en : R/W; bitpos: [6]; default: 0; + * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power + * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. + */ + uint32_t scl_pd_en:1; + /** sda_pd_en : R/W; bitpos: [7]; default: 0; + * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power + * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. + */ + uint32_t sda_pd_en:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_scl_sp_conf_reg_t; + +/** Type of scl_stretch_conf register + * Set SCL stretch of I2C slave + */ +typedef union { + struct { + /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; + * Configure the period of I2C slave stretching SCL line. + */ + uint32_t stretch_protect_num:10; + /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; + * The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL + * output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch + * event happens. The stretch cause can be seen in reg_stretch_cause. + */ + uint32_t slave_scl_stretch_en:1; + /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear the I2C slave SCL stretch function. + */ + uint32_t slave_scl_stretch_clr:1; + /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; + * The enable bit for slave to control ACK level function. + */ + uint32_t slave_byte_ack_ctl_en:1; + /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; + * Set the ACK level when slave controlling ACK level function enables. + */ + uint32_t slave_byte_ack_lvl:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} i2c_scl_stretch_conf_reg_t; + + +/** Group: Status registers */ +/** Type of sr register + * Describe I2C work status. + */ +typedef union { + struct { + /** resp_rec : RO; bitpos: [0]; default: 0; + * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. + */ + uint32_t resp_rec:1; + /** slave_rw : RO; bitpos: [1]; default: 0; + * When in slave mode, 1: master reads from slave; 0: master writes to slave. + */ + uint32_t slave_rw:1; + uint32_t reserved_2:1; + /** arb_lost : RO; bitpos: [3]; default: 0; + * When the I2C controller loses control of SCL line, this register changes to 1. + */ + uint32_t arb_lost:1; + /** bus_busy : RO; bitpos: [4]; default: 0; + * 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state. + */ + uint32_t bus_busy:1; + /** slave_addressed : RO; bitpos: [5]; default: 0; + * When configured as an I2C Slave, and the address sent by the master is + * equal to the address of the slave, then this bit will be of high level. + */ + uint32_t slave_addressed:1; + uint32_t reserved_6:2; + /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0; + * This field represents the amount of data needed to be sent. + */ + uint32_t rxfifo_cnt:6; + /** stretch_cause : RO; bitpos: [15:14]; default: 3; + * The cause of stretching SCL low in slave mode. 0: stretching SCL low at the + * beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty + * in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. + */ + uint32_t stretch_cause:2; + uint32_t reserved_16:2; + /** txfifo_cnt : RO; bitpos: [23:18]; default: 0; + * This field stores the amount of received data in RAM. + */ + uint32_t txfifo_cnt:6; + /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * This field indicates the states of the I2C module state machine. + * 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: + * Wait ACK + */ + uint32_t scl_main_state_last:3; + uint32_t reserved_27:1; + /** scl_state_last : RO; bitpos: [30:28]; default: 0; + * This field indicates the states of the state machine used to produce SCL. + * 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop + */ + uint32_t scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} i2c_sr_reg_t; + +/** Type of fifo_st register + * FIFO status register. + */ +typedef union { + struct { + /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0; + * This is the offset address of the APB reading from rxfifo + */ + uint32_t rxfifo_raddr:5; + /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0; + * This is the offset address of i2c module receiving data and writing to rxfifo. + */ + uint32_t rxfifo_waddr:5; + /** txfifo_raddr : RO; bitpos: [14:10]; default: 0; + * This is the offset address of i2c module reading from txfifo. + */ + uint32_t txfifo_raddr:5; + /** txfifo_waddr : RO; bitpos: [19:15]; default: 0; + * This is the offset address of APB bus writing to txfifo. + */ + uint32_t txfifo_waddr:5; + uint32_t reserved_20:2; + /** slave_rw_point : RO; bitpos: [29:22]; default: 0; + * The received data in I2C slave mode. + */ + uint32_t slave_rw_point:8; + uint32_t reserved_30:2; + }; + uint32_t val; +} i2c_fifo_st_reg_t; + +/** Type of data register + * Rx FIFO read data. + */ +typedef union { + struct { + /** fifo_rdata : RO; bitpos: [7:0]; default: 0; + * The value of rx FIFO read data. + */ + uint32_t fifo_rdata:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} i2c_data_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_raw:1; + /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_raw:1; + /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_raw:1; + /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_raw:1; + /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_raw:1; + /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_raw:1; + /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_raw:1; + /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_raw:1; + /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_raw:1; + /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_raw:1; + /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_raw:1; + /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_raw:1; + /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_raw:1; + /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_raw:1; + /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_raw:1; + /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_raw:1; + /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0; + * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_raw:1; + /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0; + * The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_raw:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} i2c_int_raw_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_clr:1; + /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_clr:1; + /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_clr:1; + /** end_detect_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_clr:1; + /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_clr:1; + /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_clr:1; + /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_clr:1; + /** trans_complete_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_clr:1; + /** time_out_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_clr:1; + /** trans_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_clr:1; + /** nack_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_clr:1; + /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_clr:1; + /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_clr:1; + /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_clr:1; + /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_clr:1; + /** det_start_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_clr:1; + /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_clr:1; + /** general_call_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} i2c_int_clr_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_ena:1; + /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_ena:1; + /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_ena:1; + /** end_detect_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_ena:1; + /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_ena:1; + /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_ena:1; + /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_ena:1; + /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_ena:1; + /** time_out_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_ena:1; + /** trans_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_ena:1; + /** nack_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_ena:1; + /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_ena:1; + /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_ena:1; + /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_ena:1; + /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_ena:1; + /** det_start_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_ena:1; + /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_ena:1; + /** general_call_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_ena:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} i2c_int_ena_reg_t; + +/** Type of int_status register + * Status of captured I2C communication events + */ +typedef union { + struct { + /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + */ + uint32_t rxfifo_wm_int_st:1; + /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + */ + uint32_t txfifo_wm_int_st:1; + /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + */ + uint32_t rxfifo_ovf_int_st:1; + /** end_detect_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t end_detect_int_st:1; + /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + */ + uint32_t byte_trans_done_int_st:1; + /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + */ + uint32_t arbitration_lost_int_st:1; + /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t mst_txfifo_udf_int_st:1; + /** trans_complete_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + */ + uint32_t trans_complete_int_st:1; + /** time_out_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + */ + uint32_t time_out_int_st:1; + /** trans_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + */ + uint32_t trans_start_int_st:1; + /** nack_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t nack_int_st:1; + /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + */ + uint32_t txfifo_ovf_int_st:1; + /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + */ + uint32_t rxfifo_udf_int_st:1; + /** scl_st_to_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + */ + uint32_t scl_st_to_int_st:1; + /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + */ + uint32_t scl_main_st_to_int_st:1; + /** det_start_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for I2C_DET_START_INT interrupt. + */ + uint32_t det_start_int_st:1; + /** slave_stretch_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + */ + uint32_t slave_stretch_int_st:1; + /** general_call_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + */ + uint32_t general_call_int_st:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} i2c_int_status_reg_t; + + +/** Group: Command registers */ +/** Type of comd0 register + * I2C command register 0 + */ +typedef union { + struct { + /** command0 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 0. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command0:14; + uint32_t reserved_14:17; + /** command0_done : R/W/SS; bitpos: [31]; default: 0; + * When command 0 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command0_done:1; + }; + uint32_t val; +} i2c_comd0_reg_t; + +/** Type of comd1 register + * I2C command register 1 + */ +typedef union { + struct { + /** command1 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 1. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command1:14; + uint32_t reserved_14:17; + /** command1_done : R/W/SS; bitpos: [31]; default: 0; + * When command 1 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command1_done:1; + }; + uint32_t val; +} i2c_comd1_reg_t; + +/** Type of comd2 register + * I2C command register 2 + */ +typedef union { + struct { + /** command2 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 2. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command2:14; + uint32_t reserved_14:17; + /** command2_done : R/W/SS; bitpos: [31]; default: 0; + * When command 2 is done in I2C Master mode, this bit changes to high + * Level. + */ + uint32_t command2_done:1; + }; + uint32_t val; +} i2c_comd2_reg_t; + +/** Type of comd3 register + * I2C command register 3 + */ +typedef union { + struct { + /** command3 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 3. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command3:14; + uint32_t reserved_14:17; + /** command3_done : R/W/SS; bitpos: [31]; default: 0; + * When command 3 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command3_done:1; + }; + uint32_t val; +} i2c_comd3_reg_t; + +/** Type of comd4 register + * I2C command register 4 + */ +typedef union { + struct { + /** command4 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 4. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command4:14; + uint32_t reserved_14:17; + /** command4_done : R/W/SS; bitpos: [31]; default: 0; + * When command 4 is done in I2C Master mode, this bit changes to high + * level. + */ + uint32_t command4_done:1; + }; + uint32_t val; +} i2c_comd4_reg_t; + +/** Type of comd5 register + * I2C command register 5 + */ +typedef union { + struct { + /** command5 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 5. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command5:14; + uint32_t reserved_14:17; + /** command5_done : R/W/SS; bitpos: [31]; default: 0; + * When command 5 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command5_done:1; + }; + uint32_t val; +} i2c_comd5_reg_t; + +/** Type of comd6 register + * I2C command register 6 + */ +typedef union { + struct { + /** command6 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 6. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command6:14; + uint32_t reserved_14:17; + /** command6_done : R/W/SS; bitpos: [31]; default: 0; + * When command 6 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command6_done:1; + }; + uint32_t val; +} i2c_comd6_reg_t; + +/** Type of comd7 register + * I2C command register 7 + */ +typedef union { + struct { + /** command7 : R/W; bitpos: [13:0]; default: 0; + * This is the content of command 7. It consists of three parts: + * op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END. + * Byte_num represents the number of bytes that need to be sent or received. + * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd + * structure for more + * Information. + */ + uint32_t command7:14; + uint32_t reserved_14:17; + /** command7_done : R/W/SS; bitpos: [31]; default: 0; + * When command 7 is done in I2C Master mode, this bit changes to high level. + */ + uint32_t command7_done:1; + }; + uint32_t val; +} i2c_comd7_reg_t; + + +/** Group: Version register */ +/** Type of date register + * Version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [31:0]; default: 537330177; + * This is the the version register. + */ + uint32_t date:32; + }; + uint32_t val; +} i2c_date_reg_t; + + +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : RO; bitpos: [31:0]; default: 0; + * This is the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : RO; bitpos: [31:0]; default: 0; + * This is the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + +typedef struct { + volatile i2c_scl_low_period_reg_t scl_low_period; + volatile i2c_ctr_reg_t ctr; + volatile i2c_sr_reg_t sr; + volatile i2c_to_reg_t to; + volatile i2c_slave_addr_reg_t slave_addr; + volatile i2c_fifo_st_reg_t fifo_st; + volatile i2c_fifo_conf_reg_t fifo_conf; + volatile i2c_data_reg_t data; + volatile i2c_int_raw_reg_t int_raw; + volatile i2c_int_clr_reg_t int_clr; + volatile i2c_int_ena_reg_t int_ena; + volatile i2c_int_status_reg_t int_status; + volatile i2c_sda_hold_reg_t sda_hold; + volatile i2c_sda_sample_reg_t sda_sample; + volatile i2c_scl_high_period_reg_t scl_high_period; + uint32_t reserved_03c; + volatile i2c_scl_start_hold_reg_t scl_start_hold; + volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup; + volatile i2c_scl_stop_hold_reg_t scl_stop_hold; + volatile i2c_scl_stop_setup_reg_t scl_stop_setup; + volatile i2c_filter_cfg_reg_t filter_cfg; + volatile i2c_clk_conf_reg_t clk_conf; + volatile i2c_comd0_reg_t comd0; + volatile i2c_comd1_reg_t comd1; + volatile i2c_comd2_reg_t comd2; + volatile i2c_comd3_reg_t comd3; + volatile i2c_comd4_reg_t comd4; + volatile i2c_comd5_reg_t comd5; + volatile i2c_comd6_reg_t comd6; + volatile i2c_comd7_reg_t comd7; + volatile i2c_scl_st_time_out_reg_t scl_st_time_out; + volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; + volatile i2c_scl_sp_conf_reg_t scl_sp_conf; + volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf; + uint32_t reserved_088[28]; + volatile i2c_date_reg_t date; + uint32_t reserved_0fc; + volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr; + uint32_t reserved_104[31]; + volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr; } i2c_dev_t; + extern i2c_dev_t I2C0; extern i2c_dev_t I2C1; + +#ifndef __cplusplus +_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_I2C_STRUCT_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h index 889d2dd5ed..3c065af259 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_reg.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_reg.h @@ -1,686 +1,873 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RTC_I2C_REG_H_ -#define _SOC_RTC_I2C_REG_H_ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0) -/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 0.*/ -#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S)) -#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_LOW_PERIOD_S 0 +/** RTC_I2C_SCL_LOW_REG register + * configure low scl period + */ +#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_BASE + 0x0) +/** RTC_I2C_SCL_LOW_PERIOD_REG : R/W; bitpos: [19:0]; default: 256; + * time period that scl =0 + */ +#define RTC_I2C_SCL_LOW_PERIOD_REG 0x000FFFFFU +#define RTC_I2C_SCL_LOW_PERIOD_REG_M (RTC_I2C_SCL_LOW_PERIOD_REG_V << RTC_I2C_SCL_LOW_PERIOD_REG_S) +#define RTC_I2C_SCL_LOW_PERIOD_REG_V 0x000FFFFFU +#define RTC_I2C_SCL_LOW_PERIOD_REG_S 0 -#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4) -/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: rtc i2c reg clk gating.*/ -#define RTC_I2C_CLK_EN (BIT(31)) -#define RTC_I2C_CLK_EN_M (BIT(31)) -#define RTC_I2C_CLK_EN_V 0x1 -#define RTC_I2C_CLK_EN_S 31 -/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: rtc i2c sw reset.*/ -#define RTC_I2C_RESET (BIT(30)) -#define RTC_I2C_RESET_M (BIT(30)) -#define RTC_I2C_RESET_V 0x1 -#define RTC_I2C_RESET_S 30 -/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) -#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 -#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 -/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: receive lsb first.*/ -#define RTC_I2C_RX_LSB_FIRST (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) -#define RTC_I2C_RX_LSB_FIRST_V 0x1 -#define RTC_I2C_RX_LSB_FIRST_S 5 -/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: transit lsb first.*/ -#define RTC_I2C_TX_LSB_FIRST (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) -#define RTC_I2C_TX_LSB_FIRST_V 0x1 -#define RTC_I2C_TX_LSB_FIRST_S 4 -/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: force start.*/ -#define RTC_I2C_TRANS_START (BIT(3)) -#define RTC_I2C_TRANS_START_M (BIT(3)) -#define RTC_I2C_TRANS_START_V 0x1 -#define RTC_I2C_TRANS_START_S 3 -/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: 1=master, 0=slave.*/ -#define RTC_I2C_MS_MODE (BIT(2)) -#define RTC_I2C_MS_MODE_M (BIT(2)) -#define RTC_I2C_MS_MODE_V 0x1 -#define RTC_I2C_MS_MODE_S 2 -/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: 1=push pull, 0=open drain.*/ -#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) -#define RTC_I2C_SCL_FORCE_OUT_V 0x1 -#define RTC_I2C_SCL_FORCE_OUT_S 1 -/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: 1=push pull, 0=open drain.*/ +/** RTC_I2C_CTRL_REG register + * configure i2c ctrl + */ +#define RTC_I2C_CTRL_REG (DR_REG_RTC_BASE + 0x4) +/** RTC_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; + * 1=push pull,0=open drain + */ #define RTC_I2C_SDA_FORCE_OUT (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) -#define RTC_I2C_SDA_FORCE_OUT_V 0x1 +#define RTC_I2C_SDA_FORCE_OUT_M (RTC_I2C_SDA_FORCE_OUT_V << RTC_I2C_SDA_FORCE_OUT_S) +#define RTC_I2C_SDA_FORCE_OUT_V 0x00000001U #define RTC_I2C_SDA_FORCE_OUT_S 0 +/** RTC_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; + * 1=push pull,0=open drain + */ +#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_M (RTC_I2C_SCL_FORCE_OUT_V << RTC_I2C_SCL_FORCE_OUT_S) +#define RTC_I2C_SCL_FORCE_OUT_V 0x00000001U +#define RTC_I2C_SCL_FORCE_OUT_S 1 +/** RTC_I2C_MS_MODE : R/W; bitpos: [2]; default: 0; + * 1=master,0=slave + */ +#define RTC_I2C_MS_MODE (BIT(2)) +#define RTC_I2C_MS_MODE_M (RTC_I2C_MS_MODE_V << RTC_I2C_MS_MODE_S) +#define RTC_I2C_MS_MODE_V 0x00000001U +#define RTC_I2C_MS_MODE_S 2 +/** RTC_I2C_TRANS_START : R/W; bitpos: [3]; default: 0; + * force start + */ +#define RTC_I2C_TRANS_START (BIT(3)) +#define RTC_I2C_TRANS_START_M (RTC_I2C_TRANS_START_V << RTC_I2C_TRANS_START_S) +#define RTC_I2C_TRANS_START_V 0x00000001U +#define RTC_I2C_TRANS_START_S 3 +/** RTC_I2C_TX_LSB_FIRST : R/W; bitpos: [4]; default: 0; + * transit lsb first + */ +#define RTC_I2C_TX_LSB_FIRST (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_M (RTC_I2C_TX_LSB_FIRST_V << RTC_I2C_TX_LSB_FIRST_S) +#define RTC_I2C_TX_LSB_FIRST_V 0x00000001U +#define RTC_I2C_TX_LSB_FIRST_S 4 +/** RTC_I2C_RX_LSB_FIRST : R/W; bitpos: [5]; default: 0; + * receive lsb first + */ +#define RTC_I2C_RX_LSB_FIRST (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_M (RTC_I2C_RX_LSB_FIRST_V << RTC_I2C_RX_LSB_FIRST_S) +#define RTC_I2C_RX_LSB_FIRST_V 0x00000001U +#define RTC_I2C_RX_LSB_FIRST_S 5 +/** RTC_I2C_I2C_CTRL_CLK_GATE_EN : R/W; bitpos: [29]; default: 0; + * configure i2c ctrl clk enable + */ +#define RTC_I2C_I2C_CTRL_CLK_GATE_EN (BIT(29)) +#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_M (RTC_I2C_I2C_CTRL_CLK_GATE_EN_V << RTC_I2C_I2C_CTRL_CLK_GATE_EN_S) +#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_V 0x00000001U +#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_S 29 +/** RTC_I2C_I2C_RESET : R/W; bitpos: [30]; default: 0; + * rtc i2c sw reset + */ +#define RTC_I2C_I2C_RESET (BIT(30)) +#define RTC_I2C_I2C_RESET_M (RTC_I2C_I2C_RESET_V << RTC_I2C_I2C_RESET_S) +#define RTC_I2C_I2C_RESET_V 0x00000001U +#define RTC_I2C_I2C_RESET_S 30 +/** RTC_I2C_I2CCLK_EN : R/W; bitpos: [31]; default: 0; + * rtc i2c reg clk gating + */ +#define RTC_I2C_I2CCLK_EN (BIT(31)) +#define RTC_I2C_I2CCLK_EN_M (RTC_I2C_I2CCLK_EN_V << RTC_I2C_I2CCLK_EN_S) +#define RTC_I2C_I2CCLK_EN_V 0x00000001U +#define RTC_I2C_I2CCLK_EN_S 31 -#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8) -/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ -/*description: scl last status.*/ -#define RTC_I2C_SCL_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S)) -#define RTC_I2C_SCL_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_STATE_LAST_S 28 -/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ -/*description: i2c last main status.*/ -#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S)) -#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 -/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ -/*description: shifter content.*/ -#define RTC_I2C_SHIFT 0x000000FF -#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S)) -#define RTC_I2C_SHIFT_V 0xFF -#define RTC_I2C_SHIFT_S 16 -/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ -/*description: which operation is working.*/ -#define RTC_I2C_OP_CNT 0x00000003 -#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S)) -#define RTC_I2C_OP_CNT_V 0x3 -#define RTC_I2C_OP_CNT_S 6 -/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: One byte transit done.*/ -#define RTC_I2C_BYTE_TRANS (BIT(5)) -#define RTC_I2C_BYTE_TRANS_M (BIT(5)) -#define RTC_I2C_BYTE_TRANS_V 0x1 -#define RTC_I2C_BYTE_TRANS_S 5 -/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: slave reg sub address.*/ -#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) -#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 -#define RTC_I2C_SLAVE_ADDRESSED_S 4 -/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: bus is busy.*/ -#define RTC_I2C_BUS_BUSY (BIT(3)) -#define RTC_I2C_BUS_BUSY_M (BIT(3)) -#define RTC_I2C_BUS_BUSY_V 0x1 -#define RTC_I2C_BUS_BUSY_S 3 -/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: arbitration is lost.*/ -#define RTC_I2C_ARB_LOST (BIT(2)) -#define RTC_I2C_ARB_LOST_M (BIT(2)) -#define RTC_I2C_ARB_LOST_V 0x1 -#define RTC_I2C_ARB_LOST_S 2 -/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: slave read or write.*/ -#define RTC_I2C_SLAVE_RW (BIT(1)) -#define RTC_I2C_SLAVE_RW_M (BIT(1)) -#define RTC_I2C_SLAVE_RW_V 0x1 -#define RTC_I2C_SLAVE_RW_S 1 -/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: ack response.*/ +/** RTC_I2C_STATUS_REG register + * get i2c status + */ +#define RTC_I2C_STATUS_REG (DR_REG_RTC_BASE + 0x8) +/** RTC_I2C_ACK_REC : RO; bitpos: [0]; default: 0; + * ack response + */ #define RTC_I2C_ACK_REC (BIT(0)) -#define RTC_I2C_ACK_REC_M (BIT(0)) -#define RTC_I2C_ACK_REC_V 0x1 +#define RTC_I2C_ACK_REC_M (RTC_I2C_ACK_REC_V << RTC_I2C_ACK_REC_S) +#define RTC_I2C_ACK_REC_V 0x00000001U #define RTC_I2C_ACK_REC_S 0 +/** RTC_I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; + * slave read or write + */ +#define RTC_I2C_SLAVE_RW (BIT(1)) +#define RTC_I2C_SLAVE_RW_M (RTC_I2C_SLAVE_RW_V << RTC_I2C_SLAVE_RW_S) +#define RTC_I2C_SLAVE_RW_V 0x00000001U +#define RTC_I2C_SLAVE_RW_S 1 +/** RTC_I2C_ARB_LOST : RO; bitpos: [2]; default: 0; + * arbitration is lost + */ +#define RTC_I2C_ARB_LOST (BIT(2)) +#define RTC_I2C_ARB_LOST_M (RTC_I2C_ARB_LOST_V << RTC_I2C_ARB_LOST_S) +#define RTC_I2C_ARB_LOST_V 0x00000001U +#define RTC_I2C_ARB_LOST_S 2 +/** RTC_I2C_BUS_BUSY : RO; bitpos: [3]; default: 0; + * bus is busy + */ +#define RTC_I2C_BUS_BUSY (BIT(3)) +#define RTC_I2C_BUS_BUSY_M (RTC_I2C_BUS_BUSY_V << RTC_I2C_BUS_BUSY_S) +#define RTC_I2C_BUS_BUSY_V 0x00000001U +#define RTC_I2C_BUS_BUSY_S 3 +/** RTC_I2C_SLAVE_ADDRESSED : RO; bitpos: [4]; default: 0; + * slave reg sub address + */ +#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_M (RTC_I2C_SLAVE_ADDRESSED_V << RTC_I2C_SLAVE_ADDRESSED_S) +#define RTC_I2C_SLAVE_ADDRESSED_V 0x00000001U +#define RTC_I2C_SLAVE_ADDRESSED_S 4 +/** RTC_I2C_BYTE_TRANS : RO; bitpos: [5]; default: 0; + * One byte transit done + */ +#define RTC_I2C_BYTE_TRANS (BIT(5)) +#define RTC_I2C_BYTE_TRANS_M (RTC_I2C_BYTE_TRANS_V << RTC_I2C_BYTE_TRANS_S) +#define RTC_I2C_BYTE_TRANS_V 0x00000001U +#define RTC_I2C_BYTE_TRANS_S 5 +/** RTC_I2C_OP_CNT : RO; bitpos: [7:6]; default: 0; + * which operation is working + */ +#define RTC_I2C_OP_CNT 0x00000003U +#define RTC_I2C_OP_CNT_M (RTC_I2C_OP_CNT_V << RTC_I2C_OP_CNT_S) +#define RTC_I2C_OP_CNT_V 0x00000003U +#define RTC_I2C_OP_CNT_S 6 +/** RTC_I2C_SHIFT_REG : RO; bitpos: [23:16]; default: 0; + * shifter content + */ +#define RTC_I2C_SHIFT_REG 0x000000FFU +#define RTC_I2C_SHIFT_REG_M (RTC_I2C_SHIFT_REG_V << RTC_I2C_SHIFT_REG_S) +#define RTC_I2C_SHIFT_REG_V 0x000000FFU +#define RTC_I2C_SHIFT_REG_S 16 +/** RTC_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; + * i2c last main status + */ +#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define RTC_I2C_SCL_MAIN_STATE_LAST_M (RTC_I2C_SCL_MAIN_STATE_LAST_V << RTC_I2C_SCL_MAIN_STATE_LAST_S) +#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 +/** RTC_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; + * scl last status + */ +#define RTC_I2C_SCL_STATE_LAST 0x00000007U +#define RTC_I2C_SCL_STATE_LAST_M (RTC_I2C_SCL_STATE_LAST_V << RTC_I2C_SCL_STATE_LAST_S) +#define RTC_I2C_SCL_STATE_LAST_V 0x00000007U +#define RTC_I2C_SCL_STATE_LAST_S 28 -#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0xC) -/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ -/*description: time out threshold.*/ -#define RTC_I2C_TIMEOUT 0x000FFFFF -#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S)) -#define RTC_I2C_TIMEOUT_V 0xFFFFF -#define RTC_I2C_TIMEOUT_S 0 +/** RTC_I2C_TO_REG register + * configure time out + */ +#define RTC_I2C_TO_REG (DR_REG_RTC_BASE + 0xc) +/** RTC_I2C_TIME_OUT_REG : R/W; bitpos: [19:0]; default: 65536; + * time out threshold + */ +#define RTC_I2C_TIME_OUT_REG 0x000FFFFFU +#define RTC_I2C_TIME_OUT_REG_M (RTC_I2C_TIME_OUT_REG_V << RTC_I2C_TIME_OUT_REG_S) +#define RTC_I2C_TIME_OUT_REG_V 0x000FFFFFU +#define RTC_I2C_TIME_OUT_REG_S 0 -#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10) -/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: i2c 10bit mode enable.*/ -#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) -#define RTC_I2C_ADDR_10BIT_EN_V 0x1 -#define RTC_I2C_ADDR_10BIT_EN_S 31 -/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ -/*description: slave address.*/ -#define RTC_I2C_SLAVE_ADDR 0x00007FFF -#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S)) -#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +/** RTC_I2C_SLAVE_ADDR_REG register + * configure slave id + */ +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_BASE + 0x10) +/** RTC_I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; + * slave address + */ +#define RTC_I2C_SLAVE_ADDR 0x00007FFFU +#define RTC_I2C_SLAVE_ADDR_M (RTC_I2C_SLAVE_ADDR_V << RTC_I2C_SLAVE_ADDR_S) +#define RTC_I2C_SLAVE_ADDR_V 0x00007FFFU #define RTC_I2C_SLAVE_ADDR_S 0 +/** RTC_I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; + * i2c 10bit mode enable + */ +#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_M (RTC_I2C_ADDR_10BIT_EN_V << RTC_I2C_ADDR_10BIT_EN_S) +#define RTC_I2C_ADDR_10BIT_EN_V 0x00000001U +#define RTC_I2C_ADDR_10BIT_EN_S 31 -#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14) -/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ -/*description: time period that scl = 1.*/ -#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S)) -#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF -#define RTC_I2C_SCL_HIGH_PERIOD_S 0 +/** RTC_I2C_SCL_HIGH_REG register + * configure high scl period + */ +#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_BASE + 0x14) +/** RTC_I2C_SCL_HIGH_PERIOD_REG : R/W; bitpos: [19:0]; default: 256; + * time period that scl = 1 + */ +#define RTC_I2C_SCL_HIGH_PERIOD_REG 0x000FFFFFU +#define RTC_I2C_SCL_HIGH_PERIOD_REG_M (RTC_I2C_SCL_HIGH_PERIOD_REG_V << RTC_I2C_SCL_HIGH_PERIOD_REG_S) +#define RTC_I2C_SCL_HIGH_PERIOD_REG_V 0x000FFFFFU +#define RTC_I2C_SCL_HIGH_PERIOD_REG_S 0 -#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18) -/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ -/*description: time period for SDA to toggle after SCL goes low.*/ -#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF -#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S)) -#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF +/** RTC_I2C_SDA_DUTY_REG register + * configure sda duty + */ +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_BASE + 0x18) +/** RTC_I2C_SDA_DUTY_NUM : R/W; bitpos: [19:0]; default: 16; + * time period for SDA to toggle after SCL goes low + */ +#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFFU +#define RTC_I2C_SDA_DUTY_NUM_M (RTC_I2C_SDA_DUTY_NUM_V << RTC_I2C_SDA_DUTY_NUM_S) +#define RTC_I2C_SDA_DUTY_NUM_V 0x000FFFFFU #define RTC_I2C_SDA_DUTY_NUM_S 0 -#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1C) -/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to toggle after I2C start is triggered.*/ -#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S)) -#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +/** RTC_I2C_SCL_START_PERIOD_REG register + * configure scl start period + */ +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_BASE + 0x1c) +/** RTC_I2C_SCL_START_PERIOD : R/W; bitpos: [19:0]; default: 8; + * time period for SCL to toggle after I2C start is triggered + */ +#define RTC_I2C_SCL_START_PERIOD 0x000FFFFFU +#define RTC_I2C_SCL_START_PERIOD_M (RTC_I2C_SCL_START_PERIOD_V << RTC_I2C_SCL_START_PERIOD_S) +#define RTC_I2C_SCL_START_PERIOD_V 0x000FFFFFU #define RTC_I2C_SCL_START_PERIOD_S 0 -#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20) -/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ -/*description: time period for SCL to stop after I2C end is triggered.*/ -#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF -#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S)) -#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +/** RTC_I2C_SCL_STOP_PERIOD_REG register + * configure scl stop period + */ +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_BASE + 0x20) +/** RTC_I2C_SCL_STOP_PERIOD : R/W; bitpos: [19:0]; default: 8; + * time period for SCL to stop after I2C end is triggered + */ +#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFFU +#define RTC_I2C_SCL_STOP_PERIOD_M (RTC_I2C_SCL_STOP_PERIOD_V << RTC_I2C_SCL_STOP_PERIOD_S) +#define RTC_I2C_SCL_STOP_PERIOD_V 0x000FFFFFU #define RTC_I2C_SCL_STOP_PERIOD_S 0 -#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24) -/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: clear detect start interrupt.*/ -#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 -#define RTC_I2C_DETECT_START_INT_CLR_S 8 -/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: clear transit load data complete interrupt.*/ -#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_TX_DATA_INT_CLR_S 7 -/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: clear receive data interrupt.*/ -#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 -#define RTC_I2C_RX_DATA_INT_CLR_S 6 -/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: clear ack error interrupt.*/ -#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 -#define RTC_I2C_ACK_ERR_INT_CLR_S 5 -/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: clear time out interrupt.*/ -#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 -#define RTC_I2C_TIMEOUT_INT_CLR_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: clear transit complete interrupt.*/ -#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: clear master transit complete interrupt.*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: clear arbitration lost interrupt.*/ -#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: clear slave transit complete interrupt.*/ +/** RTC_I2C_INT_CLR_REG register + * interrupt clear register + */ +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_BASE + 0x24) +/** RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO; bitpos: [0]; default: 0; + * clear slave transit complete interrupt + */ #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V << RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x00000001U #define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 +/** RTC_I2C_ARBITRATION_LOST_INT_CLR : WO; bitpos: [1]; default: 0; + * clear arbitration lost interrupt + */ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (RTC_I2C_ARBITRATION_LOST_INT_CLR_V << RTC_I2C_ARBITRATION_LOST_INT_CLR_S) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 +/** RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO; bitpos: [2]; default: 0; + * clear master transit complete interrupt + */ +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V << RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x00000001U +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 +/** RTC_I2C_TRANS_COMPLETE_INT_CLR : WO; bitpos: [3]; default: 0; + * clear transit complete interrupt + */ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (RTC_I2C_TRANS_COMPLETE_INT_CLR_V << RTC_I2C_TRANS_COMPLETE_INT_CLR_S) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 +/** RTC_I2C_TIME_OUT_INT_CLR : WO; bitpos: [4]; default: 0; + * clear time out interrupt + */ +#define RTC_I2C_TIME_OUT_INT_CLR (BIT(4)) +#define RTC_I2C_TIME_OUT_INT_CLR_M (RTC_I2C_TIME_OUT_INT_CLR_V << RTC_I2C_TIME_OUT_INT_CLR_S) +#define RTC_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define RTC_I2C_TIME_OUT_INT_CLR_S 4 +/** RTC_I2C_ACK_ERR_INT_CLR : WO; bitpos: [5]; default: 0; + * clear ack error interrupt + */ +#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_M (RTC_I2C_ACK_ERR_INT_CLR_V << RTC_I2C_ACK_ERR_INT_CLR_S) +#define RTC_I2C_ACK_ERR_INT_CLR_V 0x00000001U +#define RTC_I2C_ACK_ERR_INT_CLR_S 5 +/** RTC_I2C_RX_DATA_INT_CLR : WO; bitpos: [6]; default: 0; + * clear receive data interrupt + */ +#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_M (RTC_I2C_RX_DATA_INT_CLR_V << RTC_I2C_RX_DATA_INT_CLR_S) +#define RTC_I2C_RX_DATA_INT_CLR_V 0x00000001U +#define RTC_I2C_RX_DATA_INT_CLR_S 6 +/** RTC_I2C_TX_DATA_INT_CLR : WO; bitpos: [7]; default: 0; + * clear transit load data complete interrupt + */ +#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_M (RTC_I2C_TX_DATA_INT_CLR_V << RTC_I2C_TX_DATA_INT_CLR_S) +#define RTC_I2C_TX_DATA_INT_CLR_V 0x00000001U +#define RTC_I2C_TX_DATA_INT_CLR_S 7 +/** RTC_I2C_DETECT_START_INT_CLR : WO; bitpos: [8]; default: 0; + * clear detect start interrupt + */ +#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_M (RTC_I2C_DETECT_START_INT_CLR_V << RTC_I2C_DETECT_START_INT_CLR_S) +#define RTC_I2C_DETECT_START_INT_CLR_V 0x00000001U +#define RTC_I2C_DETECT_START_INT_CLR_S 8 -#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28) -/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt raw.*/ -#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 -#define RTC_I2C_DETECT_START_INT_RAW_S 8 -/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt raw.*/ -#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_TX_DATA_INT_RAW_S 7 -/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt raw.*/ -#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 -#define RTC_I2C_RX_DATA_INT_RAW_S 6 -/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt raw.*/ -#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 -#define RTC_I2C_ACK_ERR_INT_RAW_S 5 -/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt raw.*/ -#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 -#define RTC_I2C_TIMEOUT_INT_RAW_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt raw.*/ -#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt raw.*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt raw.*/ -#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt raw.*/ +/** RTC_I2C_INT_RAW_REG register + * interrupt raw register + */ +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_BASE + 0x28) +/** RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO; bitpos: [0]; default: 0; + * slave transit complete interrupt raw + */ #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V << RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x00000001U #define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 +/** RTC_I2C_ARBITRATION_LOST_INT_RAW : RO; bitpos: [1]; default: 0; + * arbitration lost interrupt raw + */ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (RTC_I2C_ARBITRATION_LOST_INT_RAW_V << RTC_I2C_ARBITRATION_LOST_INT_RAW_S) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 +/** RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO; bitpos: [2]; default: 0; + * master transit complete interrupt raw + */ +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V << RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x00000001U +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 +/** RTC_I2C_TRANS_COMPLETE_INT_RAW : RO; bitpos: [3]; default: 0; + * transit complete interrupt raw + */ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (RTC_I2C_TRANS_COMPLETE_INT_RAW_V << RTC_I2C_TRANS_COMPLETE_INT_RAW_S) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 +/** RTC_I2C_TIME_OUT_INT_RAW : RO; bitpos: [4]; default: 0; + * time out interrupt raw + */ +#define RTC_I2C_TIME_OUT_INT_RAW (BIT(4)) +#define RTC_I2C_TIME_OUT_INT_RAW_M (RTC_I2C_TIME_OUT_INT_RAW_V << RTC_I2C_TIME_OUT_INT_RAW_S) +#define RTC_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define RTC_I2C_TIME_OUT_INT_RAW_S 4 +/** RTC_I2C_ACK_ERR_INT_RAW : RO; bitpos: [5]; default: 0; + * ack error interrupt raw + */ +#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_M (RTC_I2C_ACK_ERR_INT_RAW_V << RTC_I2C_ACK_ERR_INT_RAW_S) +#define RTC_I2C_ACK_ERR_INT_RAW_V 0x00000001U +#define RTC_I2C_ACK_ERR_INT_RAW_S 5 +/** RTC_I2C_RX_DATA_INT_RAW : RO; bitpos: [6]; default: 0; + * receive data interrupt raw + */ +#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_M (RTC_I2C_RX_DATA_INT_RAW_V << RTC_I2C_RX_DATA_INT_RAW_S) +#define RTC_I2C_RX_DATA_INT_RAW_V 0x00000001U +#define RTC_I2C_RX_DATA_INT_RAW_S 6 +/** RTC_I2C_TX_DATA_INT_RAW : RO; bitpos: [7]; default: 0; + * transit data interrupt raw + */ +#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_M (RTC_I2C_TX_DATA_INT_RAW_V << RTC_I2C_TX_DATA_INT_RAW_S) +#define RTC_I2C_TX_DATA_INT_RAW_V 0x00000001U +#define RTC_I2C_TX_DATA_INT_RAW_S 7 +/** RTC_I2C_DETECT_START_INT_RAW : RO; bitpos: [8]; default: 0; + * detect start interrupt raw + */ +#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_M (RTC_I2C_DETECT_START_INT_RAW_V << RTC_I2C_DETECT_START_INT_RAW_S) +#define RTC_I2C_DETECT_START_INT_RAW_V 0x00000001U +#define RTC_I2C_DETECT_START_INT_RAW_S 8 -#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2C) -/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: detect start interrupt state.*/ -#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ST_V 0x1 -#define RTC_I2C_DETECT_START_INT_ST_S 8 -/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: transit data interrupt state.*/ -#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ST_V 0x1 -#define RTC_I2C_TX_DATA_INT_ST_S 7 -/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: receive data interrupt state.*/ -#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ST_V 0x1 -#define RTC_I2C_RX_DATA_INT_ST_S 6 -/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: ack error interrupt state.*/ -#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ST_S 5 -/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: time out interrupt state.*/ -#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ST_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: transit complete interrupt state.*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: master transit complete interrupt state.*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: arbitration lost interrupt state.*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: slave transit complete interrupt state.*/ +/** RTC_I2C_INT_ST_REG register + * interrupt state register + */ +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_BASE + 0x2c) +/** RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO; bitpos: [0]; default: 0; + * slave transit complete interrupt state + */ #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x00000001U #define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 +/** RTC_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [1]; default: 0; + * arbitration lost interrupt state + */ +#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (RTC_I2C_ARBITRATION_LOST_INT_ST_V << RTC_I2C_ARBITRATION_LOST_INT_ST_S) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 +/** RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO; bitpos: [2]; default: 0; + * master transit complete interrupt state + */ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (RTC_I2C_MASTER_TRAN_COMP_INT_ST_V << RTC_I2C_MASTER_TRAN_COMP_INT_ST_S) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x00000001U +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 +/** RTC_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [3]; default: 0; + * transit complete interrupt state + */ +#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (RTC_I2C_TRANS_COMPLETE_INT_ST_V << RTC_I2C_TRANS_COMPLETE_INT_ST_S) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 +/** RTC_I2C_TIME_OUT_INT_ST : RO; bitpos: [4]; default: 0; + * time out interrupt state + */ +#define RTC_I2C_TIME_OUT_INT_ST (BIT(4)) +#define RTC_I2C_TIME_OUT_INT_ST_M (RTC_I2C_TIME_OUT_INT_ST_V << RTC_I2C_TIME_OUT_INT_ST_S) +#define RTC_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define RTC_I2C_TIME_OUT_INT_ST_S 4 +/** RTC_I2C_ACK_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * ack error interrupt state + */ +#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_M (RTC_I2C_ACK_ERR_INT_ST_V << RTC_I2C_ACK_ERR_INT_ST_S) +#define RTC_I2C_ACK_ERR_INT_ST_V 0x00000001U +#define RTC_I2C_ACK_ERR_INT_ST_S 5 +/** RTC_I2C_RX_DATA_INT_ST : RO; bitpos: [6]; default: 0; + * receive data interrupt state + */ +#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_M (RTC_I2C_RX_DATA_INT_ST_V << RTC_I2C_RX_DATA_INT_ST_S) +#define RTC_I2C_RX_DATA_INT_ST_V 0x00000001U +#define RTC_I2C_RX_DATA_INT_ST_S 6 +/** RTC_I2C_TX_DATA_INT_ST : RO; bitpos: [7]; default: 0; + * transit data interrupt state + */ +#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_M (RTC_I2C_TX_DATA_INT_ST_V << RTC_I2C_TX_DATA_INT_ST_S) +#define RTC_I2C_TX_DATA_INT_ST_V 0x00000001U +#define RTC_I2C_TX_DATA_INT_ST_S 7 +/** RTC_I2C_DETECT_START_INT_ST : RO; bitpos: [8]; default: 0; + * detect start interrupt state + */ +#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_M (RTC_I2C_DETECT_START_INT_ST_V << RTC_I2C_DETECT_START_INT_ST_S) +#define RTC_I2C_DETECT_START_INT_ST_V 0x00000001U +#define RTC_I2C_DETECT_START_INT_ST_S 8 -#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30) -/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: enable detect start interrupt.*/ -#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) -#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 -#define RTC_I2C_DETECT_START_INT_ENA_S 8 -/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: enable transit data interrupt.*/ -#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) -#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_TX_DATA_INT_ENA_S 7 -/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: enable receive data interrupt.*/ -#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) -#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 -#define RTC_I2C_RX_DATA_INT_ENA_S 6 -/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: enable eack error interrupt.*/ -#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) -#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 -#define RTC_I2C_ACK_ERR_INT_ENA_S 5 -/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: enable time out interrupt.*/ -#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) -#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 -#define RTC_I2C_TIMEOUT_INT_ENA_S 4 -/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: enable transit complete interrupt.*/ -#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 -/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: enable master transit complete interrupt.*/ -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 -#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 -/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: enable arbitration lost interrupt.*/ -#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 -/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: enable slave transit complete interrupt.*/ +/** RTC_I2C_INT_ENA_REG register + * interrupt enable register + */ +#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_BASE + 0x30) +/** RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W; bitpos: [0]; default: 0; + * enable slave transit complete interrupt + */ #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) -#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x00000001U #define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 +/** RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [1]; default: 0; + * enable arbitration lost interrupt + */ +#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (RTC_I2C_ARBITRATION_LOST_INT_ENA_V << RTC_I2C_ARBITRATION_LOST_INT_ENA_S) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 +/** RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W; bitpos: [2]; default: 0; + * enable master transit complete interrupt + */ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V << RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x00000001U +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 +/** RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [3]; default: 0; + * enable transit complete interrupt + */ +#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (RTC_I2C_TRANS_COMPLETE_INT_ENA_V << RTC_I2C_TRANS_COMPLETE_INT_ENA_S) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 +/** RTC_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable time out interrupt + */ +#define RTC_I2C_TIME_OUT_INT_ENA (BIT(4)) +#define RTC_I2C_TIME_OUT_INT_ENA_M (RTC_I2C_TIME_OUT_INT_ENA_V << RTC_I2C_TIME_OUT_INT_ENA_S) +#define RTC_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define RTC_I2C_TIME_OUT_INT_ENA_S 4 +/** RTC_I2C_ACK_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * enable eack error interrupt + */ +#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_M (RTC_I2C_ACK_ERR_INT_ENA_V << RTC_I2C_ACK_ERR_INT_ENA_S) +#define RTC_I2C_ACK_ERR_INT_ENA_V 0x00000001U +#define RTC_I2C_ACK_ERR_INT_ENA_S 5 +/** RTC_I2C_RX_DATA_INT_ENA : R/W; bitpos: [6]; default: 0; + * enable receive data interrupt + */ +#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_M (RTC_I2C_RX_DATA_INT_ENA_V << RTC_I2C_RX_DATA_INT_ENA_S) +#define RTC_I2C_RX_DATA_INT_ENA_V 0x00000001U +#define RTC_I2C_RX_DATA_INT_ENA_S 6 +/** RTC_I2C_TX_DATA_INT_ENA : R/W; bitpos: [7]; default: 0; + * enable transit data interrupt + */ +#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_M (RTC_I2C_TX_DATA_INT_ENA_V << RTC_I2C_TX_DATA_INT_ENA_S) +#define RTC_I2C_TX_DATA_INT_ENA_V 0x00000001U +#define RTC_I2C_TX_DATA_INT_ENA_S 7 +/** RTC_I2C_DETECT_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * enable detect start interrupt + */ +#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_M (RTC_I2C_DETECT_START_INT_ENA_V << RTC_I2C_DETECT_START_INT_ENA_S) +#define RTC_I2C_DETECT_START_INT_ENA_V 0x00000001U +#define RTC_I2C_DETECT_START_INT_ENA_S 8 -#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34) -/* RTC_I2C_DONE : ;bitpos:[31] ;default: ; */ -/*description: i2c done.*/ -#define RTC_I2C_DONE (BIT(31)) -#define RTC_I2C_DONE_M (BIT(31)) -#define RTC_I2C_DONE_V 0x1 -#define RTC_I2C_DONE_S 31 -/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ -/*description: data sent by slave.*/ -#define RTC_I2C_SLAVE_TX_DATA 0x000000FF -#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S)) -#define RTC_I2C_SLAVE_TX_DATA_V 0xFF +/** RTC_I2C_DATA_REG register + * get i2c data status + */ +#define RTC_I2C_DATA_REG (DR_REG_RTC_BASE + 0x34) +/** RTC_I2C_I2C_RDATA : RO; bitpos: [7:0]; default: 0; + * data received + */ +#define RTC_I2C_I2C_RDATA 0x000000FFU +#define RTC_I2C_I2C_RDATA_M (RTC_I2C_I2C_RDATA_V << RTC_I2C_I2C_RDATA_S) +#define RTC_I2C_I2C_RDATA_V 0x000000FFU +#define RTC_I2C_I2C_RDATA_S 0 +/** RTC_I2C_SLAVE_TX_DATA : R/W; bitpos: [15:8]; default: 0; + * data sent by slave + */ +#define RTC_I2C_SLAVE_TX_DATA 0x000000FFU +#define RTC_I2C_SLAVE_TX_DATA_M (RTC_I2C_SLAVE_TX_DATA_V << RTC_I2C_SLAVE_TX_DATA_S) +#define RTC_I2C_SLAVE_TX_DATA_V 0x000000FFU #define RTC_I2C_SLAVE_TX_DATA_S 8 -/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ -/*description: data received.*/ -#define RTC_I2C_RDATA 0x000000FF -#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S)) -#define RTC_I2C_RDATA_V 0xFF -#define RTC_I2C_RDATA_S 0 +/** RTC_I2C_I2C_DONE : RO; bitpos: [31]; default: 0; + * i2c done + */ +#define RTC_I2C_I2C_DONE (BIT(31)) +#define RTC_I2C_I2C_DONE_M (RTC_I2C_I2C_DONE_V << RTC_I2C_I2C_DONE_S) +#define RTC_I2C_I2C_DONE_V 0x00000001U +#define RTC_I2C_I2C_DONE_S 31 -#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38) -/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command0_done.*/ -#define RTC_I2C_COMMAND0_DONE (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND0_DONE_V 0x1 -#define RTC_I2C_COMMAND0_DONE_S 31 -/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command0.*/ -#define RTC_I2C_COMMAND0 0x00003FFF -#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S)) -#define RTC_I2C_COMMAND0_V 0x3FFF +/** RTC_I2C_CMD0_REG register + * i2c commond0 register + */ +#define RTC_I2C_CMD0_REG (DR_REG_RTC_BASE + 0x38) +/** RTC_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 2307; + * command0 + */ +#define RTC_I2C_COMMAND0 0x00003FFFU +#define RTC_I2C_COMMAND0_M (RTC_I2C_COMMAND0_V << RTC_I2C_COMMAND0_S) +#define RTC_I2C_COMMAND0_V 0x00003FFFU #define RTC_I2C_COMMAND0_S 0 +/** RTC_I2C_COMMAND0_DONE : RO; bitpos: [31]; default: 0; + * command0_done + */ +#define RTC_I2C_COMMAND0_DONE (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_M (RTC_I2C_COMMAND0_DONE_V << RTC_I2C_COMMAND0_DONE_S) +#define RTC_I2C_COMMAND0_DONE_V 0x00000001U +#define RTC_I2C_COMMAND0_DONE_S 31 -#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3C) -/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command1_done.*/ -#define RTC_I2C_COMMAND1_DONE (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND1_DONE_V 0x1 -#define RTC_I2C_COMMAND1_DONE_S 31 -/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command1.*/ -#define RTC_I2C_COMMAND1 0x00003FFF -#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S)) -#define RTC_I2C_COMMAND1_V 0x3FFF +/** RTC_I2C_CMD1_REG register + * i2c commond1 register + */ +#define RTC_I2C_CMD1_REG (DR_REG_RTC_BASE + 0x3c) +/** RTC_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 6401; + * command1 + */ +#define RTC_I2C_COMMAND1 0x00003FFFU +#define RTC_I2C_COMMAND1_M (RTC_I2C_COMMAND1_V << RTC_I2C_COMMAND1_S) +#define RTC_I2C_COMMAND1_V 0x00003FFFU #define RTC_I2C_COMMAND1_S 0 +/** RTC_I2C_COMMAND1_DONE : RO; bitpos: [31]; default: 0; + * command1_done + */ +#define RTC_I2C_COMMAND1_DONE (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_M (RTC_I2C_COMMAND1_DONE_V << RTC_I2C_COMMAND1_DONE_S) +#define RTC_I2C_COMMAND1_DONE_V 0x00000001U +#define RTC_I2C_COMMAND1_DONE_S 31 -#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40) -/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command2_done.*/ -#define RTC_I2C_COMMAND2_DONE (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND2_DONE_V 0x1 -#define RTC_I2C_COMMAND2_DONE_S 31 -/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ -/*description: command2.*/ -#define RTC_I2C_COMMAND2 0x00003FFF -#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S)) -#define RTC_I2C_COMMAND2_V 0x3FFF +/** RTC_I2C_CMD2_REG register + * i2c commond2 register + */ +#define RTC_I2C_CMD2_REG (DR_REG_RTC_BASE + 0x40) +/** RTC_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 2306; + * command2 + */ +#define RTC_I2C_COMMAND2 0x00003FFFU +#define RTC_I2C_COMMAND2_M (RTC_I2C_COMMAND2_V << RTC_I2C_COMMAND2_S) +#define RTC_I2C_COMMAND2_V 0x00003FFFU #define RTC_I2C_COMMAND2_S 0 +/** RTC_I2C_COMMAND2_DONE : RO; bitpos: [31]; default: 0; + * command2_done + */ +#define RTC_I2C_COMMAND2_DONE (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_M (RTC_I2C_COMMAND2_DONE_V << RTC_I2C_COMMAND2_DONE_S) +#define RTC_I2C_COMMAND2_DONE_V 0x00000001U +#define RTC_I2C_COMMAND2_DONE_S 31 -#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44) -/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command3_done.*/ -#define RTC_I2C_COMMAND3_DONE (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND3_DONE_V 0x1 -#define RTC_I2C_COMMAND3_DONE_S 31 -/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command3.*/ -#define RTC_I2C_COMMAND3 0x00003FFF -#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S)) -#define RTC_I2C_COMMAND3_V 0x3FFF +/** RTC_I2C_CMD3_REG register + * i2c commond3 register + */ +#define RTC_I2C_CMD3_REG (DR_REG_RTC_BASE + 0x44) +/** RTC_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 257; + * command3 + */ +#define RTC_I2C_COMMAND3 0x00003FFFU +#define RTC_I2C_COMMAND3_M (RTC_I2C_COMMAND3_V << RTC_I2C_COMMAND3_S) +#define RTC_I2C_COMMAND3_V 0x00003FFFU #define RTC_I2C_COMMAND3_S 0 +/** RTC_I2C_COMMAND3_DONE : RO; bitpos: [31]; default: 0; + * command3_done + */ +#define RTC_I2C_COMMAND3_DONE (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_M (RTC_I2C_COMMAND3_DONE_V << RTC_I2C_COMMAND3_DONE_S) +#define RTC_I2C_COMMAND3_DONE_V 0x00000001U +#define RTC_I2C_COMMAND3_DONE_S 31 -#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48) -/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command4_done.*/ -#define RTC_I2C_COMMAND4_DONE (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND4_DONE_V 0x1 -#define RTC_I2C_COMMAND4_DONE_S 31 -/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command4.*/ -#define RTC_I2C_COMMAND4 0x00003FFF -#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S)) -#define RTC_I2C_COMMAND4_V 0x3FFF +/** RTC_I2C_CMD4_REG register + * i2c commond4 register + */ +#define RTC_I2C_CMD4_REG (DR_REG_RTC_BASE + 0x48) +/** RTC_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 2305; + * command4 + */ +#define RTC_I2C_COMMAND4 0x00003FFFU +#define RTC_I2C_COMMAND4_M (RTC_I2C_COMMAND4_V << RTC_I2C_COMMAND4_S) +#define RTC_I2C_COMMAND4_V 0x00003FFFU #define RTC_I2C_COMMAND4_S 0 +/** RTC_I2C_COMMAND4_DONE : RO; bitpos: [31]; default: 0; + * command4_done + */ +#define RTC_I2C_COMMAND4_DONE (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_M (RTC_I2C_COMMAND4_DONE_V << RTC_I2C_COMMAND4_DONE_S) +#define RTC_I2C_COMMAND4_DONE_V 0x00000001U +#define RTC_I2C_COMMAND4_DONE_S 31 -#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4C) -/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command5_done.*/ -#define RTC_I2C_COMMAND5_DONE (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND5_DONE_V 0x1 -#define RTC_I2C_COMMAND5_DONE_S 31 -/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command5.*/ -#define RTC_I2C_COMMAND5 0x00003FFF -#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S)) -#define RTC_I2C_COMMAND5_V 0x3FFF +/** RTC_I2C_CMD5_REG register + * i2c commond5_register + */ +#define RTC_I2C_CMD5_REG (DR_REG_RTC_BASE + 0x4c) +/** RTC_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 5889; + * command5 + */ +#define RTC_I2C_COMMAND5 0x00003FFFU +#define RTC_I2C_COMMAND5_M (RTC_I2C_COMMAND5_V << RTC_I2C_COMMAND5_S) +#define RTC_I2C_COMMAND5_V 0x00003FFFU #define RTC_I2C_COMMAND5_S 0 +/** RTC_I2C_COMMAND5_DONE : RO; bitpos: [31]; default: 0; + * command5_done + */ +#define RTC_I2C_COMMAND5_DONE (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_M (RTC_I2C_COMMAND5_DONE_V << RTC_I2C_COMMAND5_DONE_S) +#define RTC_I2C_COMMAND5_DONE_V 0x00000001U +#define RTC_I2C_COMMAND5_DONE_S 31 -#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50) -/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command6_done.*/ -#define RTC_I2C_COMMAND6_DONE (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND6_DONE_V 0x1 -#define RTC_I2C_COMMAND6_DONE_S 31 -/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command6.*/ -#define RTC_I2C_COMMAND6 0x00003FFF -#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S)) -#define RTC_I2C_COMMAND6_V 0x3FFF +/** RTC_I2C_CMD6_REG register + * i2c commond6 register + */ +#define RTC_I2C_CMD6_REG (DR_REG_RTC_BASE + 0x50) +/** RTC_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 6401; + * command6 + */ +#define RTC_I2C_COMMAND6 0x00003FFFU +#define RTC_I2C_COMMAND6_M (RTC_I2C_COMMAND6_V << RTC_I2C_COMMAND6_S) +#define RTC_I2C_COMMAND6_V 0x00003FFFU #define RTC_I2C_COMMAND6_S 0 +/** RTC_I2C_COMMAND6_DONE : RO; bitpos: [31]; default: 0; + * command6_done + */ +#define RTC_I2C_COMMAND6_DONE (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_M (RTC_I2C_COMMAND6_DONE_V << RTC_I2C_COMMAND6_DONE_S) +#define RTC_I2C_COMMAND6_DONE_V 0x00000001U +#define RTC_I2C_COMMAND6_DONE_S 31 -#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54) -/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command7_done.*/ -#define RTC_I2C_COMMAND7_DONE (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND7_DONE_V 0x1 -#define RTC_I2C_COMMAND7_DONE_S 31 -/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ -/*description: command7.*/ -#define RTC_I2C_COMMAND7 0x00003FFF -#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S)) -#define RTC_I2C_COMMAND7_V 0x3FFF +/** RTC_I2C_CMD7_REG register + * i2c commond7 register + */ +#define RTC_I2C_CMD7_REG (DR_REG_RTC_BASE + 0x54) +/** RTC_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 2308; + * command7 + */ +#define RTC_I2C_COMMAND7 0x00003FFFU +#define RTC_I2C_COMMAND7_M (RTC_I2C_COMMAND7_V << RTC_I2C_COMMAND7_S) +#define RTC_I2C_COMMAND7_V 0x00003FFFU #define RTC_I2C_COMMAND7_S 0 +/** RTC_I2C_COMMAND7_DONE : RO; bitpos: [31]; default: 0; + * command7_done + */ +#define RTC_I2C_COMMAND7_DONE (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_M (RTC_I2C_COMMAND7_DONE_V << RTC_I2C_COMMAND7_DONE_S) +#define RTC_I2C_COMMAND7_DONE_V 0x00000001U +#define RTC_I2C_COMMAND7_DONE_S 31 -#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58) -/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command8_done.*/ -#define RTC_I2C_COMMAND8_DONE (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND8_DONE_V 0x1 -#define RTC_I2C_COMMAND8_DONE_S 31 -/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command8.*/ -#define RTC_I2C_COMMAND8 0x00003FFF -#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S)) -#define RTC_I2C_COMMAND8_V 0x3FFF +/** RTC_I2C_CMD8_REG register + * i2c commond8 register + */ +#define RTC_I2C_CMD8_REG (DR_REG_RTC_BASE + 0x58) +/** RTC_I2C_COMMAND8 : R/W; bitpos: [13:0]; default: 6401; + * command8 + */ +#define RTC_I2C_COMMAND8 0x00003FFFU +#define RTC_I2C_COMMAND8_M (RTC_I2C_COMMAND8_V << RTC_I2C_COMMAND8_S) +#define RTC_I2C_COMMAND8_V 0x00003FFFU #define RTC_I2C_COMMAND8_S 0 +/** RTC_I2C_COMMAND8_DONE : RO; bitpos: [31]; default: 0; + * command8_done + */ +#define RTC_I2C_COMMAND8_DONE (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_M (RTC_I2C_COMMAND8_DONE_V << RTC_I2C_COMMAND8_DONE_S) +#define RTC_I2C_COMMAND8_DONE_V 0x00000001U +#define RTC_I2C_COMMAND8_DONE_S 31 -#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5C) -/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command9_done.*/ -#define RTC_I2C_COMMAND9_DONE (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND9_DONE_V 0x1 -#define RTC_I2C_COMMAND9_DONE_S 31 -/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ -/*description: command9.*/ -#define RTC_I2C_COMMAND9 0x00003FFF -#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S)) -#define RTC_I2C_COMMAND9_V 0x3FFF +/** RTC_I2C_CMD9_REG register + * i2c commond9 register + */ +#define RTC_I2C_CMD9_REG (DR_REG_RTC_BASE + 0x5c) +/** RTC_I2C_COMMAND9 : R/W; bitpos: [13:0]; default: 2307; + * command9 + */ +#define RTC_I2C_COMMAND9 0x00003FFFU +#define RTC_I2C_COMMAND9_M (RTC_I2C_COMMAND9_V << RTC_I2C_COMMAND9_S) +#define RTC_I2C_COMMAND9_V 0x00003FFFU #define RTC_I2C_COMMAND9_S 0 +/** RTC_I2C_COMMAND9_DONE : RO; bitpos: [31]; default: 0; + * command9_done + */ +#define RTC_I2C_COMMAND9_DONE (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_M (RTC_I2C_COMMAND9_DONE_V << RTC_I2C_COMMAND9_DONE_S) +#define RTC_I2C_COMMAND9_DONE_V 0x00000001U +#define RTC_I2C_COMMAND9_DONE_S 31 -#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60) -/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command10_done.*/ -#define RTC_I2C_COMMAND10_DONE (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND10_DONE_V 0x1 -#define RTC_I2C_COMMAND10_DONE_S 31 -/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ -/*description: command10.*/ -#define RTC_I2C_COMMAND10 0x00003FFF -#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S)) -#define RTC_I2C_COMMAND10_V 0x3FFF +/** RTC_I2C_CMD10_REG register + * i2c commond10 register + */ +#define RTC_I2C_CMD10_REG (DR_REG_RTC_BASE + 0x60) +/** RTC_I2C_COMMAND10 : R/W; bitpos: [13:0]; default: 257; + * command10 + */ +#define RTC_I2C_COMMAND10 0x00003FFFU +#define RTC_I2C_COMMAND10_M (RTC_I2C_COMMAND10_V << RTC_I2C_COMMAND10_S) +#define RTC_I2C_COMMAND10_V 0x00003FFFU #define RTC_I2C_COMMAND10_S 0 +/** RTC_I2C_COMMAND10_DONE : RO; bitpos: [31]; default: 0; + * command10_done + */ +#define RTC_I2C_COMMAND10_DONE (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_M (RTC_I2C_COMMAND10_DONE_V << RTC_I2C_COMMAND10_DONE_S) +#define RTC_I2C_COMMAND10_DONE_V 0x00000001U +#define RTC_I2C_COMMAND10_DONE_S 31 -#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64) -/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command11_done.*/ -#define RTC_I2C_COMMAND11_DONE (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND11_DONE_V 0x1 -#define RTC_I2C_COMMAND11_DONE_S 31 -/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ -/*description: command11.*/ -#define RTC_I2C_COMMAND11 0x00003FFF -#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S)) -#define RTC_I2C_COMMAND11_V 0x3FFF +/** RTC_I2C_CMD11_REG register + * i2c commond11 register + */ +#define RTC_I2C_CMD11_REG (DR_REG_RTC_BASE + 0x64) +/** RTC_I2C_COMMAND11 : R/W; bitpos: [13:0]; default: 2305; + * command11 + */ +#define RTC_I2C_COMMAND11 0x00003FFFU +#define RTC_I2C_COMMAND11_M (RTC_I2C_COMMAND11_V << RTC_I2C_COMMAND11_S) +#define RTC_I2C_COMMAND11_V 0x00003FFFU #define RTC_I2C_COMMAND11_S 0 +/** RTC_I2C_COMMAND11_DONE : RO; bitpos: [31]; default: 0; + * command11_done + */ +#define RTC_I2C_COMMAND11_DONE (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_M (RTC_I2C_COMMAND11_DONE_V << RTC_I2C_COMMAND11_DONE_S) +#define RTC_I2C_COMMAND11_DONE_V 0x00000001U +#define RTC_I2C_COMMAND11_DONE_S 31 -#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68) -/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command12_done.*/ -#define RTC_I2C_COMMAND12_DONE (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND12_DONE_V 0x1 -#define RTC_I2C_COMMAND12_DONE_S 31 -/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ -/*description: command12.*/ -#define RTC_I2C_COMMAND12 0x00003FFF -#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S)) -#define RTC_I2C_COMMAND12_V 0x3FFF +/** RTC_I2C_CMD12_REG register + * i2c commond12 register + */ +#define RTC_I2C_CMD12_REG (DR_REG_RTC_BASE + 0x68) +/** RTC_I2C_COMMAND12 : R/W; bitpos: [13:0]; default: 5889; + * command12 + */ +#define RTC_I2C_COMMAND12 0x00003FFFU +#define RTC_I2C_COMMAND12_M (RTC_I2C_COMMAND12_V << RTC_I2C_COMMAND12_S) +#define RTC_I2C_COMMAND12_V 0x00003FFFU #define RTC_I2C_COMMAND12_S 0 +/** RTC_I2C_COMMAND12_DONE : RO; bitpos: [31]; default: 0; + * command12_done + */ +#define RTC_I2C_COMMAND12_DONE (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_M (RTC_I2C_COMMAND12_DONE_V << RTC_I2C_COMMAND12_DONE_S) +#define RTC_I2C_COMMAND12_DONE_V 0x00000001U +#define RTC_I2C_COMMAND12_DONE_S 31 -#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6C) -/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command13_done.*/ -#define RTC_I2C_COMMAND13_DONE (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND13_DONE_V 0x1 -#define RTC_I2C_COMMAND13_DONE_S 31 -/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ -/*description: command13.*/ -#define RTC_I2C_COMMAND13 0x00003FFF -#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S)) -#define RTC_I2C_COMMAND13_V 0x3FFF +/** RTC_I2C_CMD13_REG register + * i2c commond13 register + */ +#define RTC_I2C_CMD13_REG (DR_REG_RTC_BASE + 0x6c) +/** RTC_I2C_COMMAND13 : R/W; bitpos: [13:0]; default: 6401; + * command13 + */ +#define RTC_I2C_COMMAND13 0x00003FFFU +#define RTC_I2C_COMMAND13_M (RTC_I2C_COMMAND13_V << RTC_I2C_COMMAND13_S) +#define RTC_I2C_COMMAND13_V 0x00003FFFU #define RTC_I2C_COMMAND13_S 0 +/** RTC_I2C_COMMAND13_DONE : RO; bitpos: [31]; default: 0; + * command13_done + */ +#define RTC_I2C_COMMAND13_DONE (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_M (RTC_I2C_COMMAND13_DONE_V << RTC_I2C_COMMAND13_DONE_S) +#define RTC_I2C_COMMAND13_DONE_V 0x00000001U +#define RTC_I2C_COMMAND13_DONE_S 31 -#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70) -/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command14_done.*/ -#define RTC_I2C_COMMAND14_DONE (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND14_DONE_V 0x1 -#define RTC_I2C_COMMAND14_DONE_S 31 -/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command14.*/ -#define RTC_I2C_COMMAND14 0x00003FFF -#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S)) -#define RTC_I2C_COMMAND14_V 0x3FFF +/** RTC_I2C_CMD14_REG register + * i2c commond14 register + */ +#define RTC_I2C_CMD14_REG (DR_REG_RTC_BASE + 0x70) +/** RTC_I2C_COMMAND14 : R/W; bitpos: [13:0]; default: 0; + * command14 + */ +#define RTC_I2C_COMMAND14 0x00003FFFU +#define RTC_I2C_COMMAND14_M (RTC_I2C_COMMAND14_V << RTC_I2C_COMMAND14_S) +#define RTC_I2C_COMMAND14_V 0x00003FFFU #define RTC_I2C_COMMAND14_S 0 +/** RTC_I2C_COMMAND14_DONE : RO; bitpos: [31]; default: 0; + * command14_done + */ +#define RTC_I2C_COMMAND14_DONE (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_M (RTC_I2C_COMMAND14_DONE_V << RTC_I2C_COMMAND14_DONE_S) +#define RTC_I2C_COMMAND14_DONE_V 0x00000001U +#define RTC_I2C_COMMAND14_DONE_S 31 -#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74) -/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ -/*description: command15_done.*/ -#define RTC_I2C_COMMAND15_DONE (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) -#define RTC_I2C_COMMAND15_DONE_V 0x1 -#define RTC_I2C_COMMAND15_DONE_S 31 -/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ -/*description: command15.*/ -#define RTC_I2C_COMMAND15 0x00003FFF -#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S)) -#define RTC_I2C_COMMAND15_V 0x3FFF +/** RTC_I2C_CMD15_REG register + * i2c commond15 register + */ +#define RTC_I2C_CMD15_REG (DR_REG_RTC_BASE + 0x74) +/** RTC_I2C_COMMAND15 : R/W; bitpos: [13:0]; default: 0; + * command15 + */ +#define RTC_I2C_COMMAND15 0x00003FFFU +#define RTC_I2C_COMMAND15_M (RTC_I2C_COMMAND15_V << RTC_I2C_COMMAND15_S) +#define RTC_I2C_COMMAND15_V 0x00003FFFU #define RTC_I2C_COMMAND15_S 0 +/** RTC_I2C_COMMAND15_DONE : RO; bitpos: [31]; default: 0; + * command15_done + */ +#define RTC_I2C_COMMAND15_DONE (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_M (RTC_I2C_COMMAND15_DONE_V << RTC_I2C_COMMAND15_DONE_S) +#define RTC_I2C_COMMAND15_DONE_V 0x00000001U +#define RTC_I2C_COMMAND15_DONE_S 31 -#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xFC) -/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ -/*description: .*/ -#define RTC_I2C_DATE 0x0FFFFFFF -#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S)) -#define RTC_I2C_DATE_V 0xFFFFFFF -#define RTC_I2C_DATE_S 0 - +/** RTC_I2C_DATE_REG register + * version register + */ +#define RTC_I2C_DATE_REG (DR_REG_RTC_BASE + 0xfc) +/** RTC_I2C_I2C_DATE : R/W; bitpos: [27:0]; default: 26235664; + * version + */ +#define RTC_I2C_I2C_DATE 0x0FFFFFFFU +#define RTC_I2C_I2C_DATE_M (RTC_I2C_I2C_DATE_V << RTC_I2C_I2C_DATE_S) +#define RTC_I2C_I2C_DATE_V 0x0FFFFFFFU +#define RTC_I2C_I2C_DATE_S 0 #ifdef __cplusplus } #endif - - - -#endif /*_SOC_RTC_I2C_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h index 7d4a4caff4..8641683f16 100644 --- a/components/soc/esp32s3/include/soc/rtc_i2c_struct.h +++ b/components/soc/esp32s3/include/soc/rtc_i2c_struct.h @@ -1,232 +1,780 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RTC_I2C_STRUCT_H_ -#define _SOC_RTC_I2C_STRUCT_H_ - +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t period : 20; /*time period that scl = 0*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } scl_low; - union { - struct { - uint32_t sda_force_out : 1; /*1=push pull, 0=open drain*/ - uint32_t scl_force_out : 1; /*1=push pull, 0=open drain*/ - uint32_t ms_mode : 1; /*1=master, 0=slave*/ - uint32_t trans_start : 1; /*force start*/ - uint32_t tx_lsb_first : 1; /*transit lsb first*/ - uint32_t rx_lsb_first : 1; /*receive lsb first*/ - uint32_t reserved6 : 23; - uint32_t i2c_ctrl_clk_gate_en : 1; - uint32_t i2c_reset : 1; /*rtc i2c sw reset*/ - uint32_t i2cclk_en : 1; /*rtc i2c reg clk gating*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t ack_rec : 1; /*ack response*/ - uint32_t slave_rw : 1; /*slave read or write*/ - uint32_t arb_lost : 1; /*arbitration is lost*/ - uint32_t bus_busy : 1; /*bus is busy*/ - uint32_t slave_addressed : 1; /*slave reg sub address*/ - uint32_t byte_trans : 1; /*One byte transit done*/ - uint32_t op_cnt : 2; /*which operation is working*/ - uint32_t reserved8 : 8; - uint32_t shift : 8; /*shifter content*/ - uint32_t scl_main_state_last : 3; /*i2c last main status*/ - uint32_t reserved27 : 1; - uint32_t scl_state_last : 3; /*scl last status*/ - uint32_t reserved31 : 1; - }; - uint32_t val; - } status; - union { - struct { - uint32_t time_out : 20; /*time out threshold*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } timeout; - union { - struct { - uint32_t addr : 15; /*slave address*/ - uint32_t reserved15 : 16; - uint32_t en_10bit : 1; /*i2c 10bit mode enable*/ - }; - uint32_t val; - } slave_addr; - union { - struct { - uint32_t period : 20; /*time period that scl = 1*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } scl_high; - union { - struct { - uint32_t sda_duty_num : 20; /*time period for SDA to toggle after SCL goes low*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } sda_duty; - union { - struct { - uint32_t scl_start_period : 20; /*time period for SCL to toggle after I2C start is triggered*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } scl_start_period; - union { - struct { - uint32_t scl_stop_period : 20; /*time period for SCL to stop after I2C end is triggered*/ - uint32_t reserved20 : 12; - }; - uint32_t val; - } scl_stop_period; - union { - struct { - uint32_t slave_tran_comp : 1; /*clear slave transit complete interrupt*/ - uint32_t arbitration_lost : 1; /*clear arbitration lost interrupt*/ - uint32_t master_tran_comp : 1; /*clear master transit complete interrupt*/ - uint32_t trans_complete : 1; /*clear transit complete interrupt*/ - uint32_t time_out : 1; /*clear time out interrupt*/ - uint32_t ack_err : 1; /*clear ack error interrupt*/ - uint32_t rx_data : 1; /*clear receive data interrupt*/ - uint32_t tx_data : 1; /*clear transit load data complete interrupt*/ - uint32_t detect_start : 1; /*clear detect start interrupt*/ - uint32_t reserved9 : 23; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t slave_tran_comp : 1; /*slave transit complete interrupt raw*/ - uint32_t arbitration_lost : 1; /*arbitration lost interrupt raw*/ - uint32_t master_tran_comp : 1; /*master transit complete interrupt raw*/ - uint32_t trans_complete : 1; /*transit complete interrupt raw*/ - uint32_t time_out : 1; /*time out interrupt raw*/ - uint32_t ack_err : 1; /*ack error interrupt raw*/ - uint32_t rx_data : 1; /*receive data interrupt raw*/ - uint32_t tx_data : 1; /*transit data interrupt raw*/ - uint32_t detect_start : 1; /*detect start interrupt raw*/ - uint32_t reserved9 : 23; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t slave_tran_comp : 1; /*slave transit complete interrupt state*/ - uint32_t arbitration_lost : 1; /*arbitration lost interrupt state*/ - uint32_t master_tran_comp : 1; /*master transit complete interrupt state*/ - uint32_t trans_complete : 1; /*transit complete interrupt state*/ - uint32_t time_out : 1; /*time out interrupt state*/ - uint32_t ack_err : 1; /*ack error interrupt state*/ - uint32_t rx_data : 1; /*receive data interrupt state*/ - uint32_t tx_data : 1; /*transit data interrupt state*/ - uint32_t detect_start : 1; /*detect start interrupt state*/ - uint32_t reserved9 : 23; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t slave_tran_comp : 1; /*enable slave transit complete interrupt*/ - uint32_t arbitration_lost : 1; /*enable arbitration lost interrupt*/ - uint32_t master_tran_comp : 1; /*enable master transit complete interrupt*/ - uint32_t trans_complete : 1; /*enable transit complete interrupt*/ - uint32_t time_out : 1; /*enable time out interrupt*/ - uint32_t ack_err : 1; /*enable eack error interrupt*/ - uint32_t rx_data : 1; /*enable receive data interrupt*/ - uint32_t tx_data : 1; /*enable transit data interrupt*/ - uint32_t detect_start : 1; /*enable detect start interrupt*/ - uint32_t reserved9 : 23; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t i2c_rdata : 8; /*data received*/ - uint32_t slave_tx_data : 8; /*data sent by slave*/ - uint32_t reserved16 : 15; - uint32_t i2c_done : 1; /*i2c done*/ - }; - uint32_t val; - } fifo_data; - union { - struct { - uint32_t command0 : 14; /* command0*/ - uint32_t reserved14 : 17; - uint32_t done : 1; /* command0_done*/ - }; - uint32_t val; - } command[16]; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t reserved_98; - uint32_t reserved_9c; - uint32_t reserved_a0; - uint32_t reserved_a4; - uint32_t reserved_a8; - uint32_t reserved_ac; - uint32_t reserved_b0; - uint32_t reserved_b4; - uint32_t reserved_b8; - uint32_t reserved_bc; - uint32_t reserved_c0; - uint32_t reserved_c4; - uint32_t reserved_c8; - uint32_t reserved_cc; - uint32_t reserved_d0; - uint32_t reserved_d4; - uint32_t reserved_d8; - uint32_t reserved_dc; - uint32_t reserved_e0; - uint32_t reserved_e4; - uint32_t reserved_e8; - uint32_t reserved_ec; - uint32_t reserved_f0; - uint32_t reserved_f4; - uint32_t reserved_f8; - union { - struct { - uint32_t i2c_date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; -} rtc_i2c_dev_t; -extern rtc_i2c_dev_t RTC_I2C; +/** Group: Configure Registers */ +/** Type of i2c_scl_low register + * configure low scl period + */ +typedef union { + struct { + /** i2c_scl_low_period_reg : R/W; bitpos: [19:0]; default: 256; + * time period that scl =0 + */ + uint32_t i2c_scl_low_period_reg:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_scl_low_reg_t; + +/** Type of i2c_ctrl register + * configure i2c ctrl + */ +typedef union { + struct { + /** i2c_sda_force_out : R/W; bitpos: [0]; default: 0; + * 1=push pull,0=open drain + */ + uint32_t i2c_sda_force_out:1; + /** i2c_scl_force_out : R/W; bitpos: [1]; default: 0; + * 1=push pull,0=open drain + */ + uint32_t i2c_scl_force_out:1; + /** i2c_ms_mode : R/W; bitpos: [2]; default: 0; + * 1=master,0=slave + */ + uint32_t i2c_ms_mode:1; + /** i2c_trans_start : R/W; bitpos: [3]; default: 0; + * force start + */ + uint32_t i2c_trans_start:1; + /** i2c_tx_lsb_first : R/W; bitpos: [4]; default: 0; + * transit lsb first + */ + uint32_t i2c_tx_lsb_first:1; + /** i2c_rx_lsb_first : R/W; bitpos: [5]; default: 0; + * receive lsb first + */ + uint32_t i2c_rx_lsb_first:1; + uint32_t reserved_6:23; + /** i2c_i2c_ctrl_clk_gate_en : R/W; bitpos: [29]; default: 0; + * configure i2c ctrl clk enable + */ + uint32_t i2c_i2c_ctrl_clk_gate_en:1; + /** i2c_i2c_reset : R/W; bitpos: [30]; default: 0; + * rtc i2c sw reset + */ + uint32_t i2c_i2c_reset:1; + /** i2c_i2cclk_en : R/W; bitpos: [31]; default: 0; + * rtc i2c reg clk gating + */ + uint32_t i2c_i2cclk_en:1; + }; + uint32_t val; +} rtc_i2c_ctrl_reg_t; + +/** Type of i2c_to register + * configure time out + */ +typedef union { + struct { + /** i2c_time_out_reg : R/W; bitpos: [19:0]; default: 65536; + * time out threshold + */ + uint32_t i2c_time_out_reg:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_to_reg_t; + +/** Type of i2c_slave_addr register + * configure slave id + */ +typedef union { + struct { + /** i2c_slave_addr : R/W; bitpos: [14:0]; default: 0; + * slave address + */ + uint32_t i2c_slave_addr:15; + uint32_t reserved_15:16; + /** i2c_addr_10bit_en : R/W; bitpos: [31]; default: 0; + * i2c 10bit mode enable + */ + uint32_t i2c_addr_10bit_en:1; + }; + uint32_t val; +} rtc_i2c_slave_addr_reg_t; + +/** Type of i2c_scl_high register + * configure high scl period + */ +typedef union { + struct { + /** i2c_scl_high_period_reg : R/W; bitpos: [19:0]; default: 256; + * time period that scl = 1 + */ + uint32_t i2c_scl_high_period_reg:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_scl_high_reg_t; + +/** Type of i2c_sda_duty register + * configure sda duty + */ +typedef union { + struct { + /** i2c_sda_duty_num : R/W; bitpos: [19:0]; default: 16; + * time period for SDA to toggle after SCL goes low + */ + uint32_t i2c_sda_duty_num:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_sda_duty_reg_t; + +/** Type of i2c_scl_start_period register + * configure scl start period + */ +typedef union { + struct { + /** i2c_scl_start_period : R/W; bitpos: [19:0]; default: 8; + * time period for SCL to toggle after I2C start is triggered + */ + uint32_t i2c_scl_start_period:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_scl_start_period_reg_t; + +/** Type of i2c_scl_stop_period register + * configure scl stop period + */ +typedef union { + struct { + /** i2c_scl_stop_period : R/W; bitpos: [19:0]; default: 8; + * time period for SCL to stop after I2C end is triggered + */ + uint32_t i2c_scl_stop_period:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} rtc_i2c_scl_stop_period_reg_t; + +/** Type of i2c_data register + * get i2c data status + */ +typedef union { + struct { + /** i2c_i2c_rdata : RO; bitpos: [7:0]; default: 0; + * data received + */ + uint32_t i2c_i2c_rdata:8; + /** i2c_slave_tx_data : R/W; bitpos: [15:8]; default: 0; + * data sent by slave + */ + uint32_t i2c_slave_tx_data:8; + uint32_t reserved_16:15; + /** i2c_i2c_done : RO; bitpos: [31]; default: 0; + * i2c done + */ + uint32_t i2c_i2c_done:1; + }; + uint32_t val; +} rtc_i2c_data_reg_t; + +/** Type of i2c_cmd0 register + * i2c commond0 register + */ +typedef union { + struct { + /** i2c_command0 : R/W; bitpos: [13:0]; default: 2307; + * command0 + */ + uint32_t i2c_command0:14; + uint32_t reserved_14:17; + /** i2c_command0_done : RO; bitpos: [31]; default: 0; + * command0_done + */ + uint32_t i2c_command0_done:1; + }; + uint32_t val; +} rtc_i2c_cmd0_reg_t; + +/** Type of i2c_cmd1 register + * i2c commond1 register + */ +typedef union { + struct { + /** i2c_command1 : R/W; bitpos: [13:0]; default: 6401; + * command1 + */ + uint32_t i2c_command1:14; + uint32_t reserved_14:17; + /** i2c_command1_done : RO; bitpos: [31]; default: 0; + * command1_done + */ + uint32_t i2c_command1_done:1; + }; + uint32_t val; +} rtc_i2c_cmd1_reg_t; + +/** Type of i2c_cmd2 register + * i2c commond2 register + */ +typedef union { + struct { + /** i2c_command2 : R/W; bitpos: [13:0]; default: 2306; + * command2 + */ + uint32_t i2c_command2:14; + uint32_t reserved_14:17; + /** i2c_command2_done : RO; bitpos: [31]; default: 0; + * command2_done + */ + uint32_t i2c_command2_done:1; + }; + uint32_t val; +} rtc_i2c_cmd2_reg_t; + +/** Type of i2c_cmd3 register + * i2c commond3 register + */ +typedef union { + struct { + /** i2c_command3 : R/W; bitpos: [13:0]; default: 257; + * command3 + */ + uint32_t i2c_command3:14; + uint32_t reserved_14:17; + /** i2c_command3_done : RO; bitpos: [31]; default: 0; + * command3_done + */ + uint32_t i2c_command3_done:1; + }; + uint32_t val; +} rtc_i2c_cmd3_reg_t; + +/** Type of i2c_cmd4 register + * i2c commond4 register + */ +typedef union { + struct { + /** i2c_command4 : R/W; bitpos: [13:0]; default: 2305; + * command4 + */ + uint32_t i2c_command4:14; + uint32_t reserved_14:17; + /** i2c_command4_done : RO; bitpos: [31]; default: 0; + * command4_done + */ + uint32_t i2c_command4_done:1; + }; + uint32_t val; +} rtc_i2c_cmd4_reg_t; + +/** Type of i2c_cmd5 register + * i2c commond5_register + */ +typedef union { + struct { + /** i2c_command5 : R/W; bitpos: [13:0]; default: 5889; + * command5 + */ + uint32_t i2c_command5:14; + uint32_t reserved_14:17; + /** i2c_command5_done : RO; bitpos: [31]; default: 0; + * command5_done + */ + uint32_t i2c_command5_done:1; + }; + uint32_t val; +} rtc_i2c_cmd5_reg_t; + +/** Type of i2c_cmd6 register + * i2c commond6 register + */ +typedef union { + struct { + /** i2c_command6 : R/W; bitpos: [13:0]; default: 6401; + * command6 + */ + uint32_t i2c_command6:14; + uint32_t reserved_14:17; + /** i2c_command6_done : RO; bitpos: [31]; default: 0; + * command6_done + */ + uint32_t i2c_command6_done:1; + }; + uint32_t val; +} rtc_i2c_cmd6_reg_t; + +/** Type of i2c_cmd7 register + * i2c commond7 register + */ +typedef union { + struct { + /** i2c_command7 : R/W; bitpos: [13:0]; default: 2308; + * command7 + */ + uint32_t i2c_command7:14; + uint32_t reserved_14:17; + /** i2c_command7_done : RO; bitpos: [31]; default: 0; + * command7_done + */ + uint32_t i2c_command7_done:1; + }; + uint32_t val; +} rtc_i2c_cmd7_reg_t; + +/** Type of i2c_cmd8 register + * i2c commond8 register + */ +typedef union { + struct { + /** i2c_command8 : R/W; bitpos: [13:0]; default: 6401; + * command8 + */ + uint32_t i2c_command8:14; + uint32_t reserved_14:17; + /** i2c_command8_done : RO; bitpos: [31]; default: 0; + * command8_done + */ + uint32_t i2c_command8_done:1; + }; + uint32_t val; +} rtc_i2c_cmd8_reg_t; + +/** Type of i2c_cmd9 register + * i2c commond9 register + */ +typedef union { + struct { + /** i2c_command9 : R/W; bitpos: [13:0]; default: 2307; + * command9 + */ + uint32_t i2c_command9:14; + uint32_t reserved_14:17; + /** i2c_command9_done : RO; bitpos: [31]; default: 0; + * command9_done + */ + uint32_t i2c_command9_done:1; + }; + uint32_t val; +} rtc_i2c_cmd9_reg_t; + +/** Type of i2c_cmd10 register + * i2c commond10 register + */ +typedef union { + struct { + /** i2c_command10 : R/W; bitpos: [13:0]; default: 257; + * command10 + */ + uint32_t i2c_command10:14; + uint32_t reserved_14:17; + /** i2c_command10_done : RO; bitpos: [31]; default: 0; + * command10_done + */ + uint32_t i2c_command10_done:1; + }; + uint32_t val; +} rtc_i2c_cmd10_reg_t; + +/** Type of i2c_cmd11 register + * i2c commond11 register + */ +typedef union { + struct { + /** i2c_command11 : R/W; bitpos: [13:0]; default: 2305; + * command11 + */ + uint32_t i2c_command11:14; + uint32_t reserved_14:17; + /** i2c_command11_done : RO; bitpos: [31]; default: 0; + * command11_done + */ + uint32_t i2c_command11_done:1; + }; + uint32_t val; +} rtc_i2c_cmd11_reg_t; + +/** Type of i2c_cmd12 register + * i2c commond12 register + */ +typedef union { + struct { + /** i2c_command12 : R/W; bitpos: [13:0]; default: 5889; + * command12 + */ + uint32_t i2c_command12:14; + uint32_t reserved_14:17; + /** i2c_command12_done : RO; bitpos: [31]; default: 0; + * command12_done + */ + uint32_t i2c_command12_done:1; + }; + uint32_t val; +} rtc_i2c_cmd12_reg_t; + +/** Type of i2c_cmd13 register + * i2c commond13 register + */ +typedef union { + struct { + /** i2c_command13 : R/W; bitpos: [13:0]; default: 6401; + * command13 + */ + uint32_t i2c_command13:14; + uint32_t reserved_14:17; + /** i2c_command13_done : RO; bitpos: [31]; default: 0; + * command13_done + */ + uint32_t i2c_command13_done:1; + }; + uint32_t val; +} rtc_i2c_cmd13_reg_t; + +/** Type of i2c_cmd14 register + * i2c commond14 register + */ +typedef union { + struct { + /** i2c_command14 : R/W; bitpos: [13:0]; default: 0; + * command14 + */ + uint32_t i2c_command14:14; + uint32_t reserved_14:17; + /** i2c_command14_done : RO; bitpos: [31]; default: 0; + * command14_done + */ + uint32_t i2c_command14_done:1; + }; + uint32_t val; +} rtc_i2c_cmd14_reg_t; + +/** Type of i2c_cmd15 register + * i2c commond15 register + */ +typedef union { + struct { + /** i2c_command15 : R/W; bitpos: [13:0]; default: 0; + * command15 + */ + uint32_t i2c_command15:14; + uint32_t reserved_14:17; + /** i2c_command15_done : RO; bitpos: [31]; default: 0; + * command15_done + */ + uint32_t i2c_command15_done:1; + }; + uint32_t val; +} rtc_i2c_cmd15_reg_t; + + +/** Group: status register */ +/** Type of i2c_status register + * get i2c status + */ +typedef union { + struct { + /** i2c_ack_rec : RO; bitpos: [0]; default: 0; + * ack response + */ + uint32_t i2c_ack_rec:1; + /** i2c_slave_rw : RO; bitpos: [1]; default: 0; + * slave read or write + */ + uint32_t i2c_slave_rw:1; + /** i2c_arb_lost : RO; bitpos: [2]; default: 0; + * arbitration is lost + */ + uint32_t i2c_arb_lost:1; + /** i2c_bus_busy : RO; bitpos: [3]; default: 0; + * bus is busy + */ + uint32_t i2c_bus_busy:1; + /** i2c_slave_addressed : RO; bitpos: [4]; default: 0; + * slave reg sub address + */ + uint32_t i2c_slave_addressed:1; + /** i2c_byte_trans : RO; bitpos: [5]; default: 0; + * One byte transit done + */ + uint32_t i2c_byte_trans:1; + /** i2c_op_cnt : RO; bitpos: [7:6]; default: 0; + * which operation is working + */ + uint32_t i2c_op_cnt:2; + uint32_t reserved_8:8; + /** i2c_shift_reg : RO; bitpos: [23:16]; default: 0; + * shifter content + */ + uint32_t i2c_shift_reg:8; + /** i2c_scl_main_state_last : RO; bitpos: [26:24]; default: 0; + * i2c last main status + */ + uint32_t i2c_scl_main_state_last:3; + uint32_t reserved_27:1; + /** i2c_scl_state_last : RO; bitpos: [30:28]; default: 0; + * scl last status + */ + uint32_t i2c_scl_state_last:3; + uint32_t reserved_31:1; + }; + uint32_t val; +} rtc_i2c_status_reg_t; + + +/** Group: interrupt Register */ +/** Type of i2c_int_clr register + * interrupt clear register + */ +typedef union { + struct { + /** i2c_slave_tran_comp_int_clr : WO; bitpos: [0]; default: 0; + * clear slave transit complete interrupt + */ + uint32_t i2c_slave_tran_comp_int_clr:1; + /** i2c_arbitration_lost_int_clr : WO; bitpos: [1]; default: 0; + * clear arbitration lost interrupt + */ + uint32_t i2c_arbitration_lost_int_clr:1; + /** i2c_master_tran_comp_int_clr : WO; bitpos: [2]; default: 0; + * clear master transit complete interrupt + */ + uint32_t i2c_master_tran_comp_int_clr:1; + /** i2c_trans_complete_int_clr : WO; bitpos: [3]; default: 0; + * clear transit complete interrupt + */ + uint32_t i2c_trans_complete_int_clr:1; + /** i2c_time_out_int_clr : WO; bitpos: [4]; default: 0; + * clear time out interrupt + */ + uint32_t i2c_time_out_int_clr:1; + /** i2c_ack_err_int_clr : WO; bitpos: [5]; default: 0; + * clear ack error interrupt + */ + uint32_t i2c_ack_err_int_clr:1; + /** i2c_rx_data_int_clr : WO; bitpos: [6]; default: 0; + * clear receive data interrupt + */ + uint32_t i2c_rx_data_int_clr:1; + /** i2c_tx_data_int_clr : WO; bitpos: [7]; default: 0; + * clear transit load data complete interrupt + */ + uint32_t i2c_tx_data_int_clr:1; + /** i2c_detect_start_int_clr : WO; bitpos: [8]; default: 0; + * clear detect start interrupt + */ + uint32_t i2c_detect_start_int_clr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} rtc_i2c_int_clr_reg_t; + +/** Type of i2c_int_raw register + * interrupt raw register + */ +typedef union { + struct { + /** i2c_slave_tran_comp_int_raw : RO; bitpos: [0]; default: 0; + * slave transit complete interrupt raw + */ + uint32_t i2c_slave_tran_comp_int_raw:1; + /** i2c_arbitration_lost_int_raw : RO; bitpos: [1]; default: 0; + * arbitration lost interrupt raw + */ + uint32_t i2c_arbitration_lost_int_raw:1; + /** i2c_master_tran_comp_int_raw : RO; bitpos: [2]; default: 0; + * master transit complete interrupt raw + */ + uint32_t i2c_master_tran_comp_int_raw:1; + /** i2c_trans_complete_int_raw : RO; bitpos: [3]; default: 0; + * transit complete interrupt raw + */ + uint32_t i2c_trans_complete_int_raw:1; + /** i2c_time_out_int_raw : RO; bitpos: [4]; default: 0; + * time out interrupt raw + */ + uint32_t i2c_time_out_int_raw:1; + /** i2c_ack_err_int_raw : RO; bitpos: [5]; default: 0; + * ack error interrupt raw + */ + uint32_t i2c_ack_err_int_raw:1; + /** i2c_rx_data_int_raw : RO; bitpos: [6]; default: 0; + * receive data interrupt raw + */ + uint32_t i2c_rx_data_int_raw:1; + /** i2c_tx_data_int_raw : RO; bitpos: [7]; default: 0; + * transit data interrupt raw + */ + uint32_t i2c_tx_data_int_raw:1; + /** i2c_detect_start_int_raw : RO; bitpos: [8]; default: 0; + * detect start interrupt raw + */ + uint32_t i2c_detect_start_int_raw:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} rtc_i2c_int_raw_reg_t; + +/** Type of i2c_int_st register + * interrupt state register + */ +typedef union { + struct { + /** i2c_slave_tran_comp_int_st : RO; bitpos: [0]; default: 0; + * slave transit complete interrupt state + */ + uint32_t i2c_slave_tran_comp_int_st:1; + /** i2c_arbitration_lost_int_st : RO; bitpos: [1]; default: 0; + * arbitration lost interrupt state + */ + uint32_t i2c_arbitration_lost_int_st:1; + /** i2c_master_tran_comp_int_st : RO; bitpos: [2]; default: 0; + * master transit complete interrupt state + */ + uint32_t i2c_master_tran_comp_int_st:1; + /** i2c_trans_complete_int_st : RO; bitpos: [3]; default: 0; + * transit complete interrupt state + */ + uint32_t i2c_trans_complete_int_st:1; + /** i2c_time_out_int_st : RO; bitpos: [4]; default: 0; + * time out interrupt state + */ + uint32_t i2c_time_out_int_st:1; + /** i2c_ack_err_int_st : RO; bitpos: [5]; default: 0; + * ack error interrupt state + */ + uint32_t i2c_ack_err_int_st:1; + /** i2c_rx_data_int_st : RO; bitpos: [6]; default: 0; + * receive data interrupt state + */ + uint32_t i2c_rx_data_int_st:1; + /** i2c_tx_data_int_st : RO; bitpos: [7]; default: 0; + * transit data interrupt state + */ + uint32_t i2c_tx_data_int_st:1; + /** i2c_detect_start_int_st : RO; bitpos: [8]; default: 0; + * detect start interrupt state + */ + uint32_t i2c_detect_start_int_st:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} rtc_i2c_int_st_reg_t; + +/** Type of i2c_int_ena register + * interrupt enable register + */ +typedef union { + struct { + /** i2c_slave_tran_comp_int_ena : R/W; bitpos: [0]; default: 0; + * enable slave transit complete interrupt + */ + uint32_t i2c_slave_tran_comp_int_ena:1; + /** i2c_arbitration_lost_int_ena : R/W; bitpos: [1]; default: 0; + * enable arbitration lost interrupt + */ + uint32_t i2c_arbitration_lost_int_ena:1; + /** i2c_master_tran_comp_int_ena : R/W; bitpos: [2]; default: 0; + * enable master transit complete interrupt + */ + uint32_t i2c_master_tran_comp_int_ena:1; + /** i2c_trans_complete_int_ena : R/W; bitpos: [3]; default: 0; + * enable transit complete interrupt + */ + uint32_t i2c_trans_complete_int_ena:1; + /** i2c_time_out_int_ena : R/W; bitpos: [4]; default: 0; + * enable time out interrupt + */ + uint32_t i2c_time_out_int_ena:1; + /** i2c_ack_err_int_ena : R/W; bitpos: [5]; default: 0; + * enable eack error interrupt + */ + uint32_t i2c_ack_err_int_ena:1; + /** i2c_rx_data_int_ena : R/W; bitpos: [6]; default: 0; + * enable receive data interrupt + */ + uint32_t i2c_rx_data_int_ena:1; + /** i2c_tx_data_int_ena : R/W; bitpos: [7]; default: 0; + * enable transit data interrupt + */ + uint32_t i2c_tx_data_int_ena:1; + /** i2c_detect_start_int_ena : R/W; bitpos: [8]; default: 0; + * enable detect start interrupt + */ + uint32_t i2c_detect_start_int_ena:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} rtc_i2c_int_ena_reg_t; + + +/** Group: version Registers */ +/** Type of i2c_date register + * version register + */ +typedef union { + struct { + /** i2c_i2c_date : R/W; bitpos: [27:0]; default: 26235664; + * version + */ + uint32_t i2c_i2c_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} rtc_i2c_date_reg_t; + + +typedef struct { + volatile rtc_i2c_scl_low_reg_t i2c_scl_low; + volatile rtc_i2c_ctrl_reg_t i2c_ctrl; + volatile rtc_i2c_status_reg_t i2c_status; + volatile rtc_i2c_to_reg_t i2c_to; + volatile rtc_i2c_slave_addr_reg_t i2c_slave_addr; + volatile rtc_i2c_scl_high_reg_t i2c_scl_high; + volatile rtc_i2c_sda_duty_reg_t i2c_sda_duty; + volatile rtc_i2c_scl_start_period_reg_t i2c_scl_start_period; + volatile rtc_i2c_scl_stop_period_reg_t i2c_scl_stop_period; + volatile rtc_i2c_int_clr_reg_t i2c_int_clr; + volatile rtc_i2c_int_raw_reg_t i2c_int_raw; + volatile rtc_i2c_int_st_reg_t i2c_int_st; + volatile rtc_i2c_int_ena_reg_t i2c_int_ena; + volatile rtc_i2c_data_reg_t i2c_data; + volatile rtc_i2c_cmd0_reg_t i2c_cmd0; + volatile rtc_i2c_cmd1_reg_t i2c_cmd1; + volatile rtc_i2c_cmd2_reg_t i2c_cmd2; + volatile rtc_i2c_cmd3_reg_t i2c_cmd3; + volatile rtc_i2c_cmd4_reg_t i2c_cmd4; + volatile rtc_i2c_cmd5_reg_t i2c_cmd5; + volatile rtc_i2c_cmd6_reg_t i2c_cmd6; + volatile rtc_i2c_cmd7_reg_t i2c_cmd7; + volatile rtc_i2c_cmd8_reg_t i2c_cmd8; + volatile rtc_i2c_cmd9_reg_t i2c_cmd9; + volatile rtc_i2c_cmd10_reg_t i2c_cmd10; + volatile rtc_i2c_cmd11_reg_t i2c_cmd11; + volatile rtc_i2c_cmd12_reg_t i2c_cmd12; + volatile rtc_i2c_cmd13_reg_t i2c_cmd13; + volatile rtc_i2c_cmd14_reg_t i2c_cmd14; + volatile rtc_i2c_cmd15_reg_t i2c_cmd15; + uint32_t reserved_078[33]; + volatile rtc_i2c_date_reg_t i2c_date; +} rtc_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(rtc_dev_t) == 0x100, "Invalid size of rtc_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_RTC_I2C_STRUCT_H_ */ diff --git a/docs/en/api-reference/peripherals/i2c.rst b/docs/en/api-reference/peripherals/i2c.rst index 3a647e6fa3..7e6022b37b 100644 --- a/docs/en/api-reference/peripherals/i2c.rst +++ b/docs/en/api-reference/peripherals/i2c.rst @@ -148,6 +148,25 @@ When :cpp:member:`i2c_config_t::clk_flags` is 0, the clock allocator will select 1. :c:macro:`I2C_SCLK_SRC_FLAG_AWARE_DFS`: Clock's baud rate will not change while APB clock is changing. 2. :c:macro:`I2C_SCLK_SRC_FLAG_LIGHT_SLEEP`: It supports Light-sleep mode, which APB clock cannot do. +.. only:: esp32s3 + + .. list-table:: Characteristics of {IDF_TARGET_NAME} clock sources + :widths: 5 5 50 20 + :header-rows: 1 + + * - Clock name + - Clock frequency + - MAX freq for SCL + - Clock capabilities + * - XTAL clock + - 40 MHz + - 2 MHz + - / + * - RTC clock + - 20 MHz + - 1 MHz + - :c:macro:`I2C_SCLK_SRC_FLAG_AWARE_DFS`, :c:macro:`I2C_SCLK_SRC_FLAG_LIGHT_SLEEP` + .. only:: esp32c3 .. list-table:: Characteristics of {IDF_TARGET_NAME} clock sources diff --git a/examples/peripherals/i2c/i2c_self_test/README.md b/examples/peripherals/i2c/i2c_self_test/README.md index d51fa8d365..d9b3b440e6 100644 --- a/examples/peripherals/i2c/i2c_self_test/README.md +++ b/examples/peripherals/i2c/i2c_self_test/README.md @@ -19,7 +19,7 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE #### Pin Assignment(esp32, esp32s2): -**Note:** The following pin assignments are used by default, yout can change these in the `menuconfig` . +**Note:** The following pin assignments are used by default, you can change these in the `menuconfig` . | | SDA | SCL | | ------------------------- | ------ | ------ | @@ -41,6 +41,30 @@ To run this example, you should have one ESP development board (e.g. ESP32-WROVE **Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors. +#### Pin Assignment(esp32s3): + +**Note:** The following pin assignments are used by default, you can change these in the `menuconfig` . + +| | SDA | SCL | +| ------------------------- | ------ | ------ | +| ESP32-S3 I2C Master | GPIO1 | GPIO2 | +| ESP32-S3 I2C Slave | GPIO4 | GPIO5 | +| BH1750 Sensor | SDA | SCL | + +- slave: + - GPIO4 is assigned as the data signal of I2C slave port + - GPIO5 is assigned as the clock signal of I2C slave port +- master: + - GPIO1 is assigned as the data signal of I2C master port + - GPIO2 is assigned as the clock signal of I2C master port + +- Connection: + - connect GPIO1 with GPIO4 + - connect GPIO2 with GPIO5 + - connect SDA/SCL of BH1750 sensor with GPIO18/GPIO19 + +**Note:** It is recommended to add external pull-up resistors for SDA/SCL pins to make the communication more stable, though the driver will enable internal pull-up resistors. + #### Pin Assignment(esp32c3): **Note:** The following pin assignments are used by default, you can change these in the `menuconfig` . diff --git a/examples/peripherals/i2c/i2c_self_test/main/Kconfig.projbuild b/examples/peripherals/i2c/i2c_self_test/main/Kconfig.projbuild index 48b6e4e65c..2dccfd9e65 100644 --- a/examples/peripherals/i2c/i2c_self_test/main/Kconfig.projbuild +++ b/examples/peripherals/i2c/i2c_self_test/main/Kconfig.projbuild @@ -4,14 +4,16 @@ menu "Example Configuration" config I2C_MASTER_SCL int "SCL GPIO Num" default 6 if IDF_TARGET_ESP32C3 - default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 + default 2 if IDF_TARGET_ESP32S3 + default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 help GPIO number for I2C Master clock line. config I2C_MASTER_SDA int "SDA GPIO Num" default 5 if IDF_TARGET_ESP32C3 - default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 + default 1 if IDF_TARGET_ESP32S3 + default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 help GPIO number for I2C Master data line. diff --git a/examples/peripherals/i2c/i2c_tools/README.md b/examples/peripherals/i2c/i2c_tools/README.md index 2fc7ee285c..71176acfe2 100644 --- a/examples/peripherals/i2c/i2c_tools/README.md +++ b/examples/peripherals/i2c/i2c_tools/README.md @@ -18,16 +18,19 @@ If you have some trouble in developing I2C related applications, or just want to ### Hardware Required -To run this example, you should have one ESP32 dev board (e.g. ESP32-WROVER Kit) or ESP32 core board (e.g. ESP32-DevKitC). For test purpose, you should have a kind of device with I2C interface as well. Here we will take the CCS811 sensor as an example to show how to test the function of this sensor without writing any code (just use the command-line tools supported by this example). For more information about CCS811, you can consult the [online datasheet](http://ams.com/ccs811). +To run this example, you should have any ESP32, ESP32-S and ESP32-C based development board. For test purpose, you should have a kind of device with I2C interface as well. Here we will take the CCS811 sensor as an example to show how to test the function of this sensor without writing any code (just use the command-line tools supported by this example). For more information about CCS811, you can consult the [online datasheet](http://ams.com/ccs811). #### Pin Assignment: **Note:** The following pin assignments are used by default, you can change them with `i2cconfig` command at any time. -| | SDA | SCL | GND | Other | VCC | -| ---------------- | ------ | ------ | ---- | ----- | ---- | -| ESP32 I2C Master | GPIO18 | GPIO19 | GND | GND | 3.3V | -| Sensor | SDA | SCL | GND | WAK | VCC | +| | SDA | SCL | GND | Other | VCC | +| ------------------- | ------ | ------ | ---- | ----- | ---- | +| ESP32 I2C Master | GPIO18 | GPIO19 | GND | GND | 3.3V | +| ESP32-S2 I2C Master | GPIO18 | GPIO19 | GND | GND | 3.3V | +| ESP32-S3 I2C Master | GPIO1 | GPIO2 | GND | GND | 3.3V | +| ESP32-C3 I2C Master | GPIO5 | GPIO6 | GND | GND | 3.3V | +| Sensor | SDA | SCL | GND | WAK | VCC | **Note: ** There’s no need to add an external pull-up resistors for SDA/SCL pin, because the driver will enable the internal pull-up resistors itself. diff --git a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c index 5a6148e3f1..75b80b59ea 100644 --- a/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c +++ b/examples/peripherals/i2c/i2c_tools/main/cmd_i2ctools.c @@ -23,8 +23,17 @@ static const char *TAG = "cmd_i2ctools"; +#if CONFIG_IDF_TARGET_ESP32S3 +static gpio_num_t i2c_gpio_sda = 1; +static gpio_num_t i2c_gpio_scl = 2; +#elif CONFIG_IDF_TARGET_ESP32C3 +static gpio_num_t i2c_gpio_sda = 5; +static gpio_num_t i2c_gpio_scl = 6; +#else static gpio_num_t i2c_gpio_sda = 18; static gpio_num_t i2c_gpio_scl = 19; +#endif + static uint32_t i2c_frequency = 100000; static i2c_port_t i2c_port = I2C_NUM_0;