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Code Issues Actions 2 Packages Projects Releases Wiki Activity

soc: remove unused DR_REG_DPORT_END macro for c2/c3/s2/s3

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jingli 2022-09-07 15:35:47 +08:00
parent 18fef64089
commit 54046ee4bf
4 changed files with 0 additions and 4 deletions
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1
components/soc/esp32c2/include/soc/reg_base.h
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@ -14,7 +14,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000

1
components/soc/esp32c3/include/soc/reg_base.h
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@ -17,7 +17,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
#define DR_REG_DPORT_END 0x600d3FFC
#define DR_REG_UART_BASE 0x60000000
#define DR_REG_SPI1_BASE 0x60002000
#define DR_REG_SPI0_BASE 0x60003000

1
components/soc/esp32s2/include/soc/reg_base.h
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@ -20,7 +20,6 @@
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000

1
components/soc/esp32s3/include/soc/soc.h
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@ -25,7 +25,6 @@
#define DR_REG_ITAG_TABLE 0x600C6000
#define DR_REG_DTAG_TABLE 0x600C8000
#define DR_REG_EXT_MEM_ENC 0x600CC000
#define DR_REG_DPORT_END 0x600D3FFC
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)