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fix(cache): fixed cache writeback/invalidate cannot reach higher vaddr parts

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This commit is contained in:
Armando 2024-09-03 14:17:14 +08:00
parent fce2680e91
commit 5316a36175
6 changed files with 110 additions and 2 deletions
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4
components/esp_rom/CMakeLists.txt
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@ -67,6 +67,10 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC
list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
endif()
if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE)
list(APPEND sources "patches/esp_rom_cache_esp32c61.c")
endif()
if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
endif()

4
components/esp_rom/esp32c61/Kconfig.soc_caps.in
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@ -102,3 +102,7 @@ config ESP_ROM_USB_OTG_NUM
config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
bool
default y
config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE
bool
default y

1
components/esp_rom/esp32c61/esp_rom_caps.h
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@ -31,3 +31,4 @@
#define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions
#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts

4
components/esp_rom/esp32c61/ld/esp32c61.rom.ld
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@ -192,9 +192,9 @@ MMU_Set_Page_Mode = 0x40000624;
MMU_Get_Page_Mode = 0x40000628;
Cache_Sync_Items = 0x4000062c;
Cache_Op_Addr = 0x40000630;
Cache_Invalidate_Addr = 0x40000634;
/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_Clean_Addr = 0x40000638;
Cache_WriteBack_Addr = 0x4000063c;
/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */
Cache_WriteBack_Invalidate_Addr = 0x40000640;
Cache_Invalidate_All = 0x40000644;
Cache_Clean_All = 0x40000648;

2
components/esp_rom/linker.lf
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@ -8,6 +8,8 @@ entries:
esp_rom_cache_esp32s2_esp32s3 (noflash)
if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y:
esp_rom_cache_writeback_esp32s3 (noflash)
if ESP_ROM_CACHE_WB_INVLD_LOW_RANGE = y:
esp_rom_cache_esp32c61 (noflash)
if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y):
esp_rom_tlsf (noflash)
if SOC_SYSTIMER_SUPPORTED = y:

97
components/esp_rom/patches/esp_rom_cache_esp32c61.c Normal file
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@ -0,0 +1,97 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_rom_caps.h"
#include "soc/soc_caps.h"
#include "soc/cache_reg.h"
#include "soc/cache_struct.h"
#include "soc/ext_mem_defs.h"
#include "hal/assert.h"
#include "esp32c61/rom/cache.h"
#include "esp_rom_sys.h"
#define CACHE_MAX_SYNC_NUM ((CACHE_SYNC_SIZE + 1) >> 1)
/**
* @brief Sync Cache items
*
* @param type sync type
* @param addr address
* @param bytes bytes to be synced
*/
__attribute__((always_inline))
static inline void s_cache_sync_items(uint32_t type, uint32_t addr, uint32_t bytes)
{
REG_WRITE(CACHE_SYNC_ADDR_REG, addr);
REG_SET_FIELD(CACHE_SYNC_SIZE_REG, CACHE_SYNC_SIZE, bytes);
REG_SET_BIT(CACHE_SYNC_CTRL_REG, type);
while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE))
;
}
int Cache_Invalidate_Addr(uint32_t vaddr, uint32_t size)
{
uint32_t plus = 0;
uint32_t cache_line_size = 32;
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
if (size == 0) {
HAL_ASSERT(false);
}
//aligned start address to cache line size
plus = vaddr & (cache_line_size - 1);
vaddr -= plus;
//make the length fit the start address
size += plus;
//aligned the length to cache line size(0->0)
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
while (size > 0) {
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
if (this_size > size) {
this_size = size;
}
s_cache_sync_items(CACHE_SYNC_INVALIDATE, vaddr, this_size);
vaddr += this_size;
size -= this_size;
}
return 0;
}
int Cache_WriteBack_Addr(uint32_t vaddr, uint32_t size)
{
uint32_t plus = 0;
uint32_t cache_line_size = 32;
uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM;
if (size == 0) {
HAL_ASSERT(false);
}
//aligned start address to cache line size
plus = vaddr & (cache_line_size - 1);
vaddr -= plus;
//make the length fit the start address
size += plus;
//aligned the length to cache line size(0->0)
size = (size + cache_line_size - 1) & ~(cache_line_size - 1);
while (size > 0) {
//aligned to cache_max_sync_size, (0->cache_max_sync_size)
uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr;
if (this_size > size) {
this_size = size;
}
s_cache_sync_items(CACHE_SYNC_WRITEBACK, vaddr, this_size);
vaddr += this_size;
size -= this_size;
}
return 0;
}