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https://github.com/espressif/esp-idf.git
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esp_common: move configs
This commit is contained in:
Renz Bagaporo
parent
03dce3668c
commit
51e66d0f82
@ -9,204 +9,6 @@ menu "Common ESP-related"
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save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
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save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
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representations.
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representations.
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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config ESP_IPC_TASK_STACK_SIZE
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int "Inter-Processor Call (IPC) task stack size"
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range 512 65536 if !APPTRACE_ENABLE
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range 2048 65536 if APPTRACE_ENABLE
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default 2048 if APPTRACE_ENABLE
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default 1024
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help
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Configure the IPC tasks stack size. One IPC task runs on each core
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(in dual core mode), and allows for cross-core function calls.
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See IPC documentation for more details.
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The default stack size should be enough for most common use cases.
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It can be shrunk if you are sure that you do not use any custom
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IPC functionality.
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config ESP_IPC_USES_CALLERS_PRIORITY
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bool "IPC runs at caller's priority"
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default y
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depends on !FREERTOS_UNICORE
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help
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If this option is not enabled then the IPC task will keep behavior
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same as prior to that of ESP-IDF v4.0, and hence IPC task will run
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at (configMAX_PRIORITIES - 1) priority.
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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choice ESP_CONSOLE_UART
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prompt "Channel for console output"
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default ESP_CONSOLE_UART_DEFAULT
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help
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Select where to send console output (through stdout and stderr).
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- Default is to use UART0 on pre-defined GPIOs.
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This ROM output can be suppressed by
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GPIO strapping or EFUSE, refer to chip datasheet for details.
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- On chips with USB peripheral, "USB CDC" option redirects output to the
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CDC port. This option uses the CDC driver in the chip ROM.
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This option is incompatible with TinyUSB stack.
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config ESP_CONSOLE_UART_DEFAULT
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bool "Default: UART0"
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config ESP_CONSOLE_USB_CDC
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bool "USB CDC"
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# The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
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# && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
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depends on IDF_TARGET_ESP32S2 && !USB_ENABLED
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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bool "None"
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endchoice
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# Internal option, indicates that console UART is used (and not USB, for example)
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config ESP_CONSOLE_UART
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bool
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default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
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config ESP_CONSOLE_MULTIPLE_UART
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bool
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default y if !IDF_TARGET_ESP32C3
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choice ESP_CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
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default ESP_CONSOLE_UART_CUSTOM_NUM_0
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help
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This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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Due to an ESP32 ROM bug, UART2 is not supported for console output
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via esp_rom_printf.
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config ESP_CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config ESP_CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
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config ESP_CONSOLE_UART_NUM
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int
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default 0 if ESP_CONSOLE_UART_DEFAULT
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default 0 if !ESP_CONSOLE_MULTIPLE_UART
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default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
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default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
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default -1 if !ESP_CONSOLE_UART
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config ESP_CONSOLE_UART_TX_GPIO
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int "UART TX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 1 if IDF_TARGET_ESP32
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default 21 if IDF_TARGET_ESP32C3
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default 43
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help
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This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
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boot log output and default standard output and standard error of the app).
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_RX_GPIO
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int "UART RX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 3 if IDF_TARGET_ESP32
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default 20 if IDF_TARGET_ESP32C3
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default 44
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help
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This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
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default default standard input of the app).
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Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_BAUDRATE
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int
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prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
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depends on ESP_CONSOLE_UART
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default 115200
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range 1200 4000000 if !PM_ENABLE
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range 1200 1000000 if PM_ENABLE
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help
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This baud rate is used by both the ESP-IDF Bootloader and the app (including
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boot log output and default standard input/output/error of the app).
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The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
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the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
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accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
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from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
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accurate.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
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int "Size of USB CDC RX buffer"
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depends on ESP_CONSOLE_USB_CDC
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default 64
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range 4 16384
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help
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Set the size of USB CDC RX buffer. Increase the buffer size if your application
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is often receiving data over USB CDC.
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config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
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bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
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depends on ESP_CONSOLE_USB_CDC
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default n
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help
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If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
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Disabling this option saves about 1kB or RAM.
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config ESP_PANIC_HANDLER_IRAM
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bool "Place panic handler code in IRAM"
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default n
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help
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If this option is disabled (default), the panic handler code is placed in flash not IRAM.
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This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
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automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
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risk, if the flash cache status is also corrupted during the crash.
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If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
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handler to run without needing to re-enable cache first. This may be necessary to debug some
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complex issues with crashes while flash cache is disabled (for example, when writing to
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SPI flash.)
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config ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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config ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY
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# Invisible option that is set by SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY, but
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# Invisible option that is set by SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY, but
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# exists even if SPIRAM is not supported
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# exists even if SPIRAM is not supported
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@ -1,20 +0,0 @@
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# sdkconfig replacement configurations for deprecated options formatted as
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# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION
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CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
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CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
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CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
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CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
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CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
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CONFIG_CONSOLE_UART_CUSTOM CONFIG_ESP_CONSOLE_UART_CUSTOM
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CONFIG_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE
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CONFIG_ESP_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE
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CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
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CONFIG_CONSOLE_UART_CUSTOM_NUM_0 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0
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CONFIG_CONSOLE_UART_CUSTOM_NUM_1 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1
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CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO
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CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO
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CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
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CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
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@ -1,3 +1,4 @@
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menu "ESP System Settings"
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menu "ESP System Settings"
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choice ESP_SYSTEM_PANIC
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choice ESP_SYSTEM_PANIC
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@ -122,6 +123,165 @@ menu "ESP System Settings"
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endmenu # Memory protection
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endmenu # Memory protection
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config ESP_SYSTEM_EVENT_QUEUE_SIZE
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int "System event queue size"
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default 32
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help
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Config system event queue size in different application.
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config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
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int "Event loop task stack size"
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default 2304
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help
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Config system event task stack size in different application.
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config ESP_MAIN_TASK_STACK_SIZE
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int "Main task stack size"
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default 3584
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help
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Configure the "main task" stack size. This is the stack of the task
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which calls app_main(). If app_main() returns then this task is deleted
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and its stack memory is freed.
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config ESP_MINIMAL_SHARED_STACK_SIZE
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int "Minimal allowed size for shared stack"
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default 2048
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help
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Minimal value of size, in bytes, accepted to execute a expression
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with shared stack.
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choice ESP_CONSOLE_UART
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prompt "Channel for console output"
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default ESP_CONSOLE_UART_DEFAULT
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help
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Select where to send console output (through stdout and stderr).
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- Default is to use UART0 on pre-defined GPIOs.
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- If "Custom" is selected, UART0 or UART1 can be chosen,
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and any pins can be selected.
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- If "None" is selected, there will be no console output on any UART, except
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for initial output from ROM bootloader. This ROM output can be suppressed by
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GPIO strapping or EFUSE, refer to chip datasheet for details.
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- On chips with USB peripheral, "USB CDC" option redirects output to the
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CDC port. This option uses the CDC driver in the chip ROM.
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This option is incompatible with TinyUSB stack.
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config ESP_CONSOLE_UART_DEFAULT
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bool "Default: UART0"
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config ESP_CONSOLE_USB_CDC
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bool "USB CDC"
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# The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
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# && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
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depends on IDF_TARGET_ESP32S2 && !USB_ENABLED
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config ESP_CONSOLE_UART_CUSTOM
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bool "Custom UART"
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config ESP_CONSOLE_NONE
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bool "None"
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endchoice
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# Internal option, indicates that console UART is used (and not USB, for example)
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config ESP_CONSOLE_UART
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bool
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default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
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config ESP_CONSOLE_MULTIPLE_UART
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bool
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default y if !IDF_TARGET_ESP32C3
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choice ESP_CONSOLE_UART_NUM
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prompt "UART peripheral to use for console output (0-1)"
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depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
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default ESP_CONSOLE_UART_CUSTOM_NUM_0
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help
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This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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Due to an ESP32 ROM bug, UART2 is not supported for console output
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via esp_rom_printf.
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config ESP_CONSOLE_UART_CUSTOM_NUM_0
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bool "UART0"
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config ESP_CONSOLE_UART_CUSTOM_NUM_1
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bool "UART1"
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endchoice
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config ESP_CONSOLE_UART_NUM
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int
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default 0 if ESP_CONSOLE_UART_DEFAULT
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default 0 if !ESP_CONSOLE_MULTIPLE_UART
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default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
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default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
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default -1 if !ESP_CONSOLE_UART
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config ESP_CONSOLE_UART_TX_GPIO
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int "UART TX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 1 if IDF_TARGET_ESP32
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default 21 if IDF_TARGET_ESP32C3
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default 43
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help
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This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
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boot log output and default standard output and standard error of the app).
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If the configuration is different in the Bootloader binary compared to the app binary, UART
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is reconfigured after the bootloader exits and the app starts.
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config ESP_CONSOLE_UART_RX_GPIO
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int "UART RX on GPIO#"
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depends on ESP_CONSOLE_UART_CUSTOM
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range 0 46
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default 3 if IDF_TARGET_ESP32
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default 20 if IDF_TARGET_ESP32C3
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default 44
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help
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This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
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default default standard input of the app).
|
||||||
|
|
||||||
|
Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
|
||||||
|
|
||||||
|
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
||||||
|
is reconfigured after the bootloader exits and the app starts.
|
||||||
|
|
||||||
|
|
||||||
|
config ESP_CONSOLE_UART_BAUDRATE
|
||||||
|
int
|
||||||
|
prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
|
||||||
|
depends on ESP_CONSOLE_UART
|
||||||
|
default 115200
|
||||||
|
range 1200 4000000 if !PM_ENABLE
|
||||||
|
range 1200 1000000 if PM_ENABLE
|
||||||
|
help
|
||||||
|
This baud rate is used by both the ESP-IDF Bootloader and the app (including
|
||||||
|
boot log output and default standard input/output/error of the app).
|
||||||
|
|
||||||
|
The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
|
||||||
|
the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
|
||||||
|
accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
|
||||||
|
from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
|
||||||
|
accurate.
|
||||||
|
|
||||||
|
If the configuration is different in the Bootloader binary compared to the app binary, UART
|
||||||
|
is reconfigured after the bootloader exits and the app starts.
|
||||||
|
|
||||||
|
config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
|
||||||
|
int "Size of USB CDC RX buffer"
|
||||||
|
depends on ESP_CONSOLE_USB_CDC
|
||||||
|
default 64
|
||||||
|
range 4 16384
|
||||||
|
help
|
||||||
|
Set the size of USB CDC RX buffer. Increase the buffer size if your application
|
||||||
|
is often receiving data over USB CDC.
|
||||||
|
|
||||||
|
config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
|
||||||
|
bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
|
||||||
|
depends on ESP_CONSOLE_USB_CDC
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
|
||||||
|
Disabling this option saves about 1kB or RAM.
|
||||||
|
|
||||||
config ESP_INT_WDT
|
config ESP_INT_WDT
|
||||||
bool "Interrupt watchdog"
|
bool "Interrupt watchdog"
|
||||||
default y
|
default y
|
||||||
@ -192,6 +352,46 @@ menu "ESP System Settings"
|
|||||||
help
|
help
|
||||||
If this option is enabled, the Task Wtachdog Timer will wach the CPU1
|
If this option is enabled, the Task Wtachdog Timer will wach the CPU1
|
||||||
Idle Task.
|
Idle Task.
|
||||||
|
|
||||||
|
config ESP_IPC_TASK_STACK_SIZE
|
||||||
|
int "Inter-Processor Call (IPC) task stack size"
|
||||||
|
range 512 65536 if !APPTRACE_ENABLE
|
||||||
|
range 2048 65536 if APPTRACE_ENABLE
|
||||||
|
default 2048 if APPTRACE_ENABLE
|
||||||
|
default 1024
|
||||||
|
help
|
||||||
|
Configure the IPC tasks stack size. One IPC task runs on each core
|
||||||
|
(in dual core mode), and allows for cross-core function calls.
|
||||||
|
|
||||||
|
See IPC documentation for more details.
|
||||||
|
|
||||||
|
The default stack size should be enough for most common use cases.
|
||||||
|
It can be shrunk if you are sure that you do not use any custom
|
||||||
|
IPC functionality.
|
||||||
|
|
||||||
|
config ESP_IPC_USES_CALLERS_PRIORITY
|
||||||
|
bool "IPC runs at caller's priority"
|
||||||
|
default y
|
||||||
|
depends on !FREERTOS_UNICORE
|
||||||
|
help
|
||||||
|
If this option is not enabled then the IPC task will keep behavior
|
||||||
|
same as prior to that of ESP-IDF v4.0, and hence IPC task will run
|
||||||
|
at (configMAX_PRIORITIES - 1) priority.
|
||||||
|
|
||||||
|
config ESP_PANIC_HANDLER_IRAM
|
||||||
|
bool "Place panic handler code in IRAM"
|
||||||
|
default n
|
||||||
|
help
|
||||||
|
If this option is disabled (default), the panic handler code is placed in flash not IRAM.
|
||||||
|
This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
|
||||||
|
automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
|
||||||
|
risk, if the flash cache status is also corrupted during the crash.
|
||||||
|
|
||||||
|
If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
|
||||||
|
handler to run without needing to re-enable cache first. This may be necessary to debug some
|
||||||
|
complex issues with crashes while flash cache is disabled (for example, when writing to
|
||||||
|
SPI flash.)
|
||||||
|
|
||||||
config ESP_DEBUG_STUBS_ENABLE
|
config ESP_DEBUG_STUBS_ENABLE
|
||||||
bool
|
bool
|
||||||
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
|
default COMPILER_OPTIMIZATION_LEVEL_DEBUG
|
||||||
|
|||||||
@ -21,8 +21,6 @@
|
|||||||
#include "esp_private/usb_console.h"
|
#include "esp_private/usb_console.h"
|
||||||
#include "esp_ota_ops.h"
|
#include "esp_ota_ops.h"
|
||||||
|
|
||||||
#include "esp_core_dump.h"
|
|
||||||
|
|
||||||
#include "soc/cpu.h"
|
#include "soc/cpu.h"
|
||||||
#include "soc/rtc.h"
|
#include "soc/rtc.h"
|
||||||
#include "hal/timer_hal.h"
|
#include "hal/timer_hal.h"
|
||||||
@ -35,7 +33,7 @@
|
|||||||
|
|
||||||
#include "sdkconfig.h"
|
#include "sdkconfig.h"
|
||||||
|
|
||||||
#if CONFIG_ESP32_ENABLE_COREDUMP
|
#if CONFIG_ESP_COREDUMP_ENABLE
|
||||||
#include "esp_core_dump.h"
|
#include "esp_core_dump.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
@ -16,6 +16,22 @@ CONFIG_ESP32C3_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPRO
|
|||||||
CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
|
CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
|
||||||
|
|
||||||
CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
|
CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
|
||||||
|
|
||||||
|
CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE
|
||||||
|
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE
|
||||||
|
CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE
|
||||||
|
CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE
|
||||||
|
CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART
|
||||||
|
CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT
|
||||||
|
CONFIG_CONSOLE_UART_CUSTOM CONFIG_ESP_CONSOLE_UART_CUSTOM
|
||||||
|
CONFIG_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE
|
||||||
|
CONFIG_ESP_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE
|
||||||
|
CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM
|
||||||
|
CONFIG_CONSOLE_UART_CUSTOM_NUM_0 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0
|
||||||
|
CONFIG_CONSOLE_UART_CUSTOM_NUM_1 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1
|
||||||
|
CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO
|
||||||
|
CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO
|
||||||
|
CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE
|
||||||
CONFIG_INT_WDT CONFIG_ESP_INT_WDT
|
CONFIG_INT_WDT CONFIG_ESP_INT_WDT
|
||||||
CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
|
CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS
|
||||||
CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
|
CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1
|
||||||
@ -25,3 +41,5 @@ CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIME
|
|||||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
|
||||||
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
|
||||||
CONFIG_ESP32_DEBUG_STUBS_ENABLE CONFIG_ESP_DEBUG_STUBS_ENABLE
|
CONFIG_ESP32_DEBUG_STUBS_ENABLE CONFIG_ESP_DEBUG_STUBS_ENABLE
|
||||||
|
CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||||
|
CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||||
|
|||||||
@ -45,7 +45,11 @@
|
|||||||
#include "nvs_flash.h"
|
#include "nvs_flash.h"
|
||||||
#include "esp_phy_init.h"
|
#include "esp_phy_init.h"
|
||||||
#include "esp_coexist_internal.h"
|
#include "esp_coexist_internal.h"
|
||||||
|
|
||||||
|
#if CONFIG_ESP_COREDUMP_ENABLE
|
||||||
#include "esp_core_dump.h"
|
#include "esp_core_dump.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
#include "esp_app_trace.h"
|
#include "esp_app_trace.h"
|
||||||
#include "esp_private/dbg_stubs.h"
|
#include "esp_private/dbg_stubs.h"
|
||||||
#include "esp_flash_encrypt.h"
|
#include "esp_flash_encrypt.h"
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user