From 51e66d0f8247fd8314458f8e209a93cb12823cf4 Mon Sep 17 00:00:00 2001 From: Renz Bagaporo Date: Tue, 26 Jan 2021 13:03:14 +0800 Subject: [PATCH] esp_common: move configs --- components/esp_common/Kconfig | 198 ------------------------ components/esp_common/sdkconfig.rename | 20 --- components/esp_system/Kconfig | 200 +++++++++++++++++++++++++ components/esp_system/panic.c | 4 +- components/esp_system/sdkconfig.rename | 18 +++ components/esp_system/startup.c | 4 + 6 files changed, 223 insertions(+), 221 deletions(-) delete mode 100644 components/esp_common/sdkconfig.rename diff --git a/components/esp_common/Kconfig b/components/esp_common/Kconfig index 0e4fdd4a46..43a74a4544 100644 --- a/components/esp_common/Kconfig +++ b/components/esp_common/Kconfig @@ -9,204 +9,6 @@ menu "Common ESP-related" save memory but this comes at the price of sacrificing distinguishable (meaningful) output string representations. - config ESP_SYSTEM_EVENT_QUEUE_SIZE - int "System event queue size" - default 32 - help - Config system event queue size in different application. - - config ESP_SYSTEM_EVENT_TASK_STACK_SIZE - int "Event loop task stack size" - default 2304 - help - Config system event task stack size in different application. - - config ESP_MAIN_TASK_STACK_SIZE - int "Main task stack size" - default 3584 - help - Configure the "main task" stack size. This is the stack of the task - which calls app_main(). If app_main() returns then this task is deleted - and its stack memory is freed. - - config ESP_IPC_TASK_STACK_SIZE - int "Inter-Processor Call (IPC) task stack size" - range 512 65536 if !APPTRACE_ENABLE - range 2048 65536 if APPTRACE_ENABLE - default 2048 if APPTRACE_ENABLE - default 1024 - help - Configure the IPC tasks stack size. One IPC task runs on each core - (in dual core mode), and allows for cross-core function calls. - - See IPC documentation for more details. - - The default stack size should be enough for most common use cases. - It can be shrunk if you are sure that you do not use any custom - IPC functionality. - - config ESP_IPC_USES_CALLERS_PRIORITY - bool "IPC runs at caller's priority" - default y - depends on !FREERTOS_UNICORE - help - If this option is not enabled then the IPC task will keep behavior - same as prior to that of ESP-IDF v4.0, and hence IPC task will run - at (configMAX_PRIORITIES - 1) priority. - - config ESP_MINIMAL_SHARED_STACK_SIZE - int "Minimal allowed size for shared stack" - default 2048 - help - Minimal value of size, in bytes, accepted to execute a expression - with shared stack. - - choice ESP_CONSOLE_UART - prompt "Channel for console output" - default ESP_CONSOLE_UART_DEFAULT - help - Select where to send console output (through stdout and stderr). - - - Default is to use UART0 on pre-defined GPIOs. - - If "Custom" is selected, UART0 or UART1 can be chosen, - and any pins can be selected. - - If "None" is selected, there will be no console output on any UART, except - for initial output from ROM bootloader. This ROM output can be suppressed by - GPIO strapping or EFUSE, refer to chip datasheet for details. - - On chips with USB peripheral, "USB CDC" option redirects output to the - CDC port. This option uses the CDC driver in the chip ROM. - This option is incompatible with TinyUSB stack. - config ESP_CONSOLE_UART_DEFAULT - bool "Default: UART0" - config ESP_CONSOLE_USB_CDC - bool "USB CDC" - # The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general. - # && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB. - depends on IDF_TARGET_ESP32S2 && !USB_ENABLED - config ESP_CONSOLE_UART_CUSTOM - bool "Custom UART" - config ESP_CONSOLE_NONE - bool "None" - endchoice - - # Internal option, indicates that console UART is used (and not USB, for example) - config ESP_CONSOLE_UART - bool - default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM - - config ESP_CONSOLE_MULTIPLE_UART - bool - default y if !IDF_TARGET_ESP32C3 - - choice ESP_CONSOLE_UART_NUM - prompt "UART peripheral to use for console output (0-1)" - depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART - default ESP_CONSOLE_UART_CUSTOM_NUM_0 - help - This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. - - If the configuration is different in the Bootloader binary compared to the app binary, UART - is reconfigured after the bootloader exits and the app starts. - - Due to an ESP32 ROM bug, UART2 is not supported for console output - via esp_rom_printf. - - config ESP_CONSOLE_UART_CUSTOM_NUM_0 - bool "UART0" - config ESP_CONSOLE_UART_CUSTOM_NUM_1 - bool "UART1" - endchoice - - config ESP_CONSOLE_UART_NUM - int - default 0 if ESP_CONSOLE_UART_DEFAULT - default 0 if !ESP_CONSOLE_MULTIPLE_UART - default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 - default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 - default -1 if !ESP_CONSOLE_UART - - config ESP_CONSOLE_UART_TX_GPIO - int "UART TX on GPIO#" - depends on ESP_CONSOLE_UART_CUSTOM - range 0 46 - default 1 if IDF_TARGET_ESP32 - default 21 if IDF_TARGET_ESP32C3 - default 43 - help - This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including - boot log output and default standard output and standard error of the app). - - If the configuration is different in the Bootloader binary compared to the app binary, UART - is reconfigured after the bootloader exits and the app starts. - - config ESP_CONSOLE_UART_RX_GPIO - int "UART RX on GPIO#" - depends on ESP_CONSOLE_UART_CUSTOM - range 0 46 - default 3 if IDF_TARGET_ESP32 - default 20 if IDF_TARGET_ESP32C3 - default 44 - help - This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including - default default standard input of the app). - - Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. - - If the configuration is different in the Bootloader binary compared to the app binary, UART - is reconfigured after the bootloader exits and the app starts. - - - config ESP_CONSOLE_UART_BAUDRATE - int - prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM - depends on ESP_CONSOLE_UART - default 115200 - range 1200 4000000 if !PM_ENABLE - range 1200 1000000 if PM_ENABLE - help - This baud rate is used by both the ESP-IDF Bootloader and the app (including - boot log output and default standard input/output/error of the app). - - The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, - the UART clock source is the APB clock and all baud rates in the available range will be sufficiently - accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided - from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be - accurate. - - If the configuration is different in the Bootloader binary compared to the app binary, UART - is reconfigured after the bootloader exits and the app starts. - - config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE - int "Size of USB CDC RX buffer" - depends on ESP_CONSOLE_USB_CDC - default 64 - range 4 16384 - help - Set the size of USB CDC RX buffer. Increase the buffer size if your application - is often receiving data over USB CDC. - - config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF - bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" - depends on ESP_CONSOLE_USB_CDC - default n - help - If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. - Disabling this option saves about 1kB or RAM. - - config ESP_PANIC_HANDLER_IRAM - bool "Place panic handler code in IRAM" - default n - help - If this option is disabled (default), the panic handler code is placed in flash not IRAM. - This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will - automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor - risk, if the flash cache status is also corrupted during the crash. - - If this option is enabled, the panic handler code is placed in IRAM. This allows the panic - handler to run without needing to re-enable cache first. This may be necessary to debug some - complex issues with crashes while flash cache is disabled (for example, when writing to - SPI flash.) - config ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY # Invisible option that is set by SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY, but # exists even if SPIRAM is not supported diff --git a/components/esp_common/sdkconfig.rename b/components/esp_common/sdkconfig.rename deleted file mode 100644 index 419f6206a5..0000000000 --- a/components/esp_common/sdkconfig.rename +++ /dev/null @@ -1,20 +0,0 @@ -# sdkconfig replacement configurations for deprecated options formatted as -# CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION - -CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE -CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE -CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE -CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE -CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART -CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT -CONFIG_CONSOLE_UART_CUSTOM CONFIG_ESP_CONSOLE_UART_CUSTOM -CONFIG_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE -CONFIG_ESP_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE -CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM -CONFIG_CONSOLE_UART_CUSTOM_NUM_0 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0 -CONFIG_CONSOLE_UART_CUSTOM_NUM_1 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1 -CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO -CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO -CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE -CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP -CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index c223e85e9e..486c8cde45 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -1,3 +1,4 @@ + menu "ESP System Settings" choice ESP_SYSTEM_PANIC @@ -122,6 +123,165 @@ menu "ESP System Settings" endmenu # Memory protection + config ESP_SYSTEM_EVENT_QUEUE_SIZE + int "System event queue size" + default 32 + help + Config system event queue size in different application. + + config ESP_SYSTEM_EVENT_TASK_STACK_SIZE + int "Event loop task stack size" + default 2304 + help + Config system event task stack size in different application. + + config ESP_MAIN_TASK_STACK_SIZE + int "Main task stack size" + default 3584 + help + Configure the "main task" stack size. This is the stack of the task + which calls app_main(). If app_main() returns then this task is deleted + and its stack memory is freed. + + config ESP_MINIMAL_SHARED_STACK_SIZE + int "Minimal allowed size for shared stack" + default 2048 + help + Minimal value of size, in bytes, accepted to execute a expression + with shared stack. + + choice ESP_CONSOLE_UART + prompt "Channel for console output" + default ESP_CONSOLE_UART_DEFAULT + help + Select where to send console output (through stdout and stderr). + + - Default is to use UART0 on pre-defined GPIOs. + - If "Custom" is selected, UART0 or UART1 can be chosen, + and any pins can be selected. + - If "None" is selected, there will be no console output on any UART, except + for initial output from ROM bootloader. This ROM output can be suppressed by + GPIO strapping or EFUSE, refer to chip datasheet for details. + - On chips with USB peripheral, "USB CDC" option redirects output to the + CDC port. This option uses the CDC driver in the chip ROM. + This option is incompatible with TinyUSB stack. + config ESP_CONSOLE_UART_DEFAULT + bool "Default: UART0" + config ESP_CONSOLE_USB_CDC + bool "USB CDC" + # The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general. + # && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB. + depends on IDF_TARGET_ESP32S2 && !USB_ENABLED + config ESP_CONSOLE_UART_CUSTOM + bool "Custom UART" + config ESP_CONSOLE_NONE + bool "None" + endchoice + + # Internal option, indicates that console UART is used (and not USB, for example) + config ESP_CONSOLE_UART + bool + default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM + + config ESP_CONSOLE_MULTIPLE_UART + bool + default y if !IDF_TARGET_ESP32C3 + + choice ESP_CONSOLE_UART_NUM + prompt "UART peripheral to use for console output (0-1)" + depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART + default ESP_CONSOLE_UART_CUSTOM_NUM_0 + help + This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. + + If the configuration is different in the Bootloader binary compared to the app binary, UART + is reconfigured after the bootloader exits and the app starts. + + Due to an ESP32 ROM bug, UART2 is not supported for console output + via esp_rom_printf. + + config ESP_CONSOLE_UART_CUSTOM_NUM_0 + bool "UART0" + config ESP_CONSOLE_UART_CUSTOM_NUM_1 + bool "UART1" + endchoice + + config ESP_CONSOLE_UART_NUM + int + default 0 if ESP_CONSOLE_UART_DEFAULT + default 0 if !ESP_CONSOLE_MULTIPLE_UART + default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 + default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 + default -1 if !ESP_CONSOLE_UART + + config ESP_CONSOLE_UART_TX_GPIO + int "UART TX on GPIO#" + depends on ESP_CONSOLE_UART_CUSTOM + range 0 46 + default 1 if IDF_TARGET_ESP32 + default 21 if IDF_TARGET_ESP32C3 + default 43 + help + This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including + boot log output and default standard output and standard error of the app). + + If the configuration is different in the Bootloader binary compared to the app binary, UART + is reconfigured after the bootloader exits and the app starts. + + config ESP_CONSOLE_UART_RX_GPIO + int "UART RX on GPIO#" + depends on ESP_CONSOLE_UART_CUSTOM + range 0 46 + default 3 if IDF_TARGET_ESP32 + default 20 if IDF_TARGET_ESP32C3 + default 44 + help + This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including + default default standard input of the app). + + Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. + + If the configuration is different in the Bootloader binary compared to the app binary, UART + is reconfigured after the bootloader exits and the app starts. + + + config ESP_CONSOLE_UART_BAUDRATE + int + prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM + depends on ESP_CONSOLE_UART + default 115200 + range 1200 4000000 if !PM_ENABLE + range 1200 1000000 if PM_ENABLE + help + This baud rate is used by both the ESP-IDF Bootloader and the app (including + boot log output and default standard input/output/error of the app). + + The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, + the UART clock source is the APB clock and all baud rates in the available range will be sufficiently + accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided + from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be + accurate. + + If the configuration is different in the Bootloader binary compared to the app binary, UART + is reconfigured after the bootloader exits and the app starts. + + config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE + int "Size of USB CDC RX buffer" + depends on ESP_CONSOLE_USB_CDC + default 64 + range 4 16384 + help + Set the size of USB CDC RX buffer. Increase the buffer size if your application + is often receiving data over USB CDC. + + config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF + bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" + depends on ESP_CONSOLE_USB_CDC + default n + help + If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. + Disabling this option saves about 1kB or RAM. + config ESP_INT_WDT bool "Interrupt watchdog" default y @@ -192,6 +352,46 @@ menu "ESP System Settings" help If this option is enabled, the Task Wtachdog Timer will wach the CPU1 Idle Task. + + config ESP_IPC_TASK_STACK_SIZE + int "Inter-Processor Call (IPC) task stack size" + range 512 65536 if !APPTRACE_ENABLE + range 2048 65536 if APPTRACE_ENABLE + default 2048 if APPTRACE_ENABLE + default 1024 + help + Configure the IPC tasks stack size. One IPC task runs on each core + (in dual core mode), and allows for cross-core function calls. + + See IPC documentation for more details. + + The default stack size should be enough for most common use cases. + It can be shrunk if you are sure that you do not use any custom + IPC functionality. + + config ESP_IPC_USES_CALLERS_PRIORITY + bool "IPC runs at caller's priority" + default y + depends on !FREERTOS_UNICORE + help + If this option is not enabled then the IPC task will keep behavior + same as prior to that of ESP-IDF v4.0, and hence IPC task will run + at (configMAX_PRIORITIES - 1) priority. + + config ESP_PANIC_HANDLER_IRAM + bool "Place panic handler code in IRAM" + default n + help + If this option is disabled (default), the panic handler code is placed in flash not IRAM. + This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will + automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor + risk, if the flash cache status is also corrupted during the crash. + + If this option is enabled, the panic handler code is placed in IRAM. This allows the panic + handler to run without needing to re-enable cache first. This may be necessary to debug some + complex issues with crashes while flash cache is disabled (for example, when writing to + SPI flash.) + config ESP_DEBUG_STUBS_ENABLE bool default COMPILER_OPTIMIZATION_LEVEL_DEBUG diff --git a/components/esp_system/panic.c b/components/esp_system/panic.c index 196e46ec6d..d35057ccb1 100644 --- a/components/esp_system/panic.c +++ b/components/esp_system/panic.c @@ -21,8 +21,6 @@ #include "esp_private/usb_console.h" #include "esp_ota_ops.h" -#include "esp_core_dump.h" - #include "soc/cpu.h" #include "soc/rtc.h" #include "hal/timer_hal.h" @@ -35,7 +33,7 @@ #include "sdkconfig.h" -#if CONFIG_ESP32_ENABLE_COREDUMP +#if CONFIG_ESP_COREDUMP_ENABLE #include "esp_core_dump.h" #endif diff --git a/components/esp_system/sdkconfig.rename b/components/esp_system/sdkconfig.rename index 5ff5eecc74..5d113edd17 100644 --- a/components/esp_system/sdkconfig.rename +++ b/components/esp_system/sdkconfig.rename @@ -16,6 +16,22 @@ CONFIG_ESP32C3_MEMPROT_FEATURE CONFIG_ESP_SYSTEM_MEMPRO CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES + +CONFIG_SYSTEM_EVENT_QUEUE_SIZE CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE +CONFIG_MAIN_TASK_STACK_SIZE CONFIG_ESP_MAIN_TASK_STACK_SIZE +CONFIG_IPC_TASK_STACK_SIZE CONFIG_ESP_IPC_TASK_STACK_SIZE +CONFIG_CONSOLE_UART CONFIG_ESP_CONSOLE_UART +CONFIG_CONSOLE_UART_DEFAULT CONFIG_ESP_CONSOLE_UART_DEFAULT +CONFIG_CONSOLE_UART_CUSTOM CONFIG_ESP_CONSOLE_UART_CUSTOM +CONFIG_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE +CONFIG_ESP_CONSOLE_UART_NONE CONFIG_ESP_CONSOLE_NONE +CONFIG_CONSOLE_UART_NUM CONFIG_ESP_CONSOLE_UART_NUM +CONFIG_CONSOLE_UART_CUSTOM_NUM_0 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_0 +CONFIG_CONSOLE_UART_CUSTOM_NUM_1 CONFIG_ESP_CONSOLE_UART_CUSTOM_NUM_1 +CONFIG_CONSOLE_UART_TX_GPIO CONFIG_ESP_CONSOLE_UART_TX_GPIO +CONFIG_CONSOLE_UART_RX_GPIO CONFIG_ESP_CONSOLE_UART_RX_GPIO +CONFIG_CONSOLE_UART_BAUDRATE CONFIG_ESP_CONSOLE_UART_BAUDRATE CONFIG_INT_WDT CONFIG_ESP_INT_WDT CONFIG_INT_WDT_TIMEOUT_MS CONFIG_ESP_INT_WDT_TIMEOUT_MS CONFIG_INT_WDT_CHECK_CPU1 CONFIG_ESP_INT_WDT_CHECK_CPU1 @@ -25,3 +41,5 @@ CONFIG_TASK_WDT_TIMEOUT_S CONFIG_ESP_TASK_WDT_TIME CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 CONFIG_ESP32_DEBUG_STUBS_ENABLE CONFIG_ESP_DEBUG_STUBS_ENABLE +CONFIG_ESP32_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP +CONFIG_ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index 3ad549d267..4527ffa48a 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -45,7 +45,11 @@ #include "nvs_flash.h" #include "esp_phy_init.h" #include "esp_coexist_internal.h" + +#if CONFIG_ESP_COREDUMP_ENABLE #include "esp_core_dump.h" +#endif + #include "esp_app_trace.h" #include "esp_private/dbg_stubs.h" #include "esp_flash_encrypt.h"