mirror of
https://github.com/espressif/esp-idf.git
synced 2024-09-20 00:36:01 -04:00
Merge branch 'feature/update_esp32c6_rom_20220919' into 'master'
esp32c6: update freeze rom and memory related Closes IDF-6022 See merge request espressif/esp-idf!20397
This commit is contained in:
Wu Zheng Hui
commit
511f1d7de4
@ -1,19 +1,45 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/** Simplified memory map for the bootloader.
|
||||
* Make sure the bootloader can load into main memory without overwriting itself.
|
||||
* We put 2nd bootloader in the high address space (before ROM stack/data/bss).
|
||||
* See memory usage for ROM bootloader at the end of this file.
|
||||
*
|
||||
* ESP32-C6 ROM static data usage is as follows:
|
||||
* - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
|
||||
* - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
|
||||
* - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
|
||||
*
|
||||
* The 2nd stage bootloader can take space up to the end of ROM shared
|
||||
* buffers area (0x4087c610).
|
||||
*/
|
||||
|
||||
/* The offset between Dbus and Ibus. Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. */
|
||||
iram_dram_offset = 0x0;
|
||||
|
||||
/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
|
||||
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
|
||||
*/
|
||||
|
||||
/* These lengths can be adjusted, if necessary: */
|
||||
bootloader_usable_dram_end = 0x4087c610;
|
||||
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
|
||||
bootloader_dram_seg_len = 0x5000;
|
||||
bootloader_iram_loader_seg_len = 0x7000;
|
||||
bootloader_iram_seg_len = 0x2000;
|
||||
|
||||
/* Start of the lower region is determined by region size and the end of the higher region */
|
||||
bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
|
||||
bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
|
||||
bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len + iram_dram_offset;
|
||||
bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
iram_seg (RWX) : org = 0x4086E000, len = 0x2000
|
||||
iram_loader_seg (RWX) : org = 0x40870000, len = 0x6000
|
||||
dram_seg (RW) : org = 0x40876000, len = 0x4000
|
||||
iram_seg (RWX) : org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
|
||||
iram_loader_seg (RWX) : org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
|
||||
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
|
||||
}
|
||||
|
||||
/* Default entry point: */
|
||||
@ -184,17 +210,34 @@ SECTIONS
|
||||
/**
|
||||
* Appendix: Memory Usage of ROM bootloader
|
||||
*
|
||||
* +--------+--------------+------+ 0x3FCC_AE00
|
||||
* | ^ |
|
||||
* | | |
|
||||
* | | data/bss |
|
||||
* | | |
|
||||
* | v |
|
||||
* +------------------------------+ 0x3FCD_C710
|
||||
* | ^ |
|
||||
* | | |
|
||||
* | | stack |
|
||||
* | | |
|
||||
* | v |
|
||||
* +------------------------------+ 0x3FCD_E710
|
||||
* 0x4086ad08 ------------------> _dram0_0_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
|
||||
* | |
|
||||
* | |
|
||||
* 0x4087c610 ------------------> __stack_sentry
|
||||
* | |
|
||||
* | | 2. Startup pro cpu stack (freed when IDF app is running)
|
||||
* | |
|
||||
* 0x4087e610 ------------------> __stack (pro cpu)
|
||||
* | |
|
||||
* | |
|
||||
* | | 3. Shared memory only used in startup code or nonos/early boot*
|
||||
* | | (can be freed when IDF runs)
|
||||
* | |
|
||||
* | |
|
||||
* 0x4087f564 ------------------> _dram0_rtos_reserved_start
|
||||
* | |
|
||||
* | |
|
||||
* | | 4. Shared memory used in startup code and when IDF runs
|
||||
* | |
|
||||
* | |
|
||||
* 0x4087fab0 ------------------> _dram0_rtos_reserved_end
|
||||
* | |
|
||||
* 0x4087fce8 ------------------> _data_start_interface
|
||||
* | |
|
||||
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
|
||||
* | |
|
||||
* 0x40880000 ------------------> _data_end_interface
|
||||
*/
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.coexist.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.heap.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
@ -44,7 +44,7 @@ multi_heap_get_block_address_impl = 0x40000454;
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||||
multi_heap_get_allocated_size_impl = 0x40000458;
|
||||
multi_heap_register_impl = 0x4000045c;
|
||||
multi_heap_set_lock = 0x40000460;
|
||||
multi_heap_os_funcs_init = 0x40000464;
|
||||
multi_heap_mutex_init = 0x40000464;
|
||||
multi_heap_internal_lock = 0x40000468;
|
||||
multi_heap_internal_unlock = 0x4000046c;
|
||||
multi_heap_get_first_block = 0x40000470;
|
||||
@ -76,5 +76,6 @@ PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
|
||||
PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
|
||||
PROVIDE (multi_heap_check = multi_heap_check);
|
||||
PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
|
||||
PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
|
||||
PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
|
||||
PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.libgcc.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.net80211.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
@ -50,9 +50,9 @@ ieee80211_search_node = 0x40000bbc;
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||||
ieee80211_crypto_encap = 0x40000bc0;
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||||
ieee80211_crypto_decap = 0x40000bc4;
|
||||
ieee80211_decap = 0x40000bc8;
|
||||
ieee80211_set_tx_pti = 0x40000bcc;
|
||||
wifi_is_started = 0x40000bd0;
|
||||
ieee80211_gettid = 0x40000bd4;
|
||||
wifi_is_started = 0x40000bcc;
|
||||
ieee80211_gettid = 0x40000bd0;
|
||||
ieee80211_encap_esfbuf_htc = 0x40000bd4;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
net80211_funcs = 0x4087ffac;
|
||||
g_scan = 0x4087ffa8;
|
||||
@ -63,3 +63,5 @@ g_tx_cacheq_ptr = 0x4087ff98;
|
||||
s_netstack_free = 0x4087ff94;
|
||||
mesh_rxcb = 0x4087ff90;
|
||||
sta_rxcb = 0x4087ff8c;
|
||||
g_itwt_fid = 0x4087ff88;
|
||||
esp_test_tx_addba_request = 0x4087ff84;
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.newlib-normal.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.newlib.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.phy.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
@ -18,179 +18,232 @@
|
||||
***************************************/
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||||
|
||||
/* Functions */
|
||||
phy_get_romfuncs = 0x40000e48;
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||||
rom_abs_temp = 0x40000e4c;
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||||
rom_bb_bss_cbw40_dig = 0x40000e50;
|
||||
rom_bb_wdg_test_en = 0x40000e54;
|
||||
rom_bb_wdt_get_status = 0x40000e58;
|
||||
rom_bb_wdt_int_enable = 0x40000e5c;
|
||||
rom_bb_wdt_rst_enable = 0x40000e60;
|
||||
rom_bb_wdt_timeout_clear = 0x40000e64;
|
||||
rom_cbw2040_cfg = 0x40000e68;
|
||||
rom_check_noise_floor = 0x40000e6c;
|
||||
rom_chip_i2c_readReg = 0x40000e70;
|
||||
rom_chip_i2c_writeReg = 0x40000e74;
|
||||
rom_correct_rf_ana_gain = 0x40000e78;
|
||||
rom_dc_iq_est = 0x40000e7c;
|
||||
rom_disable_agc = 0x40000e80;
|
||||
rom_en_pwdet = 0x40000e84;
|
||||
rom_enable_agc = 0x40000e88;
|
||||
rom_get_bbgain_db = 0x40000e8c;
|
||||
rom_get_data_sat = 0x40000e90;
|
||||
rom_get_i2c_read_mask = 0x40000e94;
|
||||
rom_get_pwctrl_correct = 0x40000e98;
|
||||
rom_get_rf_gain_qdb = 0x40000e9c;
|
||||
rom_i2c_readReg = 0x40000ea0;
|
||||
rom_i2c_readReg_Mask = 0x40000ea4;
|
||||
rom_i2c_writeReg = 0x40000ea8;
|
||||
rom_i2c_writeReg_Mask = 0x40000eac;
|
||||
rom_index_to_txbbgain = 0x40000eb0;
|
||||
rom_iq_est_disable = 0x40000eb4;
|
||||
rom_iq_est_enable = 0x40000eb8;
|
||||
rom_linear_to_db = 0x40000ebc;
|
||||
rom_loopback_mode_en = 0x40000ec0;
|
||||
rom_mhz2ieee = 0x40000ec4;
|
||||
rom_noise_floor_auto_set = 0x40000ec8;
|
||||
rom_pbus_debugmode = 0x40000ecc;
|
||||
rom_pbus_force_mode = 0x40000ed0;
|
||||
rom_pbus_force_test = 0x40000ed4;
|
||||
rom_pbus_rd = 0x40000ed8;
|
||||
rom_pbus_rd_addr = 0x40000edc;
|
||||
rom_pbus_rd_shift = 0x40000ee0;
|
||||
rom_pbus_set_dco = 0x40000ee4;
|
||||
rom_pbus_set_rxgain = 0x40000ee8;
|
||||
rom_pbus_workmode = 0x40000eec;
|
||||
rom_pbus_xpd_rx_off = 0x40000ef0;
|
||||
rom_pbus_xpd_rx_on = 0x40000ef4;
|
||||
rom_pbus_xpd_tx_off = 0x40000ef8;
|
||||
rom_pbus_xpd_tx_on = 0x40000efc;
|
||||
rom_phy_byte_to_word = 0x40000f00;
|
||||
rom_phy_disable_cca = 0x40000f04;
|
||||
rom_phy_enable_cca = 0x40000f08;
|
||||
rom_phy_get_noisefloor = 0x40000f0c;
|
||||
rom_phy_get_rx_freq = 0x40000f10;
|
||||
rom_phy_set_bbfreq_init = 0x40000f14;
|
||||
rom_pow_usr = 0x40000f18;
|
||||
rom_pwdet_sar2_init = 0x40000f1c;
|
||||
rom_read_hw_noisefloor = 0x40000f20;
|
||||
rom_read_sar_dout = 0x40000f24;
|
||||
rom_set_cal_rxdc = 0x40000f28;
|
||||
rom_set_chan_cal_interp = 0x40000f2c;
|
||||
rom_set_loopback_gain = 0x40000f30;
|
||||
rom_set_noise_floor = 0x40000f34;
|
||||
rom_set_rxclk_en = 0x40000f38;
|
||||
rom_set_tx_dig_gain = 0x40000f3c;
|
||||
rom_set_txcap_reg = 0x40000f40;
|
||||
rom_set_txclk_en = 0x40000f44;
|
||||
rom_spur_cal = 0x40000f48;
|
||||
rom_spur_reg_write_one_tone = 0x40000f4c;
|
||||
rom_target_power_add_backoff = 0x40000f50;
|
||||
rom_tx_pwctrl_bg_init = 0x40000f54;
|
||||
rom_txbbgain_to_index = 0x40000f58;
|
||||
rom_wifi_11g_rate_chg = 0x40000f5c;
|
||||
rom_write_gain_mem = 0x40000f60;
|
||||
chip726_phyrom_version = 0x40000f64;
|
||||
rom_disable_wifi_agc = 0x40000f68;
|
||||
rom_enable_wifi_agc = 0x40000f6c;
|
||||
rom_set_tx_gain_table = 0x40000f70;
|
||||
rom_bt_index_to_bb = 0x40000f74;
|
||||
rom_bt_bb_to_index = 0x40000f78;
|
||||
rom_wr_bt_tx_atten = 0x40000f7c;
|
||||
rom_wr_bt_tx_gain_mem = 0x40000f80;
|
||||
rom_spur_coef_cfg = 0x40000f84;
|
||||
rom_bb_bss_cbw40 = 0x40000f88;
|
||||
rom_set_cca = 0x40000f8c;
|
||||
rom_tx_paon_set = 0x40000f90;
|
||||
rom_i2cmst_reg_init = 0x40000f94;
|
||||
rom_iq_corr_enable = 0x40000f98;
|
||||
rom_fe_reg_init = 0x40000f9c;
|
||||
rom_agc_reg_init = 0x40000fa0;
|
||||
rom_bb_reg_init = 0x40000fa4;
|
||||
rom_mac_enable_bb = 0x40000fa8;
|
||||
rom_bb_wdg_cfg = 0x40000fac;
|
||||
rom_force_txon = 0x40000fb0;
|
||||
rom_fe_txrx_reset = 0x40000fb4;
|
||||
rom_set_rx_comp = 0x40000fb8;
|
||||
rom_set_pbus_reg = 0x40000fbc;
|
||||
rom_write_chan_freq = 0x40000fc0;
|
||||
rom_phy_xpd_rf = 0x40000fc4;
|
||||
rom_set_xpd_sar = 0x40000fc8;
|
||||
rom_write_dac_gain2 = 0x40000fcc;
|
||||
rom_get_target_power_offset = 0x40000fd0;
|
||||
rom_write_txrate_power_offset = 0x40000fd4;
|
||||
rom_get_rate_fcc_index = 0x40000fd8;
|
||||
rom_get_rate_target_power = 0x40000fdc;
|
||||
rom_write_wifi_dig_gain = 0x40000fe0;
|
||||
rom_bt_correct_rf_ana_gain = 0x40000fe4;
|
||||
rom_pkdet_vol_start = 0x40000fe8;
|
||||
rom_read_sar2_code = 0x40000fec;
|
||||
rom_get_sar2_vol = 0x40000ff0;
|
||||
rom_get_pll_vol = 0x40000ff4;
|
||||
rom_get_phy_target_power = 0x40000ff8;
|
||||
rom_temp_to_power = 0x40000ffc;
|
||||
rom_phy_track_pll_cap = 0x40001000;
|
||||
rom_phy_pwdet_always_en = 0x40001004;
|
||||
rom_phy_pwdet_onetime_en = 0x40001008;
|
||||
rom_get_i2c_mst0_mask = 0x4000100c;
|
||||
rom_get_i2c_hostid = 0x40001010;
|
||||
rom_enter_critical_phy = 0x40001014;
|
||||
rom_exit_critical_phy = 0x40001018;
|
||||
rom_chip_i2c_readReg_org = 0x4000101c;
|
||||
rom_i2c_paral_set_mst0 = 0x40001020;
|
||||
rom_i2c_paral_set_read = 0x40001024;
|
||||
rom_i2c_paral_read = 0x40001028;
|
||||
rom_i2c_paral_write = 0x4000102c;
|
||||
rom_i2c_paral_write_num = 0x40001030;
|
||||
rom_i2c_paral_write_mask = 0x40001034;
|
||||
rom_bb_bss_cbw40_ana = 0x40001038;
|
||||
rom_chan_to_freq = 0x4000103c;
|
||||
rom_open_i2c_xpd = 0x40001040;
|
||||
rom_dac_rate_set = 0x40001044;
|
||||
rom_tsens_read_init = 0x40001048;
|
||||
rom_tsens_code_read = 0x4000104c;
|
||||
rom_tsens_index_to_dac = 0x40001050;
|
||||
rom_tsens_index_to_offset = 0x40001054;
|
||||
rom_tsens_dac_cal = 0x40001058;
|
||||
rom_code_to_temp = 0x4000105c;
|
||||
rom_write_pll_cap_mem = 0x40001060;
|
||||
rom_pll_correct_dcap = 0x40001064;
|
||||
rom_phy_en_hw_set_freq = 0x40001068;
|
||||
rom_phy_dis_hw_set_freq = 0x4000106c;
|
||||
rom_pll_vol_cal = 0x40001070;
|
||||
rom_wrtie_pll_cap = 0x40001074;
|
||||
rom_set_tx_gain_mem = 0x40001078;
|
||||
rom_bt_tx_dig_gain = 0x4000107c;
|
||||
rom_bt_get_tx_gain = 0x40001080;
|
||||
rom_get_chan_target_power = 0x40001084;
|
||||
rom_get_tx_gain_value = 0x40001088;
|
||||
rom_wifi_tx_dig_gain = 0x4000108c;
|
||||
rom_wifi_get_tx_gain = 0x40001090;
|
||||
rom_fe_i2c_reg_renew = 0x40001094;
|
||||
rom_wifi_agc_sat_gain = 0x40001098;
|
||||
rom_i2c_master_reset = 0x4000109c;
|
||||
rom_bt_filter_reg = 0x400010a0;
|
||||
rom_phy_bbpll_cal = 0x400010a4;
|
||||
rom_i2c_sar2_init_code = 0x400010a8;
|
||||
rom_phy_param_addr = 0x400010ac;
|
||||
rom_phy_reg_init = 0x400010b0;
|
||||
rom_set_chan_reg = 0x400010b4;
|
||||
rom_phy_wakeup_init = 0x400010b8;
|
||||
rom_phy_i2c_init1 = 0x400010bc;
|
||||
rom_tsens_temp_read = 0x400010c0;
|
||||
rom_bt_track_pll_cap = 0x400010c4;
|
||||
rom_wifi_track_pll_cap = 0x400010c8;
|
||||
rom_wifi_set_tx_gain = 0x400010cc;
|
||||
rom_txpwr_cal_track = 0x400010d0;
|
||||
rom_tx_pwctrl_background = 0x400010d4;
|
||||
rom_bt_set_tx_gain = 0x400010d8;
|
||||
rom_noise_check_loop = 0x400010dc;
|
||||
rom_phy_close_rf = 0x400010e0;
|
||||
rom_phy_xpd_tsens = 0x400010e4;
|
||||
rom_phy_freq_mem_backup = 0x400010e8;
|
||||
rom_phy_ant_init = 0x400010ec;
|
||||
rom_bt_track_tx_power = 0x400010f0;
|
||||
rom_wifi_track_tx_power = 0x400010f4;
|
||||
rom_phy_dig_reg_backup = 0x400010f8;
|
||||
chip726_phyrom_version_num = 0x400010fc;
|
||||
phy_param_addr = 0x40001104;
|
||||
phy_get_romfuncs = 0x40001108;
|
||||
chip761_phyrom_version = 0x4000110c;
|
||||
chip761_phyrom_version_num = 0x40001110;
|
||||
get_rc_dout = 0x40001114;
|
||||
rc_cal = 0x40001118;
|
||||
rom_enter_critical_phy = 0x4000111c;
|
||||
rom_exit_critical_phy = 0x40001120;
|
||||
rom_set_chan_cal_interp = 0x40001124;
|
||||
rom_loopback_mode_en = 0x40001128;
|
||||
rom_bb_bss_cbw40 = 0x4000112c;
|
||||
abs_temp = 0x40001130;
|
||||
get_data_sat = 0x40001134;
|
||||
phy_byte_to_word = 0x40001138;
|
||||
set_chan_reg = 0x4000113c;
|
||||
i2c_master_reset = 0x40001140;
|
||||
rom_set_chan_freq_sw_start = 0x40001144;
|
||||
freq_module_resetn = 0x40001148;
|
||||
freq_chan_en_sw = 0x4000114c;
|
||||
write_chan_freq = 0x40001150;
|
||||
get_freq_mem_param = 0x40001154;
|
||||
get_freq_mem_addr = 0x40001158;
|
||||
bt_txpwr_freq = 0x4000115c;
|
||||
wr_rf_freq_mem = 0x40001160;
|
||||
read_rf_freq_mem = 0x40001164;
|
||||
freq_i2c_mem_write = 0x40001168;
|
||||
freq_num_get_data = 0x4000116c;
|
||||
freq_i2c_num_addr = 0x40001170;
|
||||
freq_i2c_write_set = 0x40001174;
|
||||
pll_dac_mem_update = 0x40001178;
|
||||
pll_cap_mem_update = 0x4000117c;
|
||||
get_rf_freq_cap = 0x40001180;
|
||||
get_rf_freq_init = 0x40001184;
|
||||
phy_en_hw_set_freq = 0x40001188;
|
||||
phy_dis_hw_set_freq = 0x4000118c;
|
||||
rom_pwdet_sar2_init = 0x40001190;
|
||||
rom_en_pwdet = 0x40001194;
|
||||
rom_get_sar_sig_ref = 0x40001198;
|
||||
rom_pwdet_tone_start = 0x4000119c;
|
||||
rom_pwdet_wait_idle = 0x400011a0;
|
||||
rom_read_sar_dout = 0x400011a4;
|
||||
get_tone_sar_dout = 0x400011a8;
|
||||
get_fm_sar_dout = 0x400011ac;
|
||||
txtone_linear_pwr = 0x400011b0;
|
||||
linear_to_db = 0x400011b4;
|
||||
get_power_db = 0x400011b8;
|
||||
meas_tone_pwr_db = 0x400011bc;
|
||||
pkdet_vol_start = 0x400011c0;
|
||||
read_sar2_code = 0x400011c4;
|
||||
get_sar2_vol = 0x400011c8;
|
||||
get_pll_vol = 0x400011cc;
|
||||
tx_pwctrl_bg_init = 0x400011d0;
|
||||
phy_pwdet_always_en = 0x400011d4;
|
||||
phy_pwdet_onetime_en = 0x400011d8;
|
||||
esp_tx_state_out_rom = 0x400011dc;
|
||||
ant_dft_cfg_rom = 0x400011e0;
|
||||
ant_wifitx_cfg_rom = 0x400011e4;
|
||||
ant_wifirx_cfg_rom = 0x400011e8;
|
||||
ant_bttx_cfg_rom = 0x400011ec;
|
||||
ant_btrx_cfg_rom = 0x400011f0;
|
||||
phy_chan_dump_cfg_rom = 0x400011f4;
|
||||
phy_enable_low_rate = 0x400011f8;
|
||||
phy_disable_low_rate = 0x400011fc;
|
||||
phy_is_low_rate_enabled = 0x40001200;
|
||||
phy_dig_reg_backup_rom = 0x40001204;
|
||||
phy_chan_filt_set_rom = 0x40001208;
|
||||
phy_rx11blr_cfg = 0x4000120c;
|
||||
set_cca_rom = 0x40001210;
|
||||
set_rx_sense_rom = 0x40001214;
|
||||
rx_gain_force_rom = 0x40001218;
|
||||
rom_rfpll_set_freq = 0x4000121c;
|
||||
mhz2ieee = 0x40001220;
|
||||
chan_to_freq = 0x40001224;
|
||||
restart_cal = 0x40001228;
|
||||
write_rfpll_sdm = 0x4000122c;
|
||||
wait_rfpll_cal_end = 0x40001230;
|
||||
set_rf_freq_offset = 0x40001234;
|
||||
set_rfpll_freq = 0x40001238;
|
||||
set_channel_rfpll_freq = 0x4000123c;
|
||||
rfpll_cap_correct = 0x40001240;
|
||||
rfpll_cap_init_cal = 0x40001244;
|
||||
write_pll_cap = 0x40001248;
|
||||
read_pll_cap = 0x4000124c;
|
||||
chip_v7_set_chan_ana = 0x40001250;
|
||||
freq_set_reg = 0x40001254;
|
||||
gen_rx_gain_table = 0x40001258;
|
||||
bt_txdc_cal = 0x4000125c;
|
||||
bt_txiq_cal = 0x40001260;
|
||||
txiq_cal_init = 0x40001264;
|
||||
txdc_cal_init = 0x40001268;
|
||||
txdc_cal = 0x4000126c;
|
||||
txiq_get_mis_pwr = 0x40001270;
|
||||
txiq_cover = 0x40001274;
|
||||
rfcal_txiq = 0x40001278;
|
||||
get_power_atten = 0x4000127c;
|
||||
pwdet_ref_code = 0x40001280;
|
||||
pwdet_code_cal = 0x40001284;
|
||||
rfcal_txcap = 0x40001288;
|
||||
tx_cap_init = 0x4000128c;
|
||||
rfcal_pwrctrl = 0x40001290;
|
||||
tx_pwctrl_init_cal = 0x40001294;
|
||||
tx_pwctrl_init = 0x40001298;
|
||||
bt_tx_pwctrl_init = 0x4000129c;
|
||||
rom_i2c_enter_critical = 0x400012a0;
|
||||
rom_i2c_exit_critical = 0x400012a4;
|
||||
rom_get_i2c_read_mask = 0x400012a8;
|
||||
rom_get_i2c_mst0_mask = 0x400012ac;
|
||||
rom_get_i2c_hostid = 0x400012b0;
|
||||
rom_chip_i2c_readReg_org = 0x400012b4;
|
||||
rom_chip_i2c_readReg = 0x400012b8;
|
||||
rom_i2c_readReg = 0x400012bc;
|
||||
rom_chip_i2c_writeReg = 0x400012c0;
|
||||
rom_i2c_writeReg = 0x400012c4;
|
||||
rom_i2c_readReg_Mask = 0x400012c8;
|
||||
rom_i2c_writeReg_Mask = 0x400012cc;
|
||||
rom_set_txcap_reg = 0x400012d0;
|
||||
i2c_paral_set_mst0 = 0x400012d4;
|
||||
i2c_paral_set_read = 0x400012d8;
|
||||
i2c_paral_read = 0x400012dc;
|
||||
i2c_paral_write = 0x400012e0;
|
||||
i2c_paral_write_num = 0x400012e4;
|
||||
i2c_paral_write_mask = 0x400012e8;
|
||||
i2c_sar2_init_code = 0x400012ec;
|
||||
rom_pbus_force_mode = 0x400012f0;
|
||||
rom_pbus_rd_addr = 0x400012f4;
|
||||
rom_pbus_rd_shift = 0x400012f8;
|
||||
rom_pbus_force_test = 0x400012fc;
|
||||
rom_pbus_rd = 0x40001300;
|
||||
rom_pbus_set_rxgain = 0x40001304;
|
||||
rom_pbus_xpd_rx_off = 0x40001308;
|
||||
rom_pbus_xpd_rx_on = 0x4000130c;
|
||||
rom_pbus_xpd_tx_off = 0x40001310;
|
||||
rom_pbus_xpd_tx_on = 0x40001314;
|
||||
rom_set_loopback_gain = 0x40001318;
|
||||
rom_txcal_debuge_mode = 0x4000131c;
|
||||
pbus_debugmode = 0x40001320;
|
||||
pbus_workmode = 0x40001324;
|
||||
pbus_set_dco = 0x40001328;
|
||||
txcal_work_mode = 0x4000132c;
|
||||
rom_start_tx_tone_step = 0x40001330;
|
||||
rom_stop_tx_tone = 0x40001334;
|
||||
disable_agc = 0x40001338;
|
||||
enable_agc = 0x4000133c;
|
||||
phy_disable_cca = 0x40001340;
|
||||
phy_enable_cca = 0x40001344;
|
||||
write_gain_mem = 0x40001348;
|
||||
bb_bss_cbw40_dig = 0x4000134c;
|
||||
cbw2040_cfg = 0x40001350;
|
||||
mac_tx_chan_offset = 0x40001354;
|
||||
tx_paon_set = 0x40001358;
|
||||
pwdet_reg_init = 0x4000135c;
|
||||
i2cmst_reg_init = 0x40001360;
|
||||
bt_gain_offset = 0x40001364;
|
||||
fe_reg_init = 0x40001368;
|
||||
mac_enable_bb = 0x4000136c;
|
||||
bb_wdg_cfg = 0x40001370;
|
||||
fe_txrx_reset = 0x40001374;
|
||||
set_rx_comp = 0x40001378;
|
||||
agc_reg_init = 0x4000137c;
|
||||
bb_reg_init = 0x40001380;
|
||||
open_i2c_xpd = 0x40001384;
|
||||
txiq_set_reg = 0x40001388;
|
||||
rxiq_set_reg = 0x4000138c;
|
||||
set_txclk_en = 0x40001390;
|
||||
set_rxclk_en = 0x40001394;
|
||||
bb_wdg_test_en = 0x40001398;
|
||||
noise_floor_auto_set = 0x4000139c;
|
||||
read_hw_noisefloor = 0x400013a0;
|
||||
iq_corr_enable = 0x400013a4;
|
||||
wifi_agc_sat_gain = 0x400013a8;
|
||||
phy_bbpll_cal = 0x400013ac;
|
||||
phy_ant_init = 0x400013b0;
|
||||
phy_set_bbfreq_init = 0x400013b4;
|
||||
wifi_fbw_sel = 0x400013b8;
|
||||
bt_filter_reg = 0x400013bc;
|
||||
phy_rx_sense_set = 0x400013c0;
|
||||
tx_state_set = 0x400013c4;
|
||||
phy_close_pa = 0x400013c8;
|
||||
phy_freq_correct = 0x400013cc;
|
||||
set_pbus_reg = 0x400013d0;
|
||||
wifi_rifs_mode_en = 0x400013d4;
|
||||
nrx_freq_set = 0x400013d8;
|
||||
fe_adc_on = 0x400013dc;
|
||||
phy_force_pwr_index = 0x400013e0;
|
||||
rom_iq_est_enable = 0x400013e4;
|
||||
rom_iq_est_disable = 0x400013e8;
|
||||
rom_bb_gain_index = 0x400013ec;
|
||||
rom_rfrx_gain_index = 0x400013f0;
|
||||
dc_iq_est = 0x400013f4;
|
||||
set_cal_rxdc = 0x400013f8;
|
||||
rxiq_get_mis = 0x400013fc;
|
||||
rxiq_cover_mg_mp = 0x40001400;
|
||||
rfcal_rxiq = 0x40001404;
|
||||
get_rfcal_rxiq_data = 0x40001408;
|
||||
get_dco_comp = 0x4000140c;
|
||||
pbus_rx_dco_cal = 0x40001410;
|
||||
rxdc_est_min = 0x40001414;
|
||||
pbus_rx_dco_cal_1step = 0x40001418;
|
||||
set_lb_txiq = 0x4000141c;
|
||||
set_rx_gain_cal_iq = 0x40001420;
|
||||
set_rx_gain_cal_dc = 0x40001424;
|
||||
spur_reg_write_one_tone = 0x40001428;
|
||||
spur_cal = 0x4000142c;
|
||||
spur_coef_cfg = 0x40001430;
|
||||
tsens_power_up = 0x40001434;
|
||||
tsens_read_init = 0x40001438;
|
||||
code_to_temp = 0x4000143c;
|
||||
tsens_index_to_dac = 0x40001440;
|
||||
tsens_index_to_offset = 0x40001444;
|
||||
tsens_dac_cal = 0x40001448;
|
||||
tsens_code_read = 0x4000144c;
|
||||
tsens_temp_read = 0x40001450;
|
||||
temp_to_power = 0x40001454;
|
||||
get_temp_init = 0x40001458;
|
||||
txbbgain_to_index = 0x4000145c;
|
||||
index_to_txbbgain = 0x40001460;
|
||||
bt_index_to_bb = 0x40001464;
|
||||
bt_bb_to_index = 0x40001468;
|
||||
bt_get_tx_gain = 0x4000146c;
|
||||
dig_gain_check = 0x40001470;
|
||||
wifi_get_tx_gain = 0x40001474;
|
||||
wifi_11g_rate_chg = 0x40001478;
|
||||
bt_chan_pwr_interp = 0x4000147c;
|
||||
get_rate_fcc_index = 0x40001480;
|
||||
get_chan_target_power = 0x40001484;
|
||||
get_tx_gain_value = 0x40001488;
|
||||
wifi_get_target_power = 0x4000148c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
phy_param_rom = 0x4087fcd8;
|
||||
phy_param_rom = 0x4087fce8;
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.pp.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
@ -19,245 +19,441 @@
|
||||
|
||||
/* Functions */
|
||||
esp_pp_rom_version_get = 0x40000bd8;
|
||||
RC_GetBlockAckTime = 0x40000bdc;
|
||||
ebuf_list_remove = 0x40000be0;
|
||||
esf_buf_alloc = 0x40000be4;
|
||||
esf_buf_alloc_dynamic = 0x40000be8;
|
||||
esf_buf_recycle = 0x40000bec;
|
||||
GetAccess = 0x40000bf0;
|
||||
hal_mac_is_low_rate_enabled = 0x40000bf4;
|
||||
hal_mac_tx_get_blockack = 0x40000bf8;
|
||||
hal_mac_tx_set_ppdu = 0x40000bfc;
|
||||
ic_get_trc = 0x40000c00;
|
||||
ic_mac_deinit = 0x40000c04;
|
||||
ic_mac_init = 0x40000c08;
|
||||
ic_interface_enabled = 0x40000c0c;
|
||||
is_lmac_idle = 0x40000c10;
|
||||
lmacAdjustTimestamp = 0x40000c14;
|
||||
lmacDiscardAgedMSDU = 0x40000c18;
|
||||
lmacDiscardMSDU = 0x40000c1c;
|
||||
lmacEndFrameExchangeSequence = 0x40000c20;
|
||||
lmacIsIdle = 0x40000c24;
|
||||
lmacIsLongFrame = 0x40000c28;
|
||||
lmacMSDUAged = 0x40000c2c;
|
||||
lmacPostTxComplete = 0x40000c30;
|
||||
lmacProcessAllTxTimeout = 0x40000c34;
|
||||
lmacProcessCollisions = 0x40000c38;
|
||||
lmacProcessRxSucData = 0x40000c3c;
|
||||
lmacReachLongLimit = 0x40000c40;
|
||||
lmacReachShortLimit = 0x40000c44;
|
||||
lmacRecycleMPDU = 0x40000c48;
|
||||
lmacRxDone = 0x40000c4c;
|
||||
lmacSetTxFrame = 0x40000c50;
|
||||
lmacTxDone = 0x40000c54;
|
||||
lmacTxFrame = 0x40000c58;
|
||||
mac_tx_set_duration = 0x40000c5c;
|
||||
mac_tx_set_plcp0 = 0x40000c60;
|
||||
mac_tx_set_plcp1 = 0x40000c64;
|
||||
mac_tx_set_plcp2 = 0x40000c68;
|
||||
pm_check_state = 0x40000c6c;
|
||||
pm_disable_dream_timer = 0x40000c70;
|
||||
pm_disable_sleep_delay_timer = 0x40000c74;
|
||||
pm_dream = 0x40000c78;
|
||||
pm_mac_wakeup = 0x40000c7c;
|
||||
pm_mac_sleep = 0x40000c80;
|
||||
pm_enable_active_timer = 0x40000c84;
|
||||
pm_enable_sleep_delay_timer = 0x40000c88;
|
||||
pm_local_tsf_process = 0x40000c8c;
|
||||
pm_set_beacon_filter = 0x40000c90;
|
||||
pm_is_in_wifi_slice_threshold = 0x40000c94;
|
||||
pm_is_waked = 0x40000c98;
|
||||
pm_keep_alive = 0x40000c9c;
|
||||
pm_on_beacon_rx = 0x40000ca0;
|
||||
pm_on_data_rx = 0x40000ca4;
|
||||
pm_on_tbtt = 0x40000ca8;
|
||||
pm_parse_beacon = 0x40000cac;
|
||||
pm_process_tim = 0x40000cb0;
|
||||
pm_rx_beacon_process = 0x40000cb4;
|
||||
pm_rx_data_process = 0x40000cb8;
|
||||
pm_sleep = 0x40000cbc;
|
||||
pm_sleep_for = 0x40000cc0;
|
||||
pm_tbtt_process = 0x40000cc4;
|
||||
ppAMPDU2Normal = 0x40000cc8;
|
||||
ppAssembleAMPDU = 0x40000ccc;
|
||||
ppCalFrameTimes = 0x40000cd0;
|
||||
ppCalSubFrameLength = 0x40000cd4;
|
||||
ppCalTxAMPDULength = 0x40000cd8;
|
||||
ppCheckTxAMPDUlength = 0x40000cdc;
|
||||
ppDequeueRxq_Locked = 0x40000ce0;
|
||||
ppDequeueTxQ = 0x40000ce4;
|
||||
ppEmptyDelimiterLength = 0x40000ce8;
|
||||
ppEnqueueRxq = 0x40000cec;
|
||||
ppEnqueueTxDone = 0x40000cf0;
|
||||
ppGetTxframe = 0x40000cf4;
|
||||
ppMapTxQueue = 0x40000cf8;
|
||||
ppProcTxSecFrame = 0x40000cfc;
|
||||
ppProcessRxPktHdr = 0x40000d00;
|
||||
ppProcessTxQ = 0x40000d04;
|
||||
ppRecordBarRRC = 0x40000d08;
|
||||
ppRecycleAmpdu = 0x40000d0c;
|
||||
ppRecycleRxPkt = 0x40000d10;
|
||||
ppResortTxAMPDU = 0x40000d14;
|
||||
ppResumeTxAMPDU = 0x40000d18;
|
||||
ppRxFragmentProc = 0x40000d1c;
|
||||
ppRxPkt = 0x40000d20;
|
||||
ppRxProtoProc = 0x40000d24;
|
||||
ppSearchTxQueue = 0x40000d28;
|
||||
ppSearchTxframe = 0x40000d2c;
|
||||
ppSelectNextQueue = 0x40000d30;
|
||||
ppSubFromAMPDU = 0x40000d34;
|
||||
ppTask = 0x40000d38;
|
||||
ppTxPkt = 0x40000d3c;
|
||||
ppTxProtoProc = 0x40000d40;
|
||||
ppTxqUpdateBitmap = 0x40000d44;
|
||||
pp_coex_tx_request = 0x40000d48;
|
||||
pp_hdrsize = 0x40000d4c;
|
||||
pp_post = 0x40000d50;
|
||||
pp_process_hmac_waiting_txq = 0x40000d54;
|
||||
rcGetAmpduSched = 0x40000d58;
|
||||
rcUpdateRxDone = 0x40000d5c;
|
||||
rc_get_trc = 0x40000d60;
|
||||
rc_get_trc_by_index = 0x40000d64;
|
||||
rcAmpduLowerRate = 0x40000d68;
|
||||
rcampduuprate = 0x40000d6c;
|
||||
rcClearCurAMPDUSched = 0x40000d70;
|
||||
rcClearCurSched = 0x40000d74;
|
||||
rcClearCurStat = 0x40000d78;
|
||||
rcGetSched = 0x40000d7c;
|
||||
rcLowerSched = 0x40000d80;
|
||||
rcSetTxAmpduLimit = 0x40000d84;
|
||||
rcTxUpdatePer = 0x40000d88;
|
||||
rcUpdateAckSnr = 0x40000d8c;
|
||||
rcUpdateRate = 0x40000d90;
|
||||
rcUpdateTxDone = 0x40000d94;
|
||||
rcUpdateTxDoneAmpdu2 = 0x40000d98;
|
||||
rcUpSched = 0x40000d9c;
|
||||
rssi_margin = 0x40000da0;
|
||||
rx11NRate2AMPDULimit = 0x40000da4;
|
||||
TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000da8;
|
||||
TRC_AMPDU_PER_UP_THRESHOLD = 0x40000dac;
|
||||
trc_calc_duration = 0x40000db0;
|
||||
trc_isTxAmpduOperational = 0x40000db4;
|
||||
trc_onAmpduOp = 0x40000db8;
|
||||
TRC_PER_IS_GOOD = 0x40000dbc;
|
||||
trc_SetTxAmpduState = 0x40000dc0;
|
||||
trc_tid_isTxAmpduOperational = 0x40000dc4;
|
||||
trcAmpduSetState = 0x40000dc8;
|
||||
wDevCheckBlockError = 0x40000dcc;
|
||||
wDev_AppendRxBlocks = 0x40000dd0;
|
||||
wDev_DiscardFrame = 0x40000dd4;
|
||||
wDev_GetNoiseFloor = 0x40000dd8;
|
||||
wDev_IndicateAmpdu = 0x40000ddc;
|
||||
wDev_IndicateFrame = 0x40000de0;
|
||||
wdev_mac_reg_load = 0x40000de4;
|
||||
wdev_mac_reg_store = 0x40000de8;
|
||||
wdev_mac_special_reg_load = 0x40000dec;
|
||||
wdev_mac_special_reg_store = 0x40000df0;
|
||||
wdev_mac_wakeup = 0x40000df4;
|
||||
wdev_mac_sleep = 0x40000df8;
|
||||
hal_mac_is_dma_enable = 0x40000dfc;
|
||||
wDev_ProcessFiq = 0x40000e00;
|
||||
wDev_ProcessRxSucData = 0x40000e04;
|
||||
wdevProcessRxSucDataAll = 0x40000e08;
|
||||
wdev_csi_len_align = 0x40000e0c;
|
||||
ppDequeueTxDone_Locked = 0x40000e10;
|
||||
ppProcTxDone = 0x40000e14;
|
||||
pm_tx_data_done_process = 0x40000e18;
|
||||
config_is_cache_tx_buf_enabled = 0x40000e1c;
|
||||
ppMapWaitTxq = 0x40000e20;
|
||||
ppProcessWaitingQueue = 0x40000e24;
|
||||
ppDisableQueue = 0x40000e28;
|
||||
pm_allow_tx = 0x40000e2c;
|
||||
wdev_is_data_in_rxlist = 0x40000e30;
|
||||
ppProcTxCallback = 0x40000e34;
|
||||
mac_tx_set_hesig = 0x40000e38;
|
||||
ppCalPreFecPaddingFactor = 0x40000e3c;
|
||||
mac_tx_set_tb = 0x40000e40;
|
||||
mac_tx_set_mplen = 0x40000e44;
|
||||
ppCalTxopRTSThreshold = 0x40000bdc;
|
||||
RC_GetBlockAckTime = 0x40000be0;
|
||||
ebuf_list_remove = 0x40000be4;
|
||||
esf_buf_alloc = 0x40000be8;
|
||||
esf_buf_alloc_dynamic = 0x40000bec;
|
||||
esf_buf_recycle = 0x40000bf0;
|
||||
GetAccess = 0x40000bf4;
|
||||
hal_mac_is_low_rate_enabled = 0x40000bf8;
|
||||
hal_mac_tx_get_blockack = 0x40000bfc;
|
||||
hal_mac_tx_set_ppdu = 0x40000c00;
|
||||
ic_get_trc = 0x40000c04;
|
||||
ic_mac_deinit = 0x40000c08;
|
||||
ic_mac_init = 0x40000c0c;
|
||||
ic_interface_enabled = 0x40000c10;
|
||||
is_lmac_idle = 0x40000c14;
|
||||
lmacAdjustTimestamp = 0x40000c18;
|
||||
lmacDiscardAgedMSDU = 0x40000c1c;
|
||||
lmacDiscardMSDU = 0x40000c20;
|
||||
lmacEndFrameExchangeSequence = 0x40000c24;
|
||||
lmacIsIdle = 0x40000c28;
|
||||
lmacIsLongFrame = 0x40000c2c;
|
||||
lmacMSDUAged = 0x40000c30;
|
||||
lmacPostTxComplete = 0x40000c34;
|
||||
lmacProcessAllTxTimeout = 0x40000c38;
|
||||
lmacProcessCollisions = 0x40000c3c;
|
||||
lmacProcessRxSucData = 0x40000c40;
|
||||
lmacReachLongLimit = 0x40000c44;
|
||||
lmacReachShortLimit = 0x40000c48;
|
||||
lmacRecycleMPDU = 0x40000c4c;
|
||||
lmacRxDone = 0x40000c50;
|
||||
lmacSetTxFrame = 0x40000c54;
|
||||
lmacTxDone = 0x40000c58;
|
||||
lmacTxFrame = 0x40000c5c;
|
||||
mac_tx_set_duration = 0x40000c60;
|
||||
mac_tx_set_plcp0 = 0x40000c64;
|
||||
mac_tx_set_plcp1 = 0x40000c68;
|
||||
mac_tx_set_plcp2 = 0x40000c6c;
|
||||
pm_check_state = 0x40000c70;
|
||||
pm_disable_dream_timer = 0x40000c74;
|
||||
pm_disable_sleep_delay_timer = 0x40000c78;
|
||||
pm_dream = 0x40000c7c;
|
||||
pm_mac_wakeup = 0x40000c80;
|
||||
pm_mac_sleep = 0x40000c84;
|
||||
pm_enable_active_timer = 0x40000c88;
|
||||
pm_enable_sleep_delay_timer = 0x40000c8c;
|
||||
pm_local_tsf_process = 0x40000c90;
|
||||
pm_set_beacon_filter = 0x40000c94;
|
||||
pm_is_in_wifi_slice_threshold = 0x40000c98;
|
||||
pm_is_waked = 0x40000c9c;
|
||||
pm_keep_alive = 0x40000ca0;
|
||||
pm_on_beacon_rx = 0x40000ca4;
|
||||
pm_on_data_rx = 0x40000ca8;
|
||||
pm_on_tbtt = 0x40000cac;
|
||||
pm_parse_beacon = 0x40000cb0;
|
||||
pm_process_tim = 0x40000cb4;
|
||||
pm_rx_beacon_process = 0x40000cb8;
|
||||
pm_rx_data_process = 0x40000cbc;
|
||||
pm_sleep = 0x40000cc0;
|
||||
pm_sleep_for = 0x40000cc4;
|
||||
pm_tbtt_process = 0x40000cc8;
|
||||
ppAMPDU2Normal = 0x40000ccc;
|
||||
ppAssembleAMPDU = 0x40000cd0;
|
||||
ppCalFrameTimes = 0x40000cd4;
|
||||
ppCalSubFrameLength = 0x40000cd8;
|
||||
ppCalTxAMPDULength = 0x40000cdc;
|
||||
ppCheckTxAMPDUlength = 0x40000ce0;
|
||||
ppDequeueRxq_Locked = 0x40000ce4;
|
||||
ppDequeueTxQ = 0x40000ce8;
|
||||
ppEmptyDelimiterLength = 0x40000cec;
|
||||
ppEnqueueRxq = 0x40000cf0;
|
||||
ppEnqueueTxDone = 0x40000cf4;
|
||||
ppGetTxframe = 0x40000cf8;
|
||||
ppMapTxQueue = 0x40000cfc;
|
||||
ppProcTxSecFrame = 0x40000d00;
|
||||
ppProcessRxPktHdr = 0x40000d04;
|
||||
ppProcessTxQ = 0x40000d08;
|
||||
ppRecordBarRRC = 0x40000d0c;
|
||||
ppRecycleAmpdu = 0x40000d10;
|
||||
ppRecycleRxPkt = 0x40000d14;
|
||||
ppResortTxAMPDU = 0x40000d18;
|
||||
ppResumeTxAMPDU = 0x40000d1c;
|
||||
ppRxFragmentProc = 0x40000d20;
|
||||
ppRxPkt = 0x40000d24;
|
||||
ppRxProtoProc = 0x40000d28;
|
||||
ppSearchTxQueue = 0x40000d2c;
|
||||
ppSearchTxframe = 0x40000d30;
|
||||
ppSelectNextQueue = 0x40000d34;
|
||||
ppSubFromAMPDU = 0x40000d38;
|
||||
ppTask = 0x40000d3c;
|
||||
ppTxPkt = 0x40000d40;
|
||||
ppTxProtoProc = 0x40000d44;
|
||||
ppTxqUpdateBitmap = 0x40000d48;
|
||||
pp_coex_tx_request = 0x40000d4c;
|
||||
pp_hdrsize = 0x40000d50;
|
||||
pp_post = 0x40000d54;
|
||||
pp_process_hmac_waiting_txq = 0x40000d58;
|
||||
rcGetAmpduSched = 0x40000d5c;
|
||||
rcUpdateRxDone = 0x40000d60;
|
||||
rc_get_trc = 0x40000d64;
|
||||
rc_get_trc_by_index = 0x40000d68;
|
||||
rcAmpduLowerRate = 0x40000d6c;
|
||||
rcampduuprate = 0x40000d70;
|
||||
rcClearCurAMPDUSched = 0x40000d74;
|
||||
rcClearCurSched = 0x40000d78;
|
||||
rcClearCurStat = 0x40000d7c;
|
||||
rcGetSched = 0x40000d80;
|
||||
rcLowerSched = 0x40000d84;
|
||||
rcSetTxAmpduLimit = 0x40000d88;
|
||||
rcTxUpdatePer = 0x40000d8c;
|
||||
rcUpdateAckSnr = 0x40000d90;
|
||||
rcUpdateRate = 0x40000d94;
|
||||
rcUpdateTxDone = 0x40000d98;
|
||||
rcUpdateTxDoneAmpdu2 = 0x40000d9c;
|
||||
rcUpSched = 0x40000da0;
|
||||
rssi_margin = 0x40000da4;
|
||||
rx11NRate2AMPDULimit = 0x40000da8;
|
||||
TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40000dac;
|
||||
TRC_AMPDU_PER_UP_THRESHOLD = 0x40000db0;
|
||||
trc_calc_duration = 0x40000db4;
|
||||
trc_isTxAmpduOperational = 0x40000db8;
|
||||
trc_onAmpduOp = 0x40000dbc;
|
||||
TRC_PER_IS_GOOD = 0x40000dc0;
|
||||
trc_SetTxAmpduState = 0x40000dc4;
|
||||
trc_tid_isTxAmpduOperational = 0x40000dc8;
|
||||
trcAmpduSetState = 0x40000dcc;
|
||||
wDevCheckBlockError = 0x40000dd0;
|
||||
wDev_AppendRxBlocks = 0x40000dd4;
|
||||
wDev_DiscardFrame = 0x40000dd8;
|
||||
wDev_GetNoiseFloor = 0x40000ddc;
|
||||
wDev_IndicateAmpdu = 0x40000de0;
|
||||
wDev_IndicateFrame = 0x40000de4;
|
||||
wdev_mac_reg_load = 0x40000de8;
|
||||
wdev_mac_reg_store = 0x40000dec;
|
||||
wdev_mac_special_reg_load = 0x40000df0;
|
||||
wdev_mac_special_reg_store = 0x40000df4;
|
||||
wdev_mac_wakeup = 0x40000df8;
|
||||
wdev_mac_sleep = 0x40000dfc;
|
||||
hal_mac_is_dma_enable = 0x40000e00;
|
||||
wDev_ProcessFiq = 0x40000e04;
|
||||
wDev_ProcessRxSucData = 0x40000e08;
|
||||
wdevProcessRxSucDataAll = 0x40000e0c;
|
||||
wdev_csi_len_align = 0x40000e10;
|
||||
ppDequeueTxDone_Locked = 0x40000e14;
|
||||
ppProcTxDone = 0x40000e18;
|
||||
pm_tx_data_done_process = 0x40000e1c;
|
||||
config_is_cache_tx_buf_enabled = 0x40000e20;
|
||||
ppMapWaitTxq = 0x40000e24;
|
||||
ppProcessWaitingQueue = 0x40000e28;
|
||||
ppDisableQueue = 0x40000e2c;
|
||||
pm_allow_tx = 0x40000e30;
|
||||
wdev_is_data_in_rxlist = 0x40000e34;
|
||||
ppProcTxCallback = 0x40000e38;
|
||||
mac_tx_set_hesig = 0x40000e3c;
|
||||
ppCalPreFecPaddingFactor = 0x40000e40;
|
||||
mac_tx_set_tb = 0x40000e44;
|
||||
mac_tx_set_mplen = 0x40000e48;
|
||||
hal_get_tsf_timer = 0x40000e4c;
|
||||
ppTxPktForceWaked = 0x40000e50;
|
||||
lmacProcessLongFrameSuccess = 0x40000e54;
|
||||
lmacProcessShortFrameSuccess = 0x40000e58;
|
||||
lmacDiscardFrameExchangeSequence = 0x40000e5c;
|
||||
lmacProcessTBSuccess = 0x40000e60;
|
||||
lmacProcessTxSuccess = 0x40000e64;
|
||||
lmacProcessAckTimeout = 0x40000e68;
|
||||
lmacProcessTxComplete = 0x40000e6c;
|
||||
ppRemoveHTC = 0x40000e70;
|
||||
get_estimated_batime = 0x40000e74;
|
||||
is_use_muedca = 0x40000e78;
|
||||
hal_mac_tx_clr_mplen = 0x40000e7c;
|
||||
hal_mac_get_txq_state = 0x40000e80;
|
||||
hal_mac_clr_txq_state = 0x40000e84;
|
||||
hal_mac_get_txq_complete = 0x40000e88;
|
||||
ht_get_min_subframe_len = 0x40000e8c;
|
||||
rx11ACRate2AMPDULimit = 0x40000e90;
|
||||
pwr_hal_clear_intr_status = 0x40000e94;
|
||||
pwr_hal_clear_mac_modem_beacon_miss_intr_filter = 0x40000e98;
|
||||
pwr_hal_clear_mac_modem_rx_beacon_info = 0x40000e9c;
|
||||
pwr_hal_clear_mac_modem_rx_beacon_miss_counter = 0x40000ea0;
|
||||
pwr_hal_clear_mac_modem_rx_beacon_sleep_counter = 0x40000ea4;
|
||||
pwr_hal_clear_mac_modem_state_wakeup_protect_signal = 0x40000ea8;
|
||||
pwr_hal_get_intr_raw_signal = 0x40000eac;
|
||||
pwr_hal_get_intr_status = 0x40000eb0;
|
||||
pwr_hal_get_mac_modem_beacon_miss_limit_exceeded_status = 0x40000eb4;
|
||||
pwr_hal_get_mac_modem_rx_beacon_location_state = 0x40000eb8;
|
||||
pwr_hal_get_mac_modem_rx_beacon_valid_state = 0x40000ebc;
|
||||
pwr_hal_get_mac_modem_state_sleep_limit_exceeded_status = 0x40000ec0;
|
||||
pwr_hal_set_beacon_filter_abort_disable = 0x40000ec4;
|
||||
pwr_hal_set_beacon_filter_abort_enable = 0x40000ec8;
|
||||
pwr_hal_set_beacon_filter_abort_length = 0x40000ecc;
|
||||
pwr_hal_set_beacon_filter_broadcast_wakeup_disable = 0x40000ed0;
|
||||
pwr_hal_set_beacon_filter_broadcast_wakeup_enable = 0x40000ed4;
|
||||
pwr_hal_set_beacon_filter_disable = 0x40000ed8;
|
||||
pwr_hal_set_beacon_filter_enable = 0x40000edc;
|
||||
pwr_hal_set_beacon_filter_force_dump_disable = 0x40000ee0;
|
||||
pwr_hal_set_beacon_filter_force_dump_enable = 0x40000ee4;
|
||||
pwr_hal_set_beacon_filter_force_dump_limit = 0x40000ee8;
|
||||
pwr_hal_set_beacon_filter_force_sync_disable = 0x40000eec;
|
||||
pwr_hal_set_beacon_filter_force_sync_enable = 0x40000ef0;
|
||||
pwr_hal_set_beacon_filter_force_sync_limit = 0x40000ef4;
|
||||
pwr_hal_set_beacon_filter_frame_crc_state = 0x40000ef8;
|
||||
pwr_hal_set_beacon_filter_soc_wakeup_and_intr_disable = 0x40000efc;
|
||||
pwr_hal_set_beacon_filter_soc_wakeup_and_intr_enable = 0x40000f00;
|
||||
pwr_hal_set_beacon_filter_unicast_wakeup_disable = 0x40000f04;
|
||||
pwr_hal_set_beacon_filter_unicast_wakeup_enable = 0x40000f08;
|
||||
pwr_hal_set_lpclk_cycle_time = 0x40000f0c;
|
||||
pwr_hal_set_lpclk_sync_disable = 0x40000f10;
|
||||
pwr_hal_set_lpclk_sync_enable = 0x40000f14;
|
||||
pwr_hal_set_mac_modem_beacon_miss_intr_disable = 0x40000f18;
|
||||
pwr_hal_set_mac_modem_beacon_miss_intr_enable = 0x40000f1c;
|
||||
pwr_hal_set_mac_modem_beacon_miss_limit = 0x40000f20;
|
||||
pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_disable = 0x40000f24;
|
||||
pwr_hal_set_mac_modem_beacon_miss_limit_exceeded_wakeup_enable = 0x40000f28;
|
||||
pwr_hal_set_mac_modem_beacon_miss_timeout = 0x40000f2c;
|
||||
pwr_hal_set_mac_modem_state_sleep_limit = 0x40000f30;
|
||||
pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_disable = 0x40000f34;
|
||||
pwr_hal_set_mac_modem_state_sleep_limit_exceeded_wakeup_enable = 0x40000f38;
|
||||
pwr_hal_set_mac_modem_state_wakeup_protect_disable = 0x40000f3c;
|
||||
pwr_hal_set_mac_modem_state_wakeup_protect_early_time = 0x40000f40;
|
||||
pwr_hal_set_mac_modem_state_wakeup_protect_enable = 0x40000f44;
|
||||
pwr_hal_set_mac_modem_tbtt_auto_period_disable = 0x40000f48;
|
||||
pwr_hal_set_mac_modem_tbtt_auto_period_enable = 0x40000f4c;
|
||||
pwr_hal_set_mac_modem_tbtt_auto_period_interval = 0x40000f50;
|
||||
pwr_hal_set_modem_state_interface = 0x40000f54;
|
||||
hal_tsf_clear_soc_wakeup_request = 0x40000f58;
|
||||
tsf_hal_clear_mac_modem_rf_power_state = 0x40000f5c;
|
||||
tsf_hal_clear_soc_wakeup_request = 0x40000f60;
|
||||
tsf_hal_get_counter_value = 0x40000f64;
|
||||
tsf_hal_get_mac_modem_rf_power_state = 0x40000f68;
|
||||
tsf_hal_get_tbtt_interval = 0x40000f6c;
|
||||
tsf_hal_get_time = 0x40000f70;
|
||||
tsf_hal_get_timer_target = 0x40000f74;
|
||||
tsf_hal_is_tsf_enabled = 0x40000f78;
|
||||
tsf_hal_map_tbtt_target_to_rx_frame = 0x40000f7c;
|
||||
tsf_hal_map_tsf_to_bssid = 0x40000f80;
|
||||
tsf_hal_set_counter_value = 0x40000f84;
|
||||
tsf_hal_set_modem_wakeup_early_time = 0x40000f88;
|
||||
tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_disable = 0x40000f8c;
|
||||
tsf_hal_set_rx_beacon_abort_tsf_time_deviation_sync_enable = 0x40000f90;
|
||||
tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_disable = 0x40000f94;
|
||||
tsf_hal_set_rx_beacon_fail_tsf_time_deviation_sync_enable = 0x40000f98;
|
||||
tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_disable = 0x40000f9c;
|
||||
tsf_hal_set_rx_beacon_success_tsf_time_deviation_sync_enable = 0x40000fa0;
|
||||
tsf_hal_set_tbtt_disable = 0x40000fa4;
|
||||
tsf_hal_set_tbtt_early_time = 0x40000fa8;
|
||||
tsf_hal_set_tbtt_enable = 0x40000fac;
|
||||
tsf_hal_set_tbtt_interval = 0x40000fb0;
|
||||
tsf_hal_set_tbtt_intr_disable = 0x40000fb4;
|
||||
tsf_hal_set_tbtt_intr_enable = 0x40000fb8;
|
||||
tsf_hal_set_tbtt_modem_wakeup_disable = 0x40000fbc;
|
||||
tsf_hal_set_tbtt_modem_wakeup_enable = 0x40000fc0;
|
||||
tsf_hal_set_tbtt_rf_ctrl_disable = 0x40000fc4;
|
||||
tsf_hal_set_tbtt_rf_ctrl_enable = 0x40000fc8;
|
||||
tsf_hal_set_tbtt_rf_ctrl_wait_cycles = 0x40000fcc;
|
||||
tsf_hal_set_tbtt_soc_wakeup_disable = 0x40000fd0;
|
||||
tsf_hal_set_tbtt_soc_wakeup_enable = 0x40000fd4;
|
||||
tsf_hal_set_tbtt_start_time = 0x40000fd8;
|
||||
tsf_hal_set_time = 0x40000fdc;
|
||||
tsf_hal_set_timer_disable = 0x40000fe0;
|
||||
tsf_hal_set_timer_enable = 0x40000fe4;
|
||||
tsf_hal_set_timer_intr_disable = 0x40000fe8;
|
||||
tsf_hal_set_timer_intr_enable = 0x40000fec;
|
||||
tsf_hal_set_timer_modem_wakeup_disable = 0x40000ff0;
|
||||
tsf_hal_set_timer_modem_wakeup_enable = 0x40000ff4;
|
||||
tsf_hal_set_timer_rf_ctrl_disable = 0x40000ff8;
|
||||
tsf_hal_set_timer_rf_ctrl_enable = 0x40000ffc;
|
||||
tsf_hal_set_timer_rf_ctrl_wait_cycles = 0x40001000;
|
||||
tsf_hal_set_timer_soc_wakeup_disable = 0x40001004;
|
||||
tsf_hal_set_timer_soc_wakeup_enable = 0x40001008;
|
||||
tsf_hal_set_timer_target = 0x4000100c;
|
||||
tsf_hal_set_tsf_disable = 0x40001010;
|
||||
tsf_hal_set_tsf_enable = 0x40001014;
|
||||
tsf_hal_set_tsf_time_deviation = 0x40001018;
|
||||
tsf_hal_set_tsf_time_deviation_sync_disable = 0x4000101c;
|
||||
tsf_hal_set_tsf_time_deviation_sync_enable = 0x40001020;
|
||||
tsf_hal_unmap_tbtt_target_to_rx_frame = 0x40001024;
|
||||
ppSelectTxFormat = 0x40001028;
|
||||
ppCertSetRate = 0x4000102c;
|
||||
ppHEAMPDU2Normal = 0x40001030;
|
||||
ppCalTxHEAMPDULength = 0x40001034;
|
||||
ppCalTxHESMPDULength = 0x40001038;
|
||||
rcGetRate = 0x4000103c;
|
||||
rcGetDCMMaxRate = 0x40001040;
|
||||
rcGetSMPDURate = 0x40001044;
|
||||
ppDirectRecycleAmpdu = 0x40001048;
|
||||
ppCheckTxHEAMPDUlength = 0x4000104c;
|
||||
rx11AXRate2AMPDULimit = 0x40001050;
|
||||
ppRegressAmpdu = 0x40001054;
|
||||
ppCalDeliNum = 0x40001058;
|
||||
ppAdd2AMPDUTail = 0x4000105c;
|
||||
esp_test_disable_tx_statistics = 0x40001060;
|
||||
esp_test_enable_tx_statistics = 0x40001064;
|
||||
esp_test_clr_tx_statistics = 0x40001068;
|
||||
esp_test_get_tx_statistics = 0x4000106c;
|
||||
esp_test_clr_tx_tb_statistics = 0x40001070;
|
||||
esp_test_get_tx_tb_statistics = 0x40001074;
|
||||
test_tx_fail_statistics = 0x40001078;
|
||||
test_tx_succ_statistics = 0x4000107c;
|
||||
esp_test_tx_process_complete = 0x40001080;
|
||||
esp_test_tx_process_txq_state = 0x40001084;
|
||||
esp_test_tx_enab_statistics = 0x40001088;
|
||||
esp_test_tx_tb_complete = 0x4000108c;
|
||||
esp_test_tx_count_retry = 0x40001090;
|
||||
esp_test_tx_count_collision = 0x40001094;
|
||||
esp_test_tx_count_timeout = 0x40001098;
|
||||
hal_enable_tx_statistics = 0x4000109c;
|
||||
test_rx_process_complete_noeb = 0x400010a0;
|
||||
test_rx_process_complete_retry = 0x400010a4;
|
||||
esp_test_rx_process_complete = 0x400010a8;
|
||||
esp_test_clr_rx_statistics = 0x400010ac;
|
||||
esp_test_get_rx_statistics = 0x400010b0;
|
||||
test_free_rx_statistics = 0x400010b4;
|
||||
esp_test_set_rx_error_occurs = 0x400010b8;
|
||||
esp_test_get_rx_error_occurs = 0x400010bc;
|
||||
esp_test_clr_rx_error_occurs = 0x400010c0;
|
||||
esp_test_disable_rx_statistics = 0x400010c4;
|
||||
esp_test_enable_rx_statistics = 0x400010c8;
|
||||
hal_enable_rx_statistics = 0x400010cc;
|
||||
get_user_num = 0x400010d0;
|
||||
mumimo_spatial_cfg_get_nsts = 0x400010d4;
|
||||
mumimo_spatial_cfg_get_nsts_tot = 0x400010d8;
|
||||
test_mumimo_get_heltf_num = 0x400010dc;
|
||||
test_mimo_update_user_info = 0x400010e0;
|
||||
test_parse_rx_mu_mimo = 0x400010e4;
|
||||
test_nonmimo_update_user_info = 0x400010e8;
|
||||
test_parse_rx_mu_nonmimo = 0x400010ec;
|
||||
esp_test_rx_parse_mu = 0x400010f0;
|
||||
esp_test_get_rx_mu_statistics = 0x400010f4;
|
||||
esp_test_clr_rx_mu_statistics = 0x400010f8;
|
||||
esp_test_enable_rx_mu_statistics = 0x400010fc;
|
||||
esp_test_disable_rx_mu_statistics = 0x40001100;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
our_instances_ptr = 0x4004ffe0;
|
||||
pTxRx = 0x4087ff88;
|
||||
lmacConfMib_ptr = 0x4087ff84;
|
||||
our_wait_eb = 0x4087ff80;
|
||||
our_tx_eb = 0x4087ff7c;
|
||||
pp_wdev_funcs = 0x4087ff78;
|
||||
g_osi_funcs_p = 0x4087ff74;
|
||||
wDevCtrl_ptr = 0x4087ff70;
|
||||
pTxRx = 0x4087ff80;
|
||||
lmacConfMib_ptr = 0x4087ff7c;
|
||||
our_wait_eb = 0x4087ff78;
|
||||
our_tx_eb = 0x4087ff74;
|
||||
pp_wdev_funcs = 0x4087ff70;
|
||||
g_osi_funcs_p = 0x4087ff6c;
|
||||
wDevCtrl_ptr = 0x4087ff68;
|
||||
g_wdev_last_desc_reset_ptr = 0x4004ffdc;
|
||||
wDevMacSleep_ptr = 0x4087ff6c;
|
||||
g_lmac_cnt_ptr = 0x4087ff68;
|
||||
wDevMacSleep_ptr = 0x4087ff64;
|
||||
g_lmac_cnt_ptr = 0x4087ff60;
|
||||
our_controls_ptr = 0x4004ffd8;
|
||||
pp_sig_cnt_ptr = 0x4087ff64;
|
||||
g_eb_list_desc_ptr = 0x4087ff60;
|
||||
s_fragment_ptr = 0x4087ff5c;
|
||||
if_ctrl_ptr = 0x4087ff58;
|
||||
g_intr_lock_mux = 0x4087ff54;
|
||||
g_wifi_global_lock = 0x4087ff50;
|
||||
s_wifi_queue = 0x4087ff4c;
|
||||
pp_task_hdl = 0x4087ff48;
|
||||
s_pp_task_create_sem = 0x4087ff44;
|
||||
s_pp_task_del_sem = 0x4087ff40;
|
||||
g_wifi_menuconfig_ptr = 0x4087ff3c;
|
||||
xphyQueue = 0x4087ff38;
|
||||
ap_no_lr_ptr = 0x4087ff34;
|
||||
rc11BSchedTbl_ptr = 0x4087ff30;
|
||||
rc11NSchedTbl_ptr = 0x4087ff2c;
|
||||
rcLoRaSchedTbl_ptr = 0x4087ff28;
|
||||
BasicOFDMSched_ptr = 0x4087ff24;
|
||||
trc_ctl_ptr = 0x4087ff20;
|
||||
g_pm_cnt_ptr = 0x4087ff1c;
|
||||
g_pm_ptr = 0x4087ff18;
|
||||
g_pm_cfg_ptr = 0x4087ff14;
|
||||
g_esp_mesh_quick_funcs_ptr = 0x4087ff10;
|
||||
g_txop_queue_status_ptr = 0x4087ff0c;
|
||||
g_mac_sleep_en_ptr = 0x4087ff08;
|
||||
g_mesh_is_root_ptr = 0x4087ff04;
|
||||
g_mesh_topology_ptr = 0x4087ff00;
|
||||
g_mesh_init_ps_type_ptr = 0x4087fefc;
|
||||
g_mesh_is_started_ptr = 0x4087fef8;
|
||||
g_config_func = 0x4087fef4;
|
||||
g_net80211_tx_func = 0x4087fef0;
|
||||
g_timer_func = 0x4087feec;
|
||||
s_michael_mic_failure_cb = 0x4087fee8;
|
||||
wifi_sta_rx_probe_req = 0x4087fee4;
|
||||
g_tx_done_cb_func = 0x4087fee0;
|
||||
g_per_conn_trc = 0x4087fe94;
|
||||
s_encap_amsdu_func = 0x4087fe90;
|
||||
s_mplen_high_bitmap = 0x4087fce8;
|
||||
s_mplen_low_bitmap = 0x4087fcf8;
|
||||
rx_beacon_count = 0x4087fe8c;
|
||||
rx_beacon_sw_parse = 0x4087fe88;
|
||||
rx_beacon_hw_parse = 0x4087fe84;
|
||||
rx_beacon_tim_count = 0x4087fe80;
|
||||
rx_beacon_tim_udata = 0x4087fe7c;
|
||||
rx_beacon_tim_udata_bitmap = 0x4087fe78;
|
||||
rx_beacon_tim_bdata = 0x4087fe74;
|
||||
rx_beacon_tim_bdata_bitmapctl = 0x4087fe70;
|
||||
rx_beacon_tim_bdata_bitmap_trans = 0x4087fe6c;
|
||||
rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4087fe68;
|
||||
rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4087fe64;
|
||||
rx_beacon_dtim_tim = 0x4087fe60;
|
||||
rx_beacon_dtim_tim_mcast = 0x4087fe5c;
|
||||
amdpu_delay_time_ms = 0x4087fce4;
|
||||
ampdu_delay_packet = 0x4087fce0;
|
||||
ampdu_delay = 0x4087fe59;
|
||||
first_ampdu = 0x4087fe58;
|
||||
s_ht_ampdu_density_us = 0x4087fcde;
|
||||
s_ht_ampdu_density = 0x4087fcdd;
|
||||
s_running_phy_type = 0x4087fcdc;
|
||||
complete_ena_tb_seqno = 0x4087fe54;
|
||||
complete_ena_tb_final = 0x4087fe50;
|
||||
complete_ena_tb_count = 0x4087fe4c;
|
||||
s_itwt_state = 0x4087fe48;
|
||||
g_dbg_interp_tsf = 0x4087fe44;
|
||||
g_dbg_interp_tsf_end = 0x4087fe40;
|
||||
g_dbg_closrf_tsf = 0x4087fe3c;
|
||||
g_dbg_closrf_idx = 0x4087fe38;
|
||||
g_dbg_closrf_blk = 0x4087fe34;
|
||||
queue_history = 0x4087fd6c;
|
||||
queue_history_idx = 0x4087fd68;
|
||||
s_he_min_len_bytes = 0x4087fd2c;
|
||||
s_he_dcm_min_len_bytes = 0x4087fd0c;
|
||||
s_mplen_vi_bitmap = 0x4087fd08;
|
||||
s_mplen_low_bitmap = 0x4087fcf8;
|
||||
s_mplen_high_bitmap = 0x4087fce8;
|
||||
pp_sig_cnt_ptr = 0x4087ff5c;
|
||||
g_eb_list_desc_ptr = 0x4087ff58;
|
||||
s_fragment_ptr = 0x4087ff54;
|
||||
if_ctrl_ptr = 0x4087ff50;
|
||||
g_intr_lock_mux = 0x4087ff4c;
|
||||
g_wifi_global_lock = 0x4087ff48;
|
||||
s_wifi_queue = 0x4087ff44;
|
||||
pp_task_hdl = 0x4087ff40;
|
||||
s_pp_task_create_sem = 0x4087ff3c;
|
||||
s_pp_task_del_sem = 0x4087ff38;
|
||||
g_wifi_menuconfig_ptr = 0x4087ff34;
|
||||
xphyQueue = 0x4087ff30;
|
||||
ap_no_lr_ptr = 0x4087ff2c;
|
||||
rc11BSchedTbl_ptr = 0x4087ff28;
|
||||
rc11NSchedTbl_ptr = 0x4087ff24;
|
||||
rcLoRaSchedTbl_ptr = 0x4087ff20;
|
||||
BasicOFDMSched_ptr = 0x4087ff1c;
|
||||
trc_ctl_ptr = 0x4087ff18;
|
||||
g_pm_cnt_ptr = 0x4087ff14;
|
||||
g_pm_ptr = 0x4087ff10;
|
||||
g_pm_cfg_ptr = 0x4087ff0c;
|
||||
g_esp_mesh_quick_funcs_ptr = 0x4087ff08;
|
||||
g_txop_queue_status_ptr = 0x4087ff04;
|
||||
g_mac_sleep_en_ptr = 0x4087ff00;
|
||||
g_mesh_is_root_ptr = 0x4087fefc;
|
||||
g_mesh_topology_ptr = 0x4087fef8;
|
||||
g_mesh_init_ps_type_ptr = 0x4087fef4;
|
||||
g_mesh_is_started_ptr = 0x4087fef0;
|
||||
g_config_func = 0x4087feec;
|
||||
g_net80211_tx_func = 0x4087fee8;
|
||||
g_timer_func = 0x4087fee4;
|
||||
s_michael_mic_failure_cb = 0x4087fee0;
|
||||
wifi_sta_rx_probe_req = 0x4087fedc;
|
||||
g_tx_done_cb_func = 0x4087fed8;
|
||||
g_per_conn_trc = 0x4087fe8c;
|
||||
s_encap_amsdu_func = 0x4087fe88;
|
||||
rx_beacon_count = 0x4087fe84;
|
||||
rx_beacon_sw_parse = 0x4087fe80;
|
||||
rx_beacon_hw_parse = 0x4087fe7c;
|
||||
rx_beacon_tim_count = 0x4087fe78;
|
||||
rx_beacon_tim_udata = 0x4087fe74;
|
||||
rx_beacon_tim_udata_bitmap = 0x4087fe70;
|
||||
rx_beacon_tim_bdata = 0x4087fe6c;
|
||||
rx_beacon_tim_bdata_bitmapctl = 0x4087fe68;
|
||||
rx_beacon_tim_bdata_bitmap_trans = 0x4087fe64;
|
||||
rx_beacon_tim_bdata_bitmap_mbssid_self = 0x4087fe60;
|
||||
rx_beacon_tim_bdata_bitmap_mbssid_other = 0x4087fe5c;
|
||||
rx_beacon_dtim_tim = 0x4087fe58;
|
||||
rx_beacon_dtim_tim_mcast = 0x4087fe54;
|
||||
amdpu_delay_time_ms = 0x4087fd08;
|
||||
ampdu_delay_packet = 0x4087fd04;
|
||||
ampdu_delay = 0x4087fe51;
|
||||
first_ampdu = 0x4087fe50;
|
||||
s_ht_ampdu_density_us = 0x4087fd02;
|
||||
s_ht_ampdu_density = 0x4087fd01;
|
||||
s_running_phy_type = 0x4087fd00;
|
||||
complete_ena_tb_seqno = 0x4087fe4c;
|
||||
complete_ena_tb_final = 0x4087fe48;
|
||||
complete_ena_tb_count = 0x4087fe44;
|
||||
s_itwt_state = 0x4087fe40;
|
||||
g_dbg_interp_tsf = 0x4087fe3c;
|
||||
g_dbg_interp_tsf_end = 0x4087fe38;
|
||||
g_dbg_closrf_tsf = 0x4087fe34;
|
||||
g_dbg_closrf_idx = 0x4087fe30;
|
||||
g_dbg_closrf_blk = 0x4087fe2c;
|
||||
s_he_min_len_bytes = 0x4087fdf0;
|
||||
s_he_dcm_min_len_bytes = 0x4087fdd0;
|
||||
s_mplen_low_bitmap = 0x4087fdc0;
|
||||
s_mplen_high_bitmap = 0x4087fdb0;
|
||||
s_mplen_vi_bitmap = 0x4087fdac;
|
||||
s_mplen_bk_bitmap = 0x4087fda8;
|
||||
esp_wifi_cert_tx_mcs = 0x4087fcfc;
|
||||
esp_wifi_cert_tx_bcc = 0x4087fcf8;
|
||||
esp_wifi_cert_tx_ltf = 0x4087fcf4;
|
||||
esp_wifi_cert_tx_gi = 0x4087fcf0;
|
||||
esp_wifi_cert_tx_nss = 0x4087fcec;
|
||||
esp_test_tx_statistics_aci_bitmap = 0x4087fda4;
|
||||
esp_test_tx_statistics = 0x4087fd94;
|
||||
esp_test_tx_tb_statistics = 0x4087fd84;
|
||||
esp_test_tx_fail_statistics = 0x4087fd24;
|
||||
esp_test_rx_statistics = 0x4087fd1c;
|
||||
esp_test_rx_mu_statistics = 0x4087fd18;
|
||||
esp_test_mu_print_ru_allocation = 0x4087fd14;
|
||||
sigb_ru_allocation_user_num = 0x4004ffc8;
|
||||
sigb_common_ru_allocation = 0x4004ff38;
|
||||
mu_mimo_special_cfg_user_num_2 = 0x4004fee8;
|
||||
mu_mimo_special_cfg_user_num_3 = 0x4004fe80;
|
||||
mu_mimo_special_cfg_user_num_4 = 0x4004fe28;
|
||||
mu_mimo_special_cfg_user_num_5 = 0x4004fdf0;
|
||||
mu_mimo_special_cfg_user_num_6 = 0x4004fdd0;
|
||||
mu_mimo_special_cfg_user_num_7 = 0x4004fdc0;
|
||||
mu_mimo_special_cfg_user_num_8 = 0x4004fdb8;
|
||||
esp_test_rx_error_occurs = 0x4087fd10;
|
||||
g_pp_tx_pkt_num = 0x4087fd0c;
|
||||
he_max_apep_length = 0x4004fd40;
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.rvfp.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
/* ROM function interface esp32c6.rom.spiflash.ld for esp32c6
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 49b5eec776610e08f2ed989e3ffc2ba0
|
||||
* Generated from ./target/esp32c6/interface-esp32c6.yml md5sum 06c13e133e0743d09b87aba30d3e213b
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
|
||||
@ -24,23 +24,31 @@
|
||||
* - Most other malloc caps only fit in one region anyway.
|
||||
*
|
||||
*/
|
||||
const soc_memory_type_desc_t soc_memory_types[] = {
|
||||
|
||||
/* Index of memory in `soc_memory_types[]` */
|
||||
enum {
|
||||
SOC_MEMORY_TYPE_DRAM = 0,
|
||||
SOC_MEMORY_TYPE_STACK_DRAM = 1,
|
||||
SOC_MEMORY_TYPE_DIRAM = 2,
|
||||
SOC_MEMORY_TYPE_RTCRAM = 3,
|
||||
SOC_MEMORY_TYPE_NUM,
|
||||
};
|
||||
|
||||
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
|
||||
// Type 0: DRAM
|
||||
{ "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
|
||||
// Type 1: DRAM used for startup stacks
|
||||
{ "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true},
|
||||
// Type 2: DRAM which has an alias on the I-port
|
||||
{ "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: IRAM
|
||||
{ "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
|
||||
// Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
|
||||
{ "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
|
||||
// Type 3: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM
|
||||
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false},
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 0
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM
|
||||
#else
|
||||
#define SOC_MEMORY_TYPE_DEFAULT 2
|
||||
#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM
|
||||
#endif
|
||||
|
||||
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
|
||||
@ -52,15 +60,21 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
|
||||
* this list should always be sorted from low to high by start address.
|
||||
*
|
||||
*/
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //Block 4, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //Block 5, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //Block 6, can be remapped to ROM, can be used as trace memory
|
||||
{ 0x40860000, 0x20000, 1, 0x40860000}, //Block 9, can be used as trace memory
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x4000, 4, 0}, //Fast RTC memory
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Register the shared buffer area of the last memory block into the heap during heap initialization
|
||||
*/
|
||||
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
|
||||
|
||||
const soc_memory_region_t soc_memory_regions[] = {
|
||||
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory
|
||||
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory
|
||||
{ 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level2, can be used as trace memory
|
||||
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory
|
||||
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
|
||||
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
|
||||
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0}, //LPRAM
|
||||
#endif
|
||||
};
|
||||
|
||||
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
|
||||
|
||||
@ -213,8 +213,8 @@
|
||||
#define SOC_DEBUG_HIGH 0x28000000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x4087c770
|
||||
|
||||
#define SOC_ROM_STACK_START 0x4087e610
|
||||
#define SOC_ROM_STACK_SIZE 0x2000
|
||||
|
||||
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
|
||||
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user