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driver: Minor update for esp32c6

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Leave TODO for esp_adc and legacy adc driver
HAL/SOC update for spi and i2s
This commit is contained in:
wuzhenghui 2022-07-08 17:09:16 +08:00 committed by Song Ruo Jing
parent fbc19fad70
commit 5115e31175
9 changed files with 48 additions and 25 deletions
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4
components/driver/deprecated/driver/adc_types_legacy.h
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@ -61,7 +61,7 @@ typedef enum {
ADC1_CHANNEL_9, /*!< ADC1 channel 9 is GPIO10 */
ADC1_CHANNEL_MAX,
} adc1_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
typedef enum {
ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO0 */
ADC1_CHANNEL_1, /*!< ADC1 channel 1 is GPIO1 */
@ -86,7 +86,7 @@ typedef enum {
ADC2_CHANNEL_9, /*!< ADC2 channel 9 is GPIO26 (ESP32), GPIO20 (ESP32-S2) */
ADC2_CHANNEL_MAX,
} adc2_channel_t;
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5310
typedef enum {
ADC2_CHANNEL_0 = 0, /*!< ADC2 channel 0 is GPIO5 */
ADC2_CHANNEL_MAX,

9
components/esp_adc/CMakeLists.txt
View File

@ -27,6 +27,15 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/deprecated/${target}/esp_adc_cal_legacy.c
list(APPEND srcs "deprecated/${target}/esp_adc_cal_legacy.c")
endif()
# ESP32C6-TODO
if(CONFIG_IDF_TARGET_ESP32C6)
list(REMOVE_ITEM srcs
"adc_cali_curve_fitting.c" # TODO: IDF-5312
"adc_oneshot.c" # TODO: IDF-5310
"adc_common.c"
)
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
PRIV_REQUIRES driver efuse

15
components/esp_adc/esp32c6/include/adc_cali_schemes.h Normal file
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@ -0,0 +1,15 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file adc_cali_schemes.h
*
* @brief Supported calibration schemes
*/
//Now no scheme supported

28
components/hal/esp32c6/include/hal/i2s_ll.h
View File

@ -48,7 +48,7 @@ typedef struct {
static inline void i2s_ll_enable_clock(i2s_dev_t *hw)
{
// The clock gate enabling is moved to `periph_module_enable`
(void *)hw;
(void)hw;
}
/**
@ -59,7 +59,7 @@ static inline void i2s_ll_enable_clock(i2s_dev_t *hw)
static inline void i2s_ll_disable_clock(i2s_dev_t *hw)
{
// The clock gate disabling is moved to `periph_module_disable`
(void *)hw;
(void)hw;
}
/**
@ -69,7 +69,7 @@ static inline void i2s_ll_disable_clock(i2s_dev_t *hw)
*/
static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 1;
}
@ -80,7 +80,7 @@ static inline void i2s_ll_tx_enable_clock(i2s_dev_t *hw)
*/
static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 1;
}
@ -91,7 +91,7 @@ static inline void i2s_ll_rx_enable_clock(i2s_dev_t *hw)
*/
static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_en = 0;
}
@ -102,7 +102,7 @@ static inline void i2s_ll_tx_disable_clock(i2s_dev_t *hw)
*/
static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_en = 0;
}
@ -113,7 +113,7 @@ static inline void i2s_ll_rx_disable_clock(i2s_dev_t *hw)
*/
static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 0;
}
@ -124,7 +124,7 @@ static inline void i2s_ll_mclk_bind_to_tx_clk(i2s_dev_t *hw)
*/
static inline void i2s_ll_mclk_bind_to_rx_clk(i2s_dev_t *hw)
{
(void *)hw;
(void)hw;
PCR.i2s_rx_clkm_conf.i2s_mclk_sel = 1;
}
@ -202,7 +202,7 @@ static inline void i2s_ll_rx_reset_fifo(i2s_dev_t *hw)
*/
static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void *)hw;
(void)hw;
switch (src)
{
case I2S_CLK_SRC_XTAL:
@ -225,7 +225,7 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
*/
static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
{
(void *)hw;
(void)hw;
switch (src)
{
case I2S_CLK_SRC_XTAL:
@ -262,7 +262,7 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void *)hw;
(void)hw;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_x = x;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_y = y;
PCR.i2s_tx_clkm_div_conf.i2s_tx_clkm_div_z = z;
@ -280,7 +280,7 @@ static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
*/
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{
(void *)hw;
(void)hw;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_x = x;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_y = y;
PCR.i2s_rx_clkm_div_conf.i2s_rx_clkm_div_z = z;
@ -297,7 +297,7 @@ static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
{
(void *)hw;
(void)hw;
int ma = 0;
int mb = 0;
int denominator = 1;
@ -372,7 +372,7 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
*/
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
{
(void *)hw;
(void)hw;
int ma = 0;
int mb = 0;
int denominator = 1;

3
components/hal/esp32c6/include/hal/timer_ll.h
View File

@ -41,9 +41,6 @@ static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num,
case GPTIMER_CLK_SRC_APB:
clk_id = 1;
break;
case GPTIMER_CLK_SRC_RC_FAST:
clk_id = 2;
break;
default:
HAL_ASSERT(false);
break;

8
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@ -183,10 +183,6 @@ config SOC_CPU_HAS_FLEXIBLE_INTC
bool
default y
config SOC_RV32A_SUPPORTED
bool
default y
config SOC_INT_PLIC_SUPPORTED
bool
default y
@ -495,6 +491,10 @@ config SOC_SPI_PERIPH_NUM
int
default 2
config SOC_SPI_MAX_CS_NUM
int
default 6
config SOC_SPI_MAXIMUM_BUFFER_SIZE
int
default 64

2
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@ -5,6 +5,8 @@
*/
#pragma once
#include "sdkconfig.h" // TODO: IDF-5973
#ifdef __cplusplus
extern "C" {
#endif

2
components/soc/esp32c6/include/soc/soc_caps.h
View File

@ -112,7 +112,6 @@
#define SOC_CPU_CORES_NUM (1U)
#define SOC_CPU_INTR_NUM 32
#define SOC_CPU_HAS_FLEXIBLE_INTC 1
#define SOC_RV32A_SUPPORTED 1
#define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller
#define SOC_CPU_BREAKPOINTS_NUM 4
@ -276,6 +275,7 @@
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6
#define SOC_SPI_MAX_CS_NUM 6
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64

2
components/soc/esp32c6/spi_periph.c
View File

@ -36,7 +36,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spiq_in = FSPIQ_IN_IDX,
.spiwp_in = FSPIWP_IN_IDX,
.spihd_in = FSPIHD_IN_IDX,
.spics_out = {FSPICS0_OUT_IDX},
.spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX, FSPICS3_OUT_IDX, FSPICS4_OUT_IDX, FSPICS5_OUT_IDX},
.spics_in = FSPICS0_IN_IDX,
.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,