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Merge branch 'bugfix/fix_esp32s3_cache_data_memory_wrong_attr_backport_v5.0' into 'release/v5.0'

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bugfix: esp32s3 DCache data memory is retention dma inaccessible (backport v5.0)

See merge request espressif/esp-idf!19473
This commit is contained in:
morris 2022-08-10 17:56:10 +08:00
commit 5090955250
3 changed files with 7 additions and 15 deletions
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12
components/esp_hw_support/sleep_retention.c
View File

@ -37,8 +37,6 @@ static DRAM_ATTR __attribute__((unused)) sleep_retention_t s_retention;
#if SOC_PM_SUPPORT_TAGMEM_PD
#define TAGMEM_PD_MEM_TYPE_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
static int cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size)
{
@ -123,7 +121,7 @@ static esp_err_t esp_sleep_tagmem_pd_low_init(bool enable)
int tagmem_sz = cache_tagmem_retention_setup(code_start, code_size, data_start, data_size);
void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN,
tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE,
TAGMEM_PD_MEM_TYPE_CAPS);
MALLOC_CAP_RETENTION);
if (buf) {
memset(buf, 0, tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE);
s_retention.retent.tagmem.link_addr = rtc_cntl_hal_dma_link_init(buf,
@ -157,19 +155,13 @@ static esp_err_t esp_sleep_tagmem_pd_low_init(bool enable)
#if SOC_PM_SUPPORT_CPU_PD
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
#define CPU_PD_MEM_TYPE_CAPS (MALLOC_CAP_RETENTION | MALLOC_CAP_DEFAULT)
#else
#define CPU_PD_MEM_TYPE_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
#endif
esp_err_t esp_sleep_cpu_pd_low_init(bool enable)
{
if (enable) {
if (s_retention.retent.cpu_pd_mem == NULL) {
void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN,
SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE,
CPU_PD_MEM_TYPE_CAPS);
MALLOC_CAP_RETENTION);
if (buf) {
memset(buf, 0, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE);
s_retention.retent.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf,

2
components/heap/include/esp_heap_caps.h
View File

@ -33,7 +33,7 @@ extern "C" {
#define MALLOC_CAP_INTERNAL (1<<11) ///< Memory must be internal; specifically it should not disappear when flash/spiram cache is switched off
#define MALLOC_CAP_DEFAULT (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call
#define MALLOC_CAP_IRAM_8BIT (1<<13) ///< Memory must be in IRAM and allow unaligned access
#define MALLOC_CAP_RETENTION (1<<14)
#define MALLOC_CAP_RETENTION (1<<14) ///< Memory must be able to accessed by retention DMA
#define MALLOC_CAP_RTCRAM (1<<15) ///< Memory must be in RTC fast memory
#define MALLOC_CAP_INVALID (1<<31) ///< Memory can't be used / list end marker

8
components/heap/port/esp32s3/memory_layout.c
View File

@ -43,9 +43,9 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
// Type 0: DRAM
[SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false},
// Type 1: DRAM used for startup stacks
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
[SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true},
// Type 2: DRAM which has an alias on the I-port
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false},
[SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC | MALLOC_CAP_RETENTION}, true, false},
// Type 3: IRAM
[SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
// Type 4: SPI SRAM data
@ -87,10 +87,10 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy,
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task
#if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB
{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM
{ 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM, DMA is accessible but retention DMA is inaccessible
#endif
#if CONFIG_ESP32S3_DATA_CACHE_16KB
{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_NODMARAM, 0},
{ 0x3C000000, 0x4000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 10, DRAM, DMA is accessible but retention DMA is inaccessible
#endif
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory