docs(esp_eth): added warning to not use ESP32 as ETH CLK source with WiFi

components/esp_eth/Kconfig

@@ -62,13 +62,11 @@ menu "Ethernet"
                 bool "Output RMII clock from GPIO0 (Experimental!)"
                 default n
                 help
-                    GPIO0 can be set to output a pre-divided PLL clock (test only!).
+                    GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure
-                    Enabling this option will configure GPIO0 to output a 50MHz clock.
+                    GPIO0 to output a 50MHz clock. In fact this clock doesn't have directly relationship with
-                    In fact this clock doesn't have directly relationship with EMAC peripheral.
+                    EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
-                    Sometimes this clock won't work well with your PHY chip. You might need to
+                    WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
-                    add some extra devices after GPIO0 (e.g. inverter).
+                    as it would result in clock instability!
-                    Note that outputting RMII clock on GPIO0 is an experimental practice.
-                    If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
 
             if !ETH_RMII_CLK_OUTPUT_GPIO0
                 config ETH_RMII_CLK_OUT_GPIO
@@ -78,6 +76,8 @@ menu "Ethernet"
                     default 17
                     help
                         Set the GPIO number to output RMII Clock.
+                        WARNING: If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output
+                        as it would result in clock instability!
             endif # !ETH_RMII_CLK_OUTPUT_GPIO0
         endif # ETH_RMII_CLK_OUTPUT
 

components/esp_eth/include/esp_eth_mac_esp.h

@@ -51,6 +51,8 @@ typedef enum {
 /**
  * @brief RMII Clock GPIO number Options for ESP32
  *
+ * @warning If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output as it would result in clock instability.
+ *
  */
 typedef enum {
     /**
@@ -64,10 +66,8 @@ typedef enum {
     /**
      * @brief Output RMII Clock from internal APLL Clock available at GPIO0
      *
-     * @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
+     * @note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock.
-     * In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
+     * In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
-     * You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
-     * If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
      *
      */
     EMAC_APPL_CLK_OUT_GPIO = 0,

docs/en/api-reference/network/esp_eth.rst

@@ -165,6 +165,9 @@ The Ethernet driver is composed of two parts: MAC and PHY.
 
             * Force the PHY device to reset status (as the case **a** in the picture). **This could fail for some PHY device** (i.e., it still outputs signals to GPIO0 even in reset state).
 
+        .. warning::
+            If you want the **Ethernet to work with WiFi**, don’t select ESP32 as source of ``REF_CLK`` as it would result in ``REF_CLK`` instability. Either disable WiFi or use a PHY or an external oscillator as the ``REF_CLK`` source.
+
     .. only:: not esp32
 
         .. note::