diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/src/bootloader_flash_config_esp32c3.c index d140fa0ff6..065fcb6a80 100644 --- a/components/bootloader_support/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/src/bootloader_flash_config_esp32c3.c @@ -24,7 +24,7 @@ #include "soc/efuse_reg.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" -#include "soc/spi_caps.h" +#include "soc/soc_caps.h" #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" diff --git a/components/esp32c3/esp_ds.c b/components/esp32c3/esp_ds.c index 03b2f2fffb..3dbaa79dc5 100644 --- a/components/esp32c3/esp_ds.c +++ b/components/esp32c3/esp_ds.c @@ -131,7 +131,7 @@ esp_err_t esp_ds_start_sign(const void *message, // check encryption key from HMAC int64_t start_time = esp_timer_get_time(); while (ds_ll_busy() != 0) { - if ((esp_timer_get_time() - start_time) > DS_KEY_CHECK_MAX_WAIT_US) { + if ((esp_timer_get_time() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) { ds_disable_release(); return ESP32C3_ERR_HW_CRYPTO_DS_INVALID_KEY; } diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 64a8c49d15..67c3a16533 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -342,7 +342,7 @@ static void IRAM_ATTR suspend_uarts(void) uint32_t uart_fsm = 0; do { uart_fsm = uart_ll_get_fsm_status(i); - } while (!(uart_fsm == UART_FSM_IDLE || uart_fsm == UART_FSM_TX_WAIT_SEND)); + } while (!(uart_fsm == UART_LL_FSM_IDLE || uart_fsm == UART_LL_FSM_TX_WAIT_SEND)); #else while (uart_ll_get_fsm_status(i) != 0) {} #endif @@ -368,13 +368,13 @@ esp_err_t esp_sleep_cpu_pd_low_init(bool enable) { if (enable) { if (s_config.cpu_pd_mem == NULL) { - void *buf = heap_caps_aligned_alloc(RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN, - RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE, + void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN, + SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE, MALLOC_CAP_RETENTION | MALLOC_CAP_DEFAULT); if (buf) { - memset(buf, 0, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE); + memset(buf, 0, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE); s_config.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf, - buf + RTC_HAL_DMA_LINK_NODE_SIZE, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL); + buf + RTC_HAL_DMA_LINK_NODE_SIZE, SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL); } else { return ESP_ERR_NO_MEM; } diff --git a/components/hal/esp32c3/include/hal/cpu_ll.h b/components/hal/esp32c3/include/hal/cpu_ll.h index 1ac07fdab0..4e9d449409 100644 --- a/components/hal/esp32c3/include/hal/cpu_ll.h +++ b/components/hal/esp32c3/include/hal/cpu_ll.h @@ -15,7 +15,7 @@ #include -#include "soc/cpu_caps.h" +#include "soc/soc_caps.h" #include "esp_bit_defs.h" #include "soc/assist_debug_reg.h" #include "esp_attr.h" diff --git a/components/hal/esp32c3/include/hal/ds_ll.h b/components/hal/esp32c3/include/hal/ds_ll.h index 933c1573b7..fd98de367f 100644 --- a/components/hal/esp32c3/include/hal/ds_ll.h +++ b/components/hal/esp32c3/include/hal/ds_ll.h @@ -24,7 +24,7 @@ #include #include "soc/hwcrypto_reg.h" -#include "soc/ds_caps.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -69,7 +69,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void) */ static inline void ds_ll_configure_iv(const uint32_t *iv) { - for (size_t i = 0; i < (DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) { + for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) { REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]); } } @@ -99,9 +99,9 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p */ typedef struct { uint32_t addr; size_t len; } frag_t; const frag_t frags[] = { - {DS_C_Y_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8}, - {DS_C_M_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8}, - {DS_C_RB_BASE, DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_Y_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_M_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, + {DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8}, {DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE}, }; const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t); diff --git a/components/hal/esp32c3/include/hal/gdma_ll.h b/components/hal/esp32c3/include/hal/gdma_ll.h index 22410d3bdd..a1d6e1389a 100644 --- a/components/hal/esp32c3/include/hal/gdma_ll.h +++ b/components/hal/esp32c3/include/hal/gdma_ll.h @@ -17,7 +17,7 @@ #include #include "soc/gdma_struct.h" #include "soc/gdma_reg.h" -#include "soc/gdma_caps.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/mpu_ll.h b/components/hal/esp32c3/include/hal/mpu_ll.h index 9e07ee3e4b..77fa580cdb 100644 --- a/components/hal/esp32c3/include/hal/mpu_ll.h +++ b/components/hal/esp32c3/include/hal/mpu_ll.h @@ -14,7 +14,7 @@ #include -#include "soc/mpu_caps.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/uart_ll.h b/components/hal/esp32c3/include/hal/uart_ll.h index 931134f71f..c166e472f5 100644 --- a/components/hal/esp32c3/include/hal/uart_ll.h +++ b/components/hal/esp32c3/include/hal/uart_ll.h @@ -32,6 +32,9 @@ extern "C" { #define UART_LL_MIN_WAKEUP_THRESH (2) #define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask +#define UART_LL_FSM_IDLE (0x0) +#define UART_LL_FSM_TX_WAIT_SEND (0xf) + // Define UART interrupts typedef enum { UART_INTR_RXFIFO_FULL = (0x1 << 0), diff --git a/components/hal/esp32c3/rtc_cntl_hal.c b/components/hal/esp32c3/rtc_cntl_hal.c index 0c8e1eb9a3..aae2bfaed8 100644 --- a/components/hal/esp32c3/rtc_cntl_hal.c +++ b/components/hal/esp32c3/rtc_cntl_hal.c @@ -19,7 +19,7 @@ #include "esp32c3/rom/lldesc.h" #include "esp_attr.h" -#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ +#define RTC_CNTL_HAL_LINK_BUF_SIZE_MIN (SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE) /* The minimum size of dma link buffer */ typedef struct rtc_cntl_link_buf_conf { uint32_t cfg[4]; /* 4 word for dma link buffer configuration */ diff --git a/components/soc/esp32c3/include/soc/brownout_caps.h b/components/soc/esp32c3/include/soc/brownout_caps.h deleted file mode 100644 index 797d33ebb9..0000000000 --- a/components/soc/esp32c3/include/soc/brownout_caps.h +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define SOC_BROWNOUT_RESET_SUPPORTED 1 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c3/include/soc/cpu_caps.h b/components/soc/esp32c3/include/soc/cpu_caps.h deleted file mode 100644 index 2d8a80bcfc..0000000000 --- a/components/soc/esp32c3/include/soc/cpu_caps.h +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_CPU_BREAKPOINTS_NUM 8 -#define SOC_CPU_WATCHPOINTS_NUM 8 -#define SOC_CPU_HAS_FLEXIBLE_INTC 1 - -#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes diff --git a/components/soc/esp32c3/include/soc/ds_caps.h b/components/soc/esp32c3/include/soc/ds_caps.h deleted file mode 100644 index 4e5eb11010..0000000000 --- a/components/soc/esp32c3/include/soc/ds_caps.h +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -/** The maximum length of a Digital Signature in bits. */ -#define DS_SIGNATURE_MAX_BIT_LEN (3072) - -/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ -#define DS_KEY_PARAM_MD_IV_LENGTH (16) - -/** Maximum wait time for DS parameter decryption key. If overdue, then key error. - See TRM DS chapter for more details */ -#define DS_KEY_CHECK_MAX_WAIT_US (1100) diff --git a/components/soc/esp32c3/include/soc/gdma_caps.h b/components/soc/esp32c3/include/soc/gdma_caps.h deleted file mode 100644 index 0bd39fe560..0000000000 --- a/components/soc/esp32c3/include/soc/gdma_caps.h +++ /dev/null @@ -1,18 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_GDMA_GROUPS (1) -#define SOC_GDMA_PAIRS_PER_GROUP (3) diff --git a/components/soc/esp32c3/include/soc/gpio_caps.h b/components/soc/esp32c3/include/soc/gpio_caps.h deleted file mode 100644 index 8da8d2194a..0000000000 --- a/components/soc/esp32c3/include/soc/gpio_caps.h +++ /dev/null @@ -1,42 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -// ESP32-C3 has 1 GPIO peripheral -#define SOC_GPIO_PORT (1) -#define SOC_GPIO_PIN_COUNT (22) - -// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC -// On ESP32-C3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. -#define GPIO_SUPPORTS_RTC_INDEPENDENT (1) -// Force hold is a new function of ESP32-C3 -#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) -// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup -#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) - -#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) -#define RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) - -#define RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (RTC_CNTL_CPU_PD_REG_FILE_NUM * (RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) diff --git a/components/soc/esp32c3/include/soc/rtc_io_caps.h b/components/soc/esp32c3/include/soc/rtc_io_caps.h deleted file mode 100644 index 2aaa55d085..0000000000 --- a/components/soc/esp32c3/include/soc/rtc_io_caps.h +++ /dev/null @@ -1,21 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported - * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ -#define SOC_RTCIO_PIN_COUNT 0 - -#define RTCIO_LL_PIN_FUNC 0 diff --git a/components/soc/esp32c3/include/soc/sigmadelta_caps.h b/components/soc/esp32c3/include/soc/sigmadelta_caps.h deleted file mode 100644 index 7f2059a150..0000000000 --- a/components/soc/esp32c3/include/soc/sigmadelta_caps.h +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral -#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 4b58f03938..064771b83b 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -13,93 +13,15 @@ #define SOC_HMAC_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 -#include "i2c_caps.h" -#include "mpu_caps.h" -#include "sigmadelta_caps.h" -#include "uart_caps.h" -#include "brownout_caps.h" -#include "gdma_caps.h" -#include "i2s_caps.h" -#include "rtc_io_caps.h" -#include "soc_caps.h" -#include "cpu_caps.h" -#include "gpio_caps.h" -#include "ledc_caps.h" -#include "spi_caps.h" -#include "uart_caps.h" -#include "rtc_caps.h" /*-------------------------- COMMON CAPS ---------------------------------------*/ -#define SOC_SUPPORTS_SECURE_DL_MODE 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 - -/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ -#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ - -/*-------------------------- TWAI CAPS ---------------------------------------*/ -#define SOC_TWAI_BRP_MIN 2 -#define SOC_TWAI_BRP_MAX 16384 -#define SOC_TWAI_SUPPORTS_RX_STATUS 1 - -/*--------------------------- SHA CAPS ---------------------------------------*/ - -/* Max amount of bytes in a single DMA operation is 4095, - for SHA this means that the biggest safe amount of bytes is - 31 blocks of 128 bytes = 3968 -*/ -#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) -#define SOC_SHA_SUPPORT_DMA (1) - -/* The SHA engine is able to resume hashing from a user */ -#define SOC_SHA_SUPPORT_RESUME (1) - -/* Has a centralized DMA, which is shared with all peripherals */ -#define SOC_SHA_GDMA (1) - -/* Supported HW algorithms */ -#define SOC_SHA_SUPPORT_SHA1 (1) -#define SOC_SHA_SUPPORT_SHA224 (1) -#define SOC_SHA_SUPPORT_SHA256 (1) - -/*-------------------------- SYSTIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) - -/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ -#define SOC_TIMER_GROUPS (2) -#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) -#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) -#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) -#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) - -/*--------------------------- RMT CAPS ---------------------------------------*/ -#define SOC_RMT_GROUPS (1) /*!< One RMT group */ -#define SOC_RMT_TX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Transmit */ -#define SOC_RMT_RX_CANDIDATES_PER_GROUP (2) /*!< Number of channels that capable of Receive */ -#define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ -#define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ -#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ -#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ -#define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ - -/*--------------------------- RSA CAPS ---------------------------------------*/ -#define SOC_RSA_MAX_BIT_LEN (3072) - +#define SOC_SUPPORTS_SECURE_DL_MODE 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) -/*-------------------------- Flash Encryption CAPS----------------------------*/ -#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) - /* Has a centralized DMA, which is shared with all peripherals */ #define SOC_AES_GDMA (1) @@ -123,6 +45,205 @@ /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ #define SOC_APB_BACKUP_DMA (1) +/*-------------------------- BROWNOUT CAPS -----------------------------------*/ +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +/*-------------------------- CPU CAPS ----------------------------------------*/ +#define SOC_CPU_BREAKPOINTS_NUM 8 +#define SOC_CPU_WATCHPOINTS_NUM 8 +#define SOC_CPU_HAS_FLEXIBLE_INTC 1 + +#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes + +/*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ +/** The maximum length of a Digital Signature in bits. */ +#define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) + +/** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ +#define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) + +/** Maximum wait time for DS parameter decryption key. If overdue, then key error. + See TRM DS chapter for more details */ +#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) + +/*-------------------------- GDMA CAPS -------------------------------------*/ +#define SOC_GDMA_GROUPS (1) +#define SOC_GDMA_PAIRS_PER_GROUP (3) + +/*-------------------------- GPIO CAPS ---------------------------------------*/ +// ESP32-C3 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1) +#define SOC_GPIO_PIN_COUNT (22) + +// Target has no full RTC IO subsystem, so GPIO is 100% "independent" of RTC +// On ESP32-C3, Digital IOs have their own registers to control pullup/down capability, independent of RTC registers. +#define GPIO_SUPPORTS_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-C3 +#define SOC_GPIO_SUPPORT_FORCE_HOLD (1) +// GPIO0~5 on ESP32C3 can support chip deep sleep wakeup +#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) + +#define SOC_GPIO_VALID_GPIO_MASK ((1U<> 3) +#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) + +#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) + +/*-------------------------- RTCIO CAPS --------------------------------------*/ +/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported + * for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */ +#define SOC_RTCIO_PIN_COUNT 0 + +/*--------------------------- RSA CAPS ---------------------------------------*/ +#define SOC_RSA_MAX_BIT_LEN (3072) + +/*--------------------------- SHA CAPS ---------------------------------------*/ + +/* Max amount of bytes in a single DMA operation is 4095, + for SHA this means that the biggest safe amount of bytes is + 31 blocks of 128 bytes = 3968 +*/ +#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) +#define SOC_SHA_SUPPORT_DMA (1) + +/* The SHA engine is able to resume hashing from a user */ +#define SOC_SHA_SUPPORT_RESUME (1) + +/* Has a centralized DMA, which is shared with all peripherals */ +#define SOC_SHA_GDMA (1) + +/* Supported HW algorithms */ +#define SOC_SHA_SUPPORT_SHA1 (1) +#define SOC_SHA_SUPPORT_SHA224 (1) +#define SOC_SHA_SUPPORT_SHA256 (1) + +/*-------------------------- SIGMA DELTA CAPS --------------------------------*/ +#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral +#define SOC_SIGMADELTA_CHANNEL_NUM (4) // 4 channels + +/*-------------------------- SPI CAPS ----------------------------------------*/ +#define SOC_SPI_PERIPH_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 6 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 +#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) + +// Peripheral supports output given level during its "dummy phase" +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 + +#define SOC_MEMSPI_IS_INDEPENDENT 1 +#define SOC_SPI_MAX_PRE_DIVIDER 16 + +/*-------------------------- SPI MEM CAPS ---------------------------------------*/ +#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) +#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) +#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) +#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) + +/*-------------------------- SYSTIMER CAPS ----------------------------------*/ +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) + +/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ +#define SOC_TIMER_GROUPS (2) +#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1) +#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) +#define SOC_TIMER_GROUP_SUPPORT_XTAL (1) +#define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) + +/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ +#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ + +/*-------------------------- TWAI CAPS ---------------------------------------*/ +#define SOC_TWAI_BRP_MIN 2 +#define SOC_TWAI_BRP_MAX 16384 +#define SOC_TWAI_SUPPORTS_RX_STATUS 1 + +/*-------------------------- Flash Encryption CAPS----------------------------*/ +#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) + +/*-------------------------- UART CAPS ---------------------------------------*/ +// ESP32-C3 has 2 UARTs +#define SOC_UART_NUM (2) + +#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +#define SOC_UART_SUPPORT_RTC_CLK (1) +#define SOC_UART_SUPPORT_XTAL_CLK (1) + +// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled +#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) + /*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ #define SOC_WIFI_HW_TSF (1) @@ -136,13 +257,6 @@ /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) -/*-------------------------- SPI MEM CAPS ---------------------------------------*/ -#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) -#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) -#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) -#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) -#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) -#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) /*-------------------------- Power Management CAPS ----------------------------*/ #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) diff --git a/components/soc/esp32c3/include/soc/spi_caps.h b/components/soc/esp32c3/include/soc/spi_caps.h deleted file mode 100644 index fefb464f6f..0000000000 --- a/components/soc/esp32c3/include/soc/spi_caps.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#define SOC_SPI_PERIPH_NUM 2 -#define SOC_SPI_DMA_CHAN_NUM 3 -#define SOC_SPI_PERIPH_CS_NUM(i) 3 - -#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 - -//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles -#define SOC_SPI_SUPPORT_DDRCLK 1 -#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 -#define SOC_SPI_SUPPORT_CD_SIG 1 -#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 -#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 - -// Peripheral supports DIO, DOUT, QIO, or QOUT -#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) - -// Peripheral supports output given level during its "dummy phase" -#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 - -#define SOC_MEMSPI_IS_INDEPENDENT 1 - -#define SOC_SPI_MAX_PRE_DIVIDER 16 diff --git a/components/soc/esp32c3/include/soc/uart_caps.h b/components/soc/esp32c3/include/soc/uart_caps.h deleted file mode 100644 index bcbca36a3b..0000000000 --- a/components/soc/esp32c3/include/soc/uart_caps.h +++ /dev/null @@ -1,37 +0,0 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ -#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ - -#define SOC_UART_SUPPORT_RTC_CLK (1) -#define SOC_UART_SUPPORT_XTAL_CLK (1) - -// ESP32-C3 have 2 UART -#define SOC_UART_NUM (2) - -// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled -#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) -#define UART_FSM_IDLE (0x0) -#define UART_FSM_TX_WAIT_SEND (0xf) - -#ifdef __cplusplus -} -#endif