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Merge branch 'bugfix/aud-5252_v4.4' into 'release/v4.4'

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backport v4.4: fix the issue of modem hang caused by incorrect configuration of power and isolate signals

See merge request espressif/esp-idf!30097
This commit is contained in:
Jiang Jiang Jian 2024-04-15 10:44:51 +08:00
commit 5017ec08bb
8 changed files with 58 additions and 6 deletions
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13
components/esp_hw_support/port/esp32/rtc_init.c
View File

@ -20,6 +20,17 @@
void rtc_init(rtc_config_t cfg)
{
/**
* When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
* from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
* NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
* and finally triggle RTC WDT. So need to clear modem Force PD.
*
* No worry about the power consumption, Because modem Force PD will be set at the end of this function.
*/
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | RTC_CNTL_TXRF_I2C_PU |
RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU);
@ -92,7 +103,7 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
}
/* force power down wifi and bt power domain */
/* force power down modem(wifi and btdm) power domain */
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);

2
components/esp_hw_support/port/esp32/rtc_sleep.c
View File

@ -183,6 +183,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
}
if (cfg.wifi_pd_en) {
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);

13
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@ -31,6 +31,17 @@ static void set_rtc_dig_dbias(void);
void rtc_init(rtc_config_t cfg)
{
/**
* When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
* from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
* NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
* and finally triggle RTC WDT. So need to clear modem Force PD.
*
* No worry about the power consumption, Because modem Force PD will be set at the end of this function.
*/
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
@ -316,7 +327,7 @@ uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
static void set_rtc_dig_dbias()
{
/*
1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
1. a reasonable dig_dbias which by scanning pvt to make 160 CPU run successful stored in efuse;
2. also we store some value in efuse, include:
k_rtc_ldo (slope of rtc voltage & rtc_dbias);
k_dig_ldo (slope of digital voltage & digital_dbias);

4
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@ -176,11 +176,15 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
rtc_sleep_pu(pu_cfg);
}
if (cfg.wifi_pd_en) {
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
}
if (cfg.bt_pd_en) {
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO);
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);

13
components/esp_hw_support/port/esp32s2/rtc_init.c
View File

@ -29,6 +29,17 @@ static void calibrate_ocode(void);
void rtc_init(rtc_config_t cfg)
{
/**
* When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
* from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
* NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
* and finally triggle RTC WDT. So need to clear modem Force PD.
*
* No worry about the power consumption, Because modem Force PD will be set at the end of this function.
*/
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
@ -37,7 +48,7 @@ void rtc_init(rtc_config_t cfg)
// set shortest possible sleep time limit
REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
/* This power domian removed
/* This power domain removed
* set rom&ram timer
* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES);
* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES);

2
components/esp_hw_support/port/esp32s2/rtc_sleep.c
View File

@ -202,6 +202,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
}
if (cfg.wifi_pd_en) {
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);

15
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -43,6 +43,17 @@ uint32_t g_rtc_dbias_pvt_non_240m = 27;
void rtc_init(rtc_config_t cfg)
{
/**
* When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
* from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
* NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
* and finally triggle RTC WDT. So need to clear modem Force PD.
*
* No worry about the power consumption, Because modem Force PD will be set at the end of this function.
*/
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
@ -191,7 +202,7 @@ void rtc_init(rtc_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
}
/* force power down wifi and bt power domain */
/* force power down modem(wifi and ble) power domain */
SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
@ -403,7 +414,7 @@ static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)
static void rtc_set_stored_dbias(void)
{
/*
1. a reasonable dig_dbias which by scaning pvt to make 240 CPU run successful stored in efuse;
1. a reasonable dig_dbias which by scanning pvt to make 240 CPU run successful stored in efuse;
2. also we store some value in efuse, include:
k_rtc_ldo (slope of rtc voltage & rtc_dbias);
k_dig_ldo (slope of digital voltage & digital_dbias);

2
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@ -181,7 +181,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
rtc_sleep_pu(pu_cfg);
}
if (cfg.wifi_pd_en) {
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
} else {