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Merge branch 'bugfix/spiram_reserve_size_pr5373' into 'master'

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SPIRAM reserved memory size fixes

Closes IDFGH-3407 and IDFGH-3931

See merge request espressif/esp-idf!9185
This commit is contained in:
Angus Gratton 2020-09-21 12:27:00 +08:00
commit 5004812dd6
7 changed files with 52 additions and 42 deletions
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6
components/esp32/spiram.c
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@ -74,10 +74,10 @@ size_t __attribute__((weak)) esp_himem_reserved_area_size(void) {
} }
static int spiram_size_usable_for_malloc(void) static size_t spiram_size_usable_for_malloc(void)
{ {
int s=esp_spiram_get_size(); /* SPIRAM chip may be larger than the size we can map into address space */
if (s>4*1024*1024) s=4*1024*1024; //we can map at most 4MiB size_t s = MIN(esp_spiram_get_size(), SOC_EXTRAM_DATA_SIZE);
return s - esp_himem_reserved_area_size(); return s - esp_himem_reserved_area_size();
} }

59
components/esp32s2/spiram.c
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@ -50,11 +50,8 @@ static const char* TAG = "spiram";
#define PSRAM_SPEED PSRAM_CACHE_S20M #define PSRAM_SPEED PSRAM_CACHE_S20M
#endif #endif
#define SPIRAM_SIZE esp_spiram_get_size()
static bool spiram_inited=false; static bool spiram_inited=false;
/* /*
Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns Simple RAM test. Writes a word every 32 bytes. Takes about a second to complete for 4MiB. Returns
true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
@ -62,16 +59,17 @@ static bool spiram_inited=false;
*/ */
bool esp_spiram_test(void) bool esp_spiram_test(void)
{ {
volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - SPIRAM_SIZE); size_t spiram_size = esp_spiram_get_size();
volatile int *spiram=(volatile int*)(SOC_EXTRAM_DATA_HIGH - spiram_size);
size_t p; size_t p;
size_t s=SPIRAM_SIZE; size_t s = spiram_size;
int errct=0; int errct=0;
int initial_err=-1; int initial_err=-1;
if ((SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) < SPIRAM_SIZE) { if (SOC_EXTRAM_DATA_SIZE < spiram_size) {
ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH); ESP_EARLY_LOGW(TAG, "Only test spiram from %08x to %08x\n", SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH);
spiram=(volatile int*)SOC_EXTRAM_DATA_LOW; spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
s = SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW; s = SOC_EXTRAM_DATA_SIZE;
} }
for (p=0; p<(s/sizeof(int)); p+=8) { for (p=0; p<(s/sizeof(int)); p+=8) {
spiram[p]=p^0xAAAAAAAA; spiram[p]=p^0xAAAAAAAA;
@ -100,12 +98,12 @@ bool esp_spiram_test(void)
#define DBUS3_ONLY_CACHE_SIZE BUS_AHB_DBUS3_CACHE_SIZE #define DBUS3_ONLY_CACHE_SIZE BUS_AHB_DBUS3_CACHE_SIZE
#define DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE (DRAM0_DRAM1_DPORT_CACHE_SIZE + DBUS3_ONLY_CACHE_SIZE) #define DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE (DRAM0_DRAM1_DPORT_CACHE_SIZE + DBUS3_ONLY_CACHE_SIZE)
#define SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT (SPIRAM_SIZE - DRAM0_DRAM1_DPORT_CACHE_SIZE) #define SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT (spiram_size - DRAM0_DRAM1_DPORT_CACHE_SIZE)
#define SPIRAM_SIZE_EXC_DATA_CACHE (SPIRAM_SIZE - DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) #define SPIRAM_SIZE_EXC_DATA_CACHE (spiram_size - DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE)
#define SPIRAM_SMALL_SIZE_MAP_VADDR (DRAM0_CACHE_ADDRESS_HIGH - SPIRAM_SIZE) #define SPIRAM_SMALL_SIZE_MAP_VADDR (DRAM0_CACHE_ADDRESS_HIGH - spiram_size)
#define SPIRAM_SMALL_SIZE_MAP_PADDR 0 #define SPIRAM_SMALL_SIZE_MAP_PADDR 0
#define SPIRAM_SMALL_SIZE_MAP_SIZE SPIRAM_SIZE #define SPIRAM_SMALL_SIZE_MAP_SIZE spiram_size
#define SPIRAM_MID_SIZE_MAP_VADDR (AHB_DBUS3_ADDRESS_HIGH - SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT) #define SPIRAM_MID_SIZE_MAP_VADDR (AHB_DBUS3_ADDRESS_HIGH - SPIRAM_SIZE_EXC_DRAM0_DRAM1_DPORT)
#define SPIRAM_MID_SIZE_MAP_PADDR 0 #define SPIRAM_MID_SIZE_MAP_PADDR 0
@ -121,23 +119,24 @@ bool esp_spiram_test(void)
void IRAM_ATTR esp_spiram_init_cache(void) void IRAM_ATTR esp_spiram_init_cache(void)
{ {
size_t spiram_size = esp_spiram_get_size();
Cache_Suspend_DCache(); Cache_Suspend_DCache();
/* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */ /* map the address from SPIRAM end to the start, map the address in order: DRAM1, DRAM1, DPORT, DBUS3 */
if (SPIRAM_SIZE <= DRAM0_ONLY_CACHE_SIZE) { if (spiram_size <= DRAM0_ONLY_CACHE_SIZE) {
/* cache size <= 3MB + 512 KB, only map DRAM0 bus */ /* cache size <= 3MB + 512 KB, only map DRAM0 bus */
Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0); REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM0);
} else if (SPIRAM_SIZE <= DRAM0_DRAM1_CACHE_SIZE) { } else if (spiram_size <= DRAM0_DRAM1_CACHE_SIZE) {
/* cache size <= 7MB + 512KB, only map DRAM0 and DRAM1 bus */ /* cache size <= 7MB + 512KB, only map DRAM0 and DRAM1 bus */
Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0); REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0);
} else if (SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE) { } else if (spiram_size <= DRAM0_DRAM1_DPORT_CACHE_SIZE) {
/* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */
Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0); Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_SMALL_SIZE_MAP_VADDR, SPIRAM_SMALL_SIZE_MAP_PADDR, 64, SPIRAM_SMALL_SIZE_MAP_SIZE >> 16, 0);
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT); REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, EXTMEM_PRO_DCACHE_MASK_DRAM1 | EXTMEM_PRO_DCACHE_MASK_DRAM0 | EXTMEM_PRO_DCACHE_MASK_DPORT);
} else { } else {
#if CONFIG_SPIRAM_USE_AHB_DBUS3// TODO Ready to remove this macro esp32s2 no AHB bus access cache #if CONFIG_SPIRAM_USE_AHB_DBUS3// TODO Ready to remove this macro esp32s2 no AHB bus access cache
if (SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) { if (spiram_size <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) {
/* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */
Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0); Cache_Dbus_MMU_Set(MMU_ACCESS_SPIRAM, SPIRAM_MID_SIZE_MAP_VADDR, SPIRAM_MID_SIZE_MAP_PADDR, 64, SPIRAM_MID_SIZE_MAP_SIZE >> 16, 0);
} else { } else {
@ -156,8 +155,6 @@ void IRAM_ATTR esp_spiram_init_cache(void)
} }
static uint32_t pages_for_flash = 0; static uint32_t pages_for_flash = 0;
static uint32_t page0_mapped = 0;
static uint32_t page0_page = INVALID_PHY_PAGE;
static uint32_t instrcution_in_spiram = 0; static uint32_t instrcution_in_spiram = 0;
static uint32_t rodata_in_spiram = 0; static uint32_t rodata_in_spiram = 0;
@ -173,6 +170,11 @@ static uint32_t rodata_start_page = 0;
static uint32_t rodata_end_page = 0; static uint32_t rodata_end_page = 0;
#endif #endif
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA
static uint32_t page0_mapped = 0;
static uint32_t page0_page = INVALID_PHY_PAGE;
#endif
uint32_t esp_spiram_instruction_access_enabled(void) uint32_t esp_spiram_instruction_access_enabled(void)
{ {
return instrcution_in_spiram; return instrcution_in_spiram;
@ -186,11 +188,12 @@ uint32_t esp_spiram_rodata_access_enabled(void)
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
esp_err_t esp_spiram_enable_instruction_access(void) esp_err_t esp_spiram_enable_instruction_access(void)
{ {
size_t spiram_size = esp_spiram_get_size();
uint32_t pages_in_flash = 0; uint32_t pages_in_flash = 0;
pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS0, &page0_mapped);
pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_IBUS1, &page0_mapped);
if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { if ((pages_in_flash + pages_for_flash) > (spiram_size >> 16)) {
ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (SPIRAM_SIZE >> 16), (pages_in_flash + pages_for_flash)); ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the instructions, has %d pages, need %d pages.", (spiram_size >> 16), (pages_in_flash + pages_for_flash));
return ESP_FAIL; return ESP_FAIL;
} }
ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM"); ESP_EARLY_LOGI(TAG, "Instructions copied and mapped to SPIRAM");
@ -215,7 +218,7 @@ esp_err_t esp_spiram_enable_rodata_access(void)
pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS1, &page0_mapped);
pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped); pages_in_flash += Cache_Count_Flash_Pages(PRO_CACHE_DBUS2, &page0_mapped);
if ((pages_in_flash + pages_for_flash) > (SPIRAM_SIZE >> 16)) { if ((pages_in_flash + pages_for_flash) > (esp_spiram_get_size() >> 16)) {
ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data."); ESP_EARLY_LOGE(TAG, "SPI RAM space not enough for the read only data.");
return ESP_FAIL; return ESP_FAIL;
} }
@ -301,15 +304,18 @@ esp_err_t esp_spiram_init(void)
} }
spiram_inited = true; spiram_inited = true;
size_t spiram_size = esp_spiram_get_size();
#if (CONFIG_SPIRAM_SIZE != -1) #if (CONFIG_SPIRAM_SIZE != -1)
if (esp_spiram_get_size()!=CONFIG_SPIRAM_SIZE) { if (spiram_size != CONFIG_SPIRAM_SIZE) {
ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE/1024, esp_spiram_get_size()/1024); ESP_EARLY_LOGE(TAG, "Expected %dKiB chip but found %dKiB chip. Bailing out..", CONFIG_SPIRAM_SIZE/1024, spiram_size/1024);
return ESP_ERR_INVALID_SIZE; return ESP_ERR_INVALID_SIZE;
} }
#endif #endif
ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device", ESP_EARLY_LOGI(TAG, "Found %dMBit SPI RAM device",
(esp_spiram_get_size()*8)/(1024*1024)); (spiram_size*8)/(1024*1024));
ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : \ ESP_EARLY_LOGI(TAG, "SPI RAM mode: %s", PSRAM_SPEED == PSRAM_CACHE_S40M ? "sram 40m" : \
PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m"); PSRAM_SPEED == PSRAM_CACHE_S80M ? "sram 80m" : "sram 20m");
ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \ ESP_EARLY_LOGI(TAG, "PSRAM initialized, cache is in %s mode.", \
@ -322,17 +328,18 @@ esp_err_t esp_spiram_init(void)
esp_err_t esp_spiram_add_to_heapalloc(void) esp_err_t esp_spiram_add_to_heapalloc(void)
{ {
size_t spiram_size = esp_spiram_get_size();
uint32_t size_for_flash = (pages_for_flash << 16); uint32_t size_for_flash = (pages_for_flash << 16);
ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (SPIRAM_SIZE - (pages_for_flash << 16))/1024); ESP_EARLY_LOGI(TAG, "Adding pool of %dK of external SPI memory to heap allocator", (spiram_size - (pages_for_flash << 16))/1024);
//Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's //Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
//no need to explicitly specify them. //no need to explicitly specify them.
if (SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_CACHE_SIZE) { if (spiram_size <= DRAM0_DRAM1_DPORT_CACHE_SIZE) {
/* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */ /* cache size <= 10MB + 512KB, map DRAM0, DRAM1, DPORT bus */
return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1); return heap_caps_add_region((intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_SMALL_SIZE_MAP_VADDR + SPIRAM_SMALL_SIZE_MAP_SIZE -1);
} else { } else {
#if CONFIG_SPIRAM_USE_AHB_DBUS3 //TODO #if CONFIG_SPIRAM_USE_AHB_DBUS3 //TODO
if (SPIRAM_SIZE <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) { if (spiram_size <= DRAM0_DRAM1_DPORT_DBUS3_CACHE_SIZE) {
/* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */ /* cache size <= 14MB + 512KB, map DRAM0, DRAM1, DPORT bus, as well as data bus3 */
if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) { if (size_for_flash <= SPIRAM_MID_SIZE_MAP_SIZE) {
esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1); esp_err_t err = heap_caps_add_region((intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + size_for_flash, (intptr_t)SPIRAM_MID_SIZE_MAP_VADDR + SPIRAM_MID_SIZE_MAP_SIZE -1);

2
components/soc/soc/esp32/include/soc/soc.h
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@ -256,6 +256,8 @@
#define SOC_EXTRAM_DATA_LOW 0x3F800000 #define SOC_EXTRAM_DATA_LOW 0x3F800000
#define SOC_EXTRAM_DATA_HIGH 0x3FC00000 #define SOC_EXTRAM_DATA_HIGH 0x3FC00000
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x400A0000 #define SOC_DIRAM_IRAM_LOW 0x400A0000
#define SOC_DIRAM_IRAM_HIGH 0x400C0000 #define SOC_DIRAM_IRAM_HIGH 0x400C0000

2
components/soc/soc/esp32s2/include/soc/soc.h
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@ -270,6 +270,8 @@
#define SOC_EXTRAM_DATA_LOW 0x3F500000 #define SOC_EXTRAM_DATA_LOW 0x3F500000
#define SOC_EXTRAM_DATA_HIGH 0x3FF80000 #define SOC_EXTRAM_DATA_HIGH 0x3FF80000
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40020000 #define SOC_DIRAM_IRAM_LOW 0x40020000
#define SOC_DIRAM_IRAM_HIGH 0x40070000 #define SOC_DIRAM_IRAM_HIGH 0x40070000

2
components/soc/soc/esp32s3/include/soc/soc.h
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@ -248,6 +248,8 @@
#define SOC_IROM_MASK_LOW 0x40000000 #define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x4001A100 #define SOC_IROM_MASK_HIGH 0x4001A100
#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
#define SOC_DIRAM_IRAM_LOW 0x40378000 #define SOC_DIRAM_IRAM_LOW 0x40378000
#define SOC_DIRAM_IRAM_HIGH 0x403E0000 #define SOC_DIRAM_IRAM_HIGH 0x403E0000

13
components/soc/src/esp32/soc_memory_layout.c
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@ -74,13 +74,6 @@ const soc_memory_type_desc_t soc_memory_types[] = {
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t); const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
#if CONFIG_SPIRAM_SIZE == -1
// Assume we need to reserve 4MB in the auto-detection case
#define RESERVE_SPIRAM_SIZE (4*1024*1024)
#else
#define RESERVE_SPIRAM_SIZE CONFIG_SPIRAM_SIZE
#endif
/* /*
Region descriptors. These describe all regions of memory available, and map them to a type in the above type. Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
@ -92,7 +85,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory { SOC_RTC_DRAM_LOW, 0x2000, 16, 0}, //RTC Fast Memory
#endif #endif
#ifdef CONFIG_SPIRAM #ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, RESERVE_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 15, 0}, //SPI SRAM, if available
#endif #endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code { 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory { 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
@ -183,7 +176,9 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
#endif #endif
#ifdef CONFIG_SPIRAM #ifdef CONFIG_SPIRAM
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + RESERVE_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now /* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
* memory to heap depending on the actual SPIRAM chip size. */
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, spi_ram);
#endif #endif
extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end;

6
components/soc/src/esp32s2/soc_memory_layout.c
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@ -74,7 +74,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ SOC_RTC_DRAM_LOW, 0x2000, 5, 0}, //RTC Fast Memory { SOC_RTC_DRAM_LOW, 0x2000, 5, 0}, //RTC Fast Memory
#endif #endif
#ifdef CONFIG_SPIRAM #ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available
#endif #endif
#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
#if CONFIG_ESP32S2_DATA_CACHE_0KB #if CONFIG_ESP32S2_DATA_CACHE_0KB
@ -138,7 +138,9 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code); SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start - I_D_OFFSET, (intptr_t)&_iram_end - I_D_OFFSET, iram_code);
#ifdef CONFIG_SPIRAM #ifdef CONFIG_SPIRAM
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region); //SPI RAM gets added later if needed, in spiram.c; reserve it for now /* Reserve the whole possible SPIRAM region here, spiram.c will add some or all of this
* memory to heap depending on the actual SPIRAM chip size. */
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_data_region);
#endif #endif
// Blocks 19 and 20 may be reserved for the trace memory // Blocks 19 and 20 may be reserved for the trace memory