From 4f603017bdc97fd94ab515693e08d388316da4b0 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Wed, 8 Nov 2017 21:13:02 +0800 Subject: [PATCH] soc/rtc: raise core voltage when 80MHz flash frequency is used To achieve reliable operation with GD flash at 80MHz, need to raise core voltage. This causes the following current consumption increase: At 80MHz: from 29mA to 33mA At 160MHz: from 41mA to 47mA Test conditions: 2 cores running code from IRAM, remaining peripherals clock gated. --- components/soc/esp32/rtc_clk.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index 981038633d..d8c0b7328a 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -83,6 +83,20 @@ static const char* TAG = "rtc_clk"; */ #define XTAL_FREQ_EST_CYCLES 10 +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + */ +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + + static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias) { @@ -228,6 +242,8 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq) uint8_t bw; if (cpu_freq != RTC_CPU_FREQ_240M) { + /* Raise the voltage, if needed */ + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M); /* Configure 320M PLL */ switch (xtal_freq) { case RTC_XTAL_FREQ_40M: @@ -267,7 +283,7 @@ void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_cpu_freq_t cpu_freq) I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_320M); } else { /* Raise the voltage */ - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V25); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); ets_delay_us(DELAY_PLL_DBIAS_RAISE); /* Configure 480M PLL */ switch (xtal_freq) { @@ -323,7 +339,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) { rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get(); /* Switch CPU to XTAL frequency first */ - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL); REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); ets_update_cpu_frequency(xtal_freq); @@ -354,7 +370,7 @@ void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq) ets_update_cpu_frequency(2); rtc_clk_apb_freq_update(2 * MHZ); /* lower the voltage */ - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DBIAS_1V00); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M); } else { /* use PLL as clock source */ CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,