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ulp-riscv: made ulp_riscv_delay_cycles more accurate

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This commit is contained in:
Marius Vikhammer 2022-07-25 14:02:23 +08:00
parent b823831a26
commit 4f1046a292
2 changed files with 10 additions and 10 deletions
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11
components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h
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@ -94,7 +94,16 @@ void ulp_riscv_timer_resume(void);
* *
* @param cycles Number of cycles to busy wait * @param cycles Number of cycles to busy wait
*/ */
void ulp_riscv_delay_cycles(uint32_t cycles); void static inline ulp_riscv_delay_cycles(uint32_t cycles)
{
uint32_t start = ULP_RISCV_GET_CCOUNT();
/* Off with an estimate of cycles in this function to improve accuracy */
uint32_t end = start + cycles - 20;
while (ULP_RISCV_GET_CCOUNT() < end) {
/* Wait */
}
}
/** /**
* @brief Clears the GPIO wakeup interrupt bit * @brief Clears the GPIO wakeup interrupt bit

9
components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c
View File

@ -35,15 +35,6 @@ void ulp_riscv_halt(void)
while(1); while(1);
} }
void ulp_riscv_delay_cycles(uint32_t cycles)
{
uint32_t start = ULP_RISCV_GET_CCOUNT();
while ((ULP_RISCV_GET_CCOUNT() - start) < cycles) {
/* Wait */
}
}
void ulp_riscv_timer_stop(void) void ulp_riscv_timer_stop(void)
{ {
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);